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375 lines
12 KiB
375 lines
12 KiB
/**
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******************************************************************************
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* @file EEPROM_Emul/Porting/STM32WB/flash_interface.c
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* @author MCD Application Team
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* @brief This file provides all the EEPROM emulation flash interface functions.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "eeprom_emul.h"
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#include "flash_interface.h"
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#include "stm32wbxx_nucleo.h"
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/** @addtogroup EEPROM_Emulation
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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#ifdef DUALCORE_FLASH_SHARING
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#define HSEM_PROCESS_1 12U /* Number taken randomly to identify the process locking a semaphore in the driver context */
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#endif
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup EEPROM_Private_Functions
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* @{
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*/
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#ifdef DUALCORE_FLASH_SHARING
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/**
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* @brief Write a double word at the given address in Flash
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* @param Address Where to write
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* @param Data What to write
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* @param Write_type Type of writing on going (see EE_Write_type)
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* @retval EE_Status
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* - EE_OK: on success
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* - EE_WRITE_ERROR: if an error occurs
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* - EE_FLASH_USED: flash currently used by CPU2
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*/
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EE_Status FI_WriteDoubleWord(uint32_t Address, uint64_t Data, EE_Write_type Write_type)
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{
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EE_Status ee_status = EE_OK;
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/* We enter a critical section */
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UTILS_ENTER_CRITICAL_SECTION();
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/* When the ongoing writing operation is a direct one (no transfer is required,
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we are not in init process, and we do not write the state of a page) */
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if(Write_type == EE_SIMPLE_WRITE)
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{
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/* Wait for the semaphore to be free */
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while( HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) );
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/* Take the HW 7 semaphore */
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if(HAL_HSEM_Take(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1) == HAL_OK)
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{
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if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, Data) != HAL_OK)
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{
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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ee_status = EE_WRITE_ERROR;
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}
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/* Release the HW Semaphore */
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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ee_status = EE_OK;
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}
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else
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{
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/* If flash is used by CPU2, the semaphore release interrupt is activated so as to raise a notification when
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the semaphore will be unlocked (user can do other operations while waiting) */
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HAL_HSEM_ActivateNotification(__HAL_HSEM_SEMID_TO_MASK(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID));
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ee_status = EE_FLASH_USED;
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}
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}
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/* This is when the function call comes from a writing operation other than a direct one */
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else
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{
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/* Wait for the semaphore 7 to be free and take it when it is */
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while(HAL_HSEM_Take(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1) != HAL_OK)
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{
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while( HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) ) ;
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}
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if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, Data) != HAL_OK)
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{
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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ee_status = EE_WRITE_ERROR;
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}
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/* Release the HW Semaphore */
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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ee_status = EE_OK;
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}
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/* We exit the critical section */
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UTILS_EXIT_CRITICAL_SECTION();
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return ee_status;
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}
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#else
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/**
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* @brief Write a double word at the given address in Flash
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* @param Address Where to write
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* @param Data What to write
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* @retval EE_Status
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* - EE_OK: on success
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* - EE_WRITE_ERROR: if an error occurs
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*/
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HAL_StatusTypeDef FI_WriteDoubleWord(uint32_t Address, uint64_t Data)
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{
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return HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, Data);
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}
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#endif
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/**
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* @brief Erase a page in polling mode
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* @param Page Page number
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* @param NbPages Number of pages to erase
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* @retval EE_Status
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* - EE_OK: on success
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* - EE error code: if an error occurs
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*/
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EE_Status FI_PageErase(uint32_t Page, uint16_t NbPages)
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{
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EE_Status status = EE_OK;
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#ifdef DUALCORE_FLASH_SHARING
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/* Wait for last operation to be completed */
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) ;
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/* Because we want to share flash between CPU1 and 2, we erase each page individually
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* and we take then release the associated semaphore for each page erasings.
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* By doing this, we allow CPU2 to do urgent works between page erasings. */
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for (uint32_t index = Page; index < (Page + NbPages); index++)
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{
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/* We enter a critical section */
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UTILS_ENTER_CRITICAL_SECTION();
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/* Wait for the semaphore 7 to be free and take it when it is */
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while(HAL_HSEM_Take(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1) != HAL_OK)
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{
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while( HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) ) ;
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}
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/* Start erase page */
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FLASH_PageErase(index);
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/* Release the HW Semaphore */
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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/* We exit the critical section */
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UTILS_EXIT_CRITICAL_SECTION();
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/* Wait for last operation to be completed */
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) ;
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}
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/* If operation is completed or interrupted, disable the Page Erase Bit */
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CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
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/* Flush the caches to be sure of the data consistency */
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/* Flush instruction cache */
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if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN)
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{
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/* Disable instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
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/* Reset instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_RESET();
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/* Enable instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
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}
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/* Flush data cache */
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if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN)
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{
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/* Disable data cache */
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__HAL_FLASH_DATA_CACHE_DISABLE();
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/* Reset data cache */
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__HAL_FLASH_DATA_CACHE_RESET();
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/* Enable data cache */
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__HAL_FLASH_DATA_CACHE_ENABLE();
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}
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#else
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FLASH_EraseInitTypeDef s_eraseinit;
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uint32_t page_error = 0U;
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s_eraseinit.TypeErase = FLASH_TYPEERASE_PAGES;
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s_eraseinit.NbPages = NbPages;
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s_eraseinit.Page = Page;
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/* Erase the Page: Set Page status to ERASED status */
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if (HAL_FLASHEx_Erase(&s_eraseinit, &page_error) != HAL_OK)
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{
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status = EE_ERASE_ERROR;
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}
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#endif
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return status;
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}
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/**
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* @brief Erase a page with interrupt enabled
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* @param Page Page number
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* @param NbPages Number of pages to erase
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* @retval EE_Status
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* - EE_OK: on success
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* - EE error code: if an error occurs
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*/
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EE_Status FI_PageErase_IT(uint32_t Page, uint16_t NbPages)
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{
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EE_Status status = EE_OK;
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FLASH_EraseInitTypeDef s_eraseinit;
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s_eraseinit.TypeErase = FLASH_TYPEERASE_PAGES;
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s_eraseinit.NbPages = NbPages;
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s_eraseinit.Page = Page;
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#ifdef DUALCORE_FLASH_SHARING
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/* We enter a critical section */
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UTILS_ENTER_CRITICAL_SECTION();
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/* Wait for the semaphore 7 to be free and take it when it is */
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while(HAL_HSEM_Take(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1) != HAL_OK)
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{
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while( HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) ) ;
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}
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#endif
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/* Erase the Page: Set Page status to ERASED status */
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if (HAL_FLASHEx_Erase_IT(&s_eraseinit) != HAL_OK)
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{
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status = EE_ERASE_ERROR;
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}
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#ifdef DUALCORE_FLASH_SHARING
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/* Release the HW Semaphore */
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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/* We exit the critical section */
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UTILS_EXIT_CRITICAL_SECTION();
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#endif
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return status;
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}
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/**
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* @brief Flush the caches if needed to keep coherency when the flash content is modified
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*/
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void FI_CacheFlush()
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{
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/* To keep its coherency, flush the D-Cache: its content is not updated after a flash erase. */
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__HAL_FLASH_DATA_CACHE_DISABLE();
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__HAL_FLASH_DATA_CACHE_RESET();
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__HAL_FLASH_DATA_CACHE_ENABLE();
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}
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/**
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* @brief Delete corrupted Flash address, can be called from NMI. No Timeout.
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* @param Address Address of the FLASH Memory to delete
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* @retval EE_Status
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* - EE_OK: on success
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* - EE error code: if an error occurs
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*/
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EE_Status FI_DeleteCorruptedFlashAddress(uint32_t Address)
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{
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EE_Status status = EE_OK;
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/* Set FLASH Programmation bit */
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SET_BIT(FLASH->CR, FLASH_CR_PG);
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#ifdef DUALCORE_FLASH_SHARING
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/* We enter a critical section */
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UTILS_ENTER_CRITICAL_SECTION();
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/* Wait for the semaphore 7 to be free and take it when it is */
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while(HAL_HSEM_Take(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1) != HAL_OK)
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{
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while( HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) ) ;
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}
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#endif
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/* Program double word of value 0 */
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*(__IO uint32_t*)(Address) = (uint32_t)0U;
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*(__IO uint32_t*)(Address+4U) = (uint32_t)0U;
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#ifdef DUALCORE_FLASH_SHARING
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/* Release the HW Semaphore */
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, HSEM_PROCESS_1);
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/* We exit the critical section */
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UTILS_EXIT_CRITICAL_SECTION();
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#endif
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/* Wait programmation completion */
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while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) ;
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/* Check if error occured */
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if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) ||
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(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) ||
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(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)))
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{
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status = EE_DELETE_ERROR;
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}
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/* Check FLASH End of Operation flag */
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if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
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{
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/* Clear FLASH End of Operation pending bit */
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
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}
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/* Clear FLASH Programmation bit */
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CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
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/* Clear FLASH ECCD bit */
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCD);
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return status;
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}
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/**
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* @brief Check if the configuration is 128-bits bank or 2*64-bits bank
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* @param None
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* @retval EE_Status
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* - EE_OK: on success
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* - EE error code: if an error occurs
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*/
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EE_Status FI_CheckBankConfig(void)
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{
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#if defined (FLASH_OPTR_DBANK)
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FLASH_OBProgramInitTypeDef sOBCfg;
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EE_Status status;
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/* Request the Option Byte configuration :
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- User and RDP level are always returned
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- WRP and PCROP are not requested */
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sOBCfg.WRPArea = 0xFF;
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sOBCfg.PCROPConfig = 0xFF;
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HAL_FLASHEx_OBGetConfig(&sOBCfg);
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/* Check the value of the DBANK user option byte */
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if ((sOBCfg.USERConfig & OB_DBANK_64_BITS) != 0)
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{
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status = EE_OK;
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}
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else
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{
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status = EE_INVALID_BANK_CFG;
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}
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return status;
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#else
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/* No feature 128-bits single bank, so always 64-bits dual bank */
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return EE_OK;
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#endif
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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