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timer based ADC triggering

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This commit is contained in:
MightyPork
2023-03-12 21:48:32 +01:00
parent bff7f6e916
commit 091d6c5648
14 changed files with 104 additions and 60 deletions
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Core/Src/adc.c
+3 -7
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@@ -46,7 +46,7 @@ void MX_ADC1_Init(void)
PA0-WKUP ------> ADC1_IN0
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = ADC_PT100_Pin|ADC_SENSR_Pin;
GPIO_InitStruct.Pin = LL_GPIO_PIN_0|ADC_SENSR_Pin;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -67,10 +67,6 @@ void MX_ADC1_Init(void)
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD);
/* ADC1 interrupt Init */
NVIC_SetPriority(ADC1_2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_EnableIRQ(ADC1_2_IRQn);
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
@@ -82,10 +78,10 @@ void MX_ADC1_Init(void)
LL_ADC_Init(ADC1, &ADC_InitStruct);
ADC_CommonInitStruct.Multimode = LL_ADC_MULTI_INDEPENDENT;
LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_EXT_TIM1_CH1;
ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS;
ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_CONTINUOUS;
ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
Core/Src/app_heater.c
+1 -1
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@@ -109,6 +109,6 @@ void app_task_heater(void *argument)
// TODO notify UI thread of the new temperature and heating percent
vTaskDelayUntil(&wake_time, pdMS_TO_TICKS(500));
vTaskDelayUntil(&wake_time, pdMS_TO_TICKS(100));
}
}
Core/Src/app_temp.c
+12 -4
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@@ -16,8 +16,8 @@ static volatile uint16_t adc_values[4];
const float V_REFINT = 1.23f;
#define AVERAGEBUF_DEPTH 16
#define OVENTEMP_HISTORY_DEPTH 10
#define AVERAGEBUF_DEPTH 8
#define OVENTEMP_HISTORY_DEPTH 5
static struct App {
float oven_temp;
@@ -156,7 +156,14 @@ void app_analog_init()
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
LL_ADC_REG_StartConversionExtTrig(ADC_TEMP, LL_ADC_REG_TRIG_EXT_RISING);
LL_ADC_REG_StartConversionSWStart(ADC_TEMP);
// LL_ADC_REG_StartConversionSWStart(ADC_TEMP);
LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_CC1IF);
LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH1);
LL_TIM_OC_SetCompareCH1(TIM1, 10);
LL_TIM_SetAutoReload(TIM1, 20);
LL_TIM_EnableAllOutputs(TIM1);
LL_TIM_EnableCounter(TIM1);
}
static float val_to_c(float val)
@@ -241,7 +248,8 @@ float app_temp_read_soc()
void app_temp_adc_eos()
{
PUTCHAR('a');
//PUTCHAR('a');
// notify
memcpy((void *) &s_analog.adc_averagebuf[s_analog.averagebuf_ptr * 4], (const void *) adc_values, 4 * sizeof(uint16_t));
s_analog.averagebuf_ptr = (s_analog.averagebuf_ptr + 1) % AVERAGEBUF_DEPTH;
Core/Src/freertos.c
+1 -1
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@@ -223,7 +223,7 @@ void MX_FREERTOS_Init(void) {
* @retval None
*/
/* USER CODE END Header_app_task_main */
__attribute__((weak)) void app_task_main(void *argument)
__weak void app_task_main(void *argument)
{
/* USER CODE BEGIN app_task_main */
/* Infinite loop */
Core/Src/main.c
+1
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@@ -118,6 +118,7 @@ int main(void)
MX_TIM2_Init();
MX_TIM3_Init();
MX_SPI2_Init();
MX_TIM1_Init();
/* USER CODE BEGIN 2 */
PUTS("Start.\r\n");
Core/Src/stm32f1xx_it.c
-21
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@@ -206,27 +206,6 @@ void DMA1_Channel1_IRQHandler(void)
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
/**
* @brief This function handles ADC1 and ADC2 global interrupts.
*/
void ADC1_2_IRQHandler(void)
{
/* USER CODE BEGIN ADC1_2_IRQn 0 */
// app_temp_adc_eos();
// if (LL_ADC_IsActiveFlag_EOS(ADC_TEMP)) {
// LL_ADC_ClearFlag_EOS(ADC_TEMP);
// app_temp_adc_eos();
// }
/* USER CODE END ADC1_2_IRQn 0 */
/* USER CODE BEGIN ADC1_2_IRQn 1 */
/* USER CODE END ADC1_2_IRQn 1 */
}
/**
* @brief This function handles TIM4 global interrupt.
*/
Core/Src/tim.c
+52
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@@ -24,6 +24,58 @@
/* USER CODE END 0 */
/* TIM1 init function */
void MX_TIM1_Init(void)
{
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
LL_TIM_InitTypeDef TIM_InitStruct = {0};
LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};
/* Peripheral clock enable */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
TIM_InitStruct.Prescaler = 64000;
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct.Autoreload = 100;
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct.RepetitionCounter = 0;
LL_TIM_Init(TIM1, &TIM_InitStruct);
LL_TIM_DisableARRPreload(TIM1);
LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH1);
TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1;
TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
TIM_OC_InitStruct.CompareValue = 0;
TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
TIM_OC_InitStruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);
LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH1);
LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_OC1REF);
LL_TIM_DisableMasterSlaveMode(TIM1);
TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;
TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;
TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;
TIM_BDTRInitStruct.DeadTime = 0;
TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;
TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;
TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
LL_TIM_BDTR_Init(TIM1, &TIM_BDTRInitStruct);
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
/* TIM2 init function */
void MX_TIM2_Init(void)
{
Core/Src/usart.c
-1
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@@ -73,6 +73,5 @@ void MX_USART1_UART_Init(void)
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */