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107 lines
2.3 KiB
107 lines
2.3 KiB
2 years ago
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/*
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* Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------
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* Project: CMSIS NN Library
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* Title: arm_relu_q15.c
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* Description: Q15 version of ReLU
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*
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* $Date: 17. January 2018
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* $Revision: V.1.0.0
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*
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* Target Processor: Cortex-M cores
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*
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_nnfunctions.h"
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/**
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* @ingroup groupNN
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*/
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/**
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* @addtogroup Acti
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* @{
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*/
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/**
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* @brief Q15 RELU function
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* @param[in,out] data pointer to input
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* @param[in] size number of elements
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* @return none.
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*
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* @details
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*
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* Optimized relu with QSUB instructions.
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*
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*/
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void arm_relu_q15(q15_t * data, uint16_t size)
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{
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#if defined (ARM_MATH_DSP)
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/* Run the following code for Cortex-M4 and Cortex-M7 */
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uint16_t i = size >> 1;
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q15_t *pIn = data;
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q15_t *pOut = data;
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q31_t in;
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q31_t buf;
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q31_t mask;
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while (i)
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{
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in = *__SIMD32(pIn)++;
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/* extract the first bit */
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buf = __ROR(in & 0x80008000, 15);
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/* if MSB=1, mask will be 0xFF, 0x0 otherwise */
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mask = __QSUB16(0x00000000, buf);
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*__SIMD32(pOut)++ = in & (~mask);
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i--;
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}
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if (size & 0x1)
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{
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if (*pIn < 0)
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{
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*pIn = 0;
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}
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pIn++;
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}
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#else
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/* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
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uint16_t i;
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for (i = 0; i < size; i++)
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{
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if (data[i] < 0)
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data[i] = 0;
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}
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#endif /* ARM_MATH_DSP */
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}
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/**
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* @} end of Acti group
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*/
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