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1059 lines
35 KiB
1059 lines
35 KiB
/**
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******************************************************************************
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* @file stm8s_clk.h
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* @author MCD Application Team
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* @version V2.2.0
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* @date 30-September-2014
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* @brief This file contains all functions prototype and macros for the CLK peripheral.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM8S_CLK_H
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#define __STM8S_CLK_H
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/* Includes ------------------------------------------------------------------*/
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/* Contains the description of all STM8 hardware registers */
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#include "stm8s.h"
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/* Exported types ------------------------------------------------------------*/
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/** @addtogroup CLK_Exported_Types
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* @{
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*/
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/**
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* @brief Switch Mode Auto, Manual.
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*/
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typedef enum {
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CLK_SWITCHMODE_MANUAL = (uint8_t) 0x00, /*!< Enable the manual clock switching mode */
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CLK_SWITCHMODE_AUTO = (uint8_t) 0x01 /*!< Enable the automatic clock switching mode */
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} CLK_SwitchMode_TypeDef;
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/**
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* @brief Current Clock State.
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*/
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typedef enum {
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CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t) 0x00, /*!< Current clock disable */
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CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t) 0x01 /*!< Current clock enable */
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} CLK_CurrentClockState_TypeDef;
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/**
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* @brief Clock security system configuration.
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*/
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typedef enum {
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CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t) 0x05, /*!< Enable CSS with detection interrupt */
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CLK_CSSCONFIG_ENABLE = (uint8_t) 0x01, /*!< Enable CSS without detection interrupt */
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CLK_CSSCONFIG_DISABLE = (uint8_t) 0x00 /*!< Leave CSS desactivated (to be used in CLK_Init() function) */
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} CLK_CSSConfig_TypeDef;
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/**
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* @brief CLK Clock Source.
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*/
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typedef enum {
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CLK_SOURCE_HSI = (uint8_t) 0xE1, /*!< Clock Source HSI. */
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CLK_SOURCE_LSI = (uint8_t) 0xD2, /*!< Clock Source LSI. */
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CLK_SOURCE_HSE = (uint8_t) 0xB4 /*!< Clock Source HSE. */
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} CLK_Source_TypeDef;
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/**
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* @brief CLK HSI Calibration Value.
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*/
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typedef enum {
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CLK_HSITRIMVALUE_0 = (uint8_t) 0x00, /*!< HSI Calibration Value 0 */
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CLK_HSITRIMVALUE_1 = (uint8_t) 0x01, /*!< HSI Calibration Value 1 */
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CLK_HSITRIMVALUE_2 = (uint8_t) 0x02, /*!< HSI Calibration Value 2 */
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CLK_HSITRIMVALUE_3 = (uint8_t) 0x03, /*!< HSI Calibration Value 3 */
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CLK_HSITRIMVALUE_4 = (uint8_t) 0x04, /*!< HSI Calibration Value 4 */
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CLK_HSITRIMVALUE_5 = (uint8_t) 0x05, /*!< HSI Calibration Value 5 */
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CLK_HSITRIMVALUE_6 = (uint8_t) 0x06, /*!< HSI Calibration Value 6 */
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CLK_HSITRIMVALUE_7 = (uint8_t) 0x07 /*!< HSI Calibration Value 7 */
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} CLK_HSITrimValue_TypeDef;
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/**
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* @brief CLK Clock Output
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*/
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typedef enum {
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CLK_OUTPUT_HSI = (uint8_t) 0x00, /*!< Clock Output HSI */
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CLK_OUTPUT_LSI = (uint8_t) 0x02, /*!< Clock Output LSI */
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CLK_OUTPUT_HSE = (uint8_t) 0x04, /*!< Clock Output HSE */
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CLK_OUTPUT_CPU = (uint8_t) 0x08, /*!< Clock Output CPU */
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CLK_OUTPUT_CPUDIV2 = (uint8_t) 0x0A, /*!< Clock Output CPU/2 */
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CLK_OUTPUT_CPUDIV4 = (uint8_t) 0x0C, /*!< Clock Output CPU/4 */
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CLK_OUTPUT_CPUDIV8 = (uint8_t) 0x0E, /*!< Clock Output CPU/8 */
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CLK_OUTPUT_CPUDIV16 = (uint8_t) 0x10, /*!< Clock Output CPU/16 */
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CLK_OUTPUT_CPUDIV32 = (uint8_t) 0x12, /*!< Clock Output CPU/32 */
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CLK_OUTPUT_CPUDIV64 = (uint8_t) 0x14, /*!< Clock Output CPU/64 */
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CLK_OUTPUT_HSIRC = (uint8_t) 0x16, /*!< Clock Output HSI RC */
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CLK_OUTPUT_MASTER = (uint8_t) 0x18, /*!< Clock Output Master */
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CLK_OUTPUT_OTHERS = (uint8_t) 0x1A /*!< Clock Output OTHER */
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} CLK_Output_TypeDef;
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/**
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* @brief CLK Enable peripheral
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*/
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/* Elements values convention: 0xXY
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X = choice between the peripheral registers
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X = 0 : PCKENR1
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X = 1 : PCKENR2
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Y = Peripheral position in the register
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*/
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typedef enum {
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CLK_PERIPHERAL_I2C = (uint8_t) 0x00, /*!< Peripheral Clock Enable 1, I2C */
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CLK_PERIPHERAL_SPI = (uint8_t) 0x01, /*!< Peripheral Clock Enable 1, SPI */
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#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)
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CLK_PERIPHERAL_UART1 = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, UART1 */
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#else
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CLK_PERIPHERAL_UART1 = (uint8_t) 0x03, /*!< Peripheral Clock Enable 1, UART1 */
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#endif
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CLK_PERIPHERAL_UART2 = (uint8_t) 0x03, /*!< Peripheral Clock Enable 1, UART2 */
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CLK_PERIPHERAL_UART3 = (uint8_t) 0x03, /*!< Peripheral Clock Enable 1, UART3 */
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CLK_PERIPHERAL_TIMER6 = (uint8_t) 0x04, /*!< Peripheral Clock Enable 1, Timer6 */
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CLK_PERIPHERAL_TIMER4 = (uint8_t) 0x04, /*!< Peripheral Clock Enable 1, Timer4 */
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CLK_PERIPHERAL_TIMER5 = (uint8_t) 0x05, /*!< Peripheral Clock Enable 1, Timer5 */
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CLK_PERIPHERAL_TIMER2 = (uint8_t) 0x05, /*!< Peripheral Clock Enable 1, Timer2 */
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CLK_PERIPHERAL_TIMER3 = (uint8_t) 0x06, /*!< Peripheral Clock Enable 1, Timer3 */
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CLK_PERIPHERAL_TIMER1 = (uint8_t) 0x07, /*!< Peripheral Clock Enable 1, Timer1 */
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CLK_PERIPHERAL_AWU = (uint8_t) 0x12, /*!< Peripheral Clock Enable 2, AWU */
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CLK_PERIPHERAL_ADC = (uint8_t) 0x13, /*!< Peripheral Clock Enable 2, ADC */
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CLK_PERIPHERAL_CAN = (uint8_t) 0x17 /*!< Peripheral Clock Enable 2, CAN */
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} CLK_Peripheral_TypeDef;
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/**
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* @brief CLK Flags.
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*/
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/* Elements values convention: 0xXZZ
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X = choice between the flags registers
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X = 1 : ICKR
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X = 2 : ECKR
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X = 3 : SWCR
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X = 4 : CSSR
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X = 5 : CCOR
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ZZ = flag mask in the register (same as map file)
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*/
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typedef enum {
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CLK_FLAG_LSIRDY = (uint16_t) 0x0110, /*!< Low speed internal oscillator ready Flag */
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CLK_FLAG_HSIRDY = (uint16_t) 0x0102, /*!< High speed internal oscillator ready Flag */
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CLK_FLAG_HSERDY = (uint16_t) 0x0202, /*!< High speed external oscillator ready Flag */
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CLK_FLAG_SWIF = (uint16_t) 0x0308, /*!< Clock switch interrupt Flag */
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CLK_FLAG_SWBSY = (uint16_t) 0x0301, /*!< Switch busy Flag */
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CLK_FLAG_CSSD = (uint16_t) 0x0408, /*!< Clock security system detection Flag */
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CLK_FLAG_AUX = (uint16_t) 0x0402, /*!< Auxiliary oscillator connected to master clock */
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CLK_FLAG_CCOBSY = (uint16_t) 0x0504, /*!< Configurable clock output busy */
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CLK_FLAG_CCORDY = (uint16_t) 0x0502 /*!< Configurable clock output ready */
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} CLK_Flag_TypeDef;
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/**
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* @brief CLK interrupt configuration and Flags cleared by software.
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*/
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typedef enum {
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CLK_IT_CSSD = (uint8_t) 0x0C, /*!< Clock security system detection Flag */
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CLK_IT_SWIF = (uint8_t) 0x1C /*!< Clock switch interrupt Flag */
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} CLK_IT_TypeDef;
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/**
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* @brief CLK Clock Divisor.
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*/
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/* Warning:
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0xxxxxx = HSI divider
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1xxxxxx = CPU divider
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Other bits correspond to the divider's bits mapping
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*/
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typedef enum {
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CLK_PRESCALER_HSIDIV1 = (uint8_t) 0x00, /*!< High speed internal clock prescaler: 1 */
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CLK_PRESCALER_HSIDIV2 = (uint8_t) 0x08, /*!< High speed internal clock prescaler: 2 */
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CLK_PRESCALER_HSIDIV4 = (uint8_t) 0x10, /*!< High speed internal clock prescaler: 4 */
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CLK_PRESCALER_HSIDIV8 = (uint8_t) 0x18, /*!< High speed internal clock prescaler: 8 */
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CLK_PRESCALER_CPUDIV1 = (uint8_t) 0x80, /*!< CPU clock division factors 1 */
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CLK_PRESCALER_CPUDIV2 = (uint8_t) 0x81, /*!< CPU clock division factors 2 */
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CLK_PRESCALER_CPUDIV4 = (uint8_t) 0x82, /*!< CPU clock division factors 4 */
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CLK_PRESCALER_CPUDIV8 = (uint8_t) 0x83, /*!< CPU clock division factors 8 */
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CLK_PRESCALER_CPUDIV16 = (uint8_t) 0x84, /*!< CPU clock division factors 16 */
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CLK_PRESCALER_CPUDIV32 = (uint8_t) 0x85, /*!< CPU clock division factors 32 */
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CLK_PRESCALER_CPUDIV64 = (uint8_t) 0x86, /*!< CPU clock division factors 64 */
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CLK_PRESCALER_CPUDIV128 = (uint8_t) 0x87 /*!< CPU clock division factors 128 */
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} CLK_Prescaler_TypeDef;
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/**
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* @brief SWIM Clock divider.
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*/
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typedef enum {
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CLK_SWIMDIVIDER_2 = (uint8_t) 0x00, /*!< SWIM clock is divided by 2 */
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CLK_SWIMDIVIDER_OTHER = (uint8_t) 0x01 /*!< SWIM clock is not divided by 2 */
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} CLK_SWIMDivider_TypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @addtogroup CLK_Exported_Constants
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* @{
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*/
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#define CLK_TIMEOUT ((uint16_t)0xFFFF) /*!< Max Timeout for the clock switch operation. */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup CLK_Private_Macros
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* @{
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*/
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/**
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* @brief Macros used by the assert function in order to check the different functions parameters.
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*/
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/**
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* @brief Macros used by the assert function in order to check the clock switching modes.
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*/
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#define IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))
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/**
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* @brief Macros used by the assert function in order to check the current clock state.
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*/
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#define IS_CLK_CURRENTCLOCKSTATE_OK(STATE) (((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\
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((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))
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/**
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* @brief Macros used by the assert function in order to check the CSS configuration.
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*/
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#define IS_CLK_CSSCONFIG_OK(CSSVALUE) (((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\
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((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\
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((CSSVALUE) == CLK_CSSCONFIG_DISABLE))
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/**
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* @brief Macros used by the assert function in order to check the different clock sources.
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*/
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#define IS_CLK_SOURCE_OK(SOURCE) (((SOURCE) == CLK_SOURCE_HSI) ||\
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((SOURCE) == CLK_SOURCE_LSI) ||\
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((SOURCE) == CLK_SOURCE_HSE))
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/**
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* @brief Macros used by the assert function in order to check the different HSI trimming values.
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*/
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#define IS_CLK_HSITRIMVALUE_OK(TRIMVALUE) (((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\
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((TRIMVALUE) == CLK_HSITRIMVALUE_7))
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/**
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* @brief Macros used by the assert function in order to check the different clocks to output.
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*/
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#define IS_CLK_OUTPUT_OK(OUTPUT) (((OUTPUT) == CLK_OUTPUT_HSI) ||\
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((OUTPUT) == CLK_OUTPUT_HSE) ||\
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((OUTPUT) == CLK_OUTPUT_LSI) ||\
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((OUTPUT) == CLK_OUTPUT_CPU) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\
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((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\
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((OUTPUT) == CLK_OUTPUT_HSIRC) ||\
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((OUTPUT) == CLK_OUTPUT_MASTER) ||\
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((OUTPUT) == CLK_OUTPUT_OTHERS))
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/**
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* @brief Macros used by the assert function in order to check the different peripheral's clock.
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*/
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#define IS_CLK_PERIPHERAL_OK(PERIPHERAL) (((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\
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((PERIPHERAL) == CLK_PERIPHERAL_AWU))
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/**
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* @brief Macros used by the assert function in order to check the different clock flags.
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*/
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#define IS_CLK_FLAG_OK(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
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((FLAG) == CLK_FLAG_HSIRDY) ||\
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((FLAG) == CLK_FLAG_HSERDY) ||\
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((FLAG) == CLK_FLAG_SWIF) ||\
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((FLAG) == CLK_FLAG_SWBSY) ||\
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((FLAG) == CLK_FLAG_CSSD) ||\
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((FLAG) == CLK_FLAG_AUX) ||\
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((FLAG) == CLK_FLAG_CCOBSY) ||\
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((FLAG) == CLK_FLAG_CCORDY))
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/**
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* @brief Macros used by the assert function in order to check the different clock IT pending bits.
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*/
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#define IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))
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/**
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* @brief Macros used by the assert function in order to check the different HSI prescaler values.
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*/
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#define IS_CLK_HSIPRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV8))
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/**
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* @brief Macros used by the assert function in order to check the different clock prescaler values.
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*/
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#define IS_CLK_PRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\
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((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\
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((PRESCALER) == CLK_PRESCALER_CPUDIV128))
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/**
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* @brief Macros used by the assert function in order to check the different SWIM dividers values.
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*/
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#define IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))
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#if 0
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/**
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* @}
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*/
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/** @addtogroup CLK_Exported_functions
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* @{
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*/
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void CLK_DeInit(void);
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void CLK_HSECmd(FunctionalState NewState);
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void CLK_HSICmd(FunctionalState NewState);
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void CLK_LSICmd(FunctionalState NewState);
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void CLK_CCOCmd(FunctionalState NewState);
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void CLK_ClockSwitchCmd(FunctionalState NewState);
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void CLK_FastHaltWakeUpCmd(FunctionalState NewState);
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void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState);
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void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
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ErrorStatus
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CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState,
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CLK_CurrentClockState_TypeDef CLK_CurrentClockState);
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void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler);
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void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO);
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void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
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void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler);
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void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider);
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void CLK_ClockSecuritySystemEnable(void);
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void CLK_SYSCLKEmergencyClear(void);
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void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue);
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uint32_t CLK_GetClockFreq(void);
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CLK_Source_TypeDef CLK_GetSYSCLKSource(void);
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FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG);
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ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
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void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
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#endif
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/** @addtogroup STM8S_StdPeriph_Driver
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private Constants ---------------------------------------------------------*/
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/**
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* @addtogroup CLK_Private_Constants
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* @{
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*/
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//CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}; /*!< Holds the different CLK prescaler values */
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/**
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* @}
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*/
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/* Public functions ----------------------------------------------------------*/
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/**
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* @addtogroup CLK_Public_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the CLK peripheral registers to their default reset
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* values.
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* @param None
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* @retval None
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* @par Warning:
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* Resetting the CCOR register: \n
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* When the CCOEN bit is set, the reset of the CCOR register require
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* two consecutive write instructions in order to reset first the CCOEN bit
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* and the second one is to reset the CCOSEL bits.
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*/
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inline void CLK_DeInit(void)
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{
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CLK->ICKR = CLK_ICKR_RESET_VALUE;
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CLK->ECKR = CLK_ECKR_RESET_VALUE;
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CLK->SWR = CLK_SWR_RESET_VALUE;
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CLK->SWCR = CLK_SWCR_RESET_VALUE;
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CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
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CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
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CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
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CLK->CSSR = CLK_CSSR_RESET_VALUE;
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CLK->CCOR = CLK_CCOR_RESET_VALUE;
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while ((CLK->CCOR & CLK_CCOR_CCOEN) != 0) {}
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CLK->CCOR = CLK_CCOR_RESET_VALUE;
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CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
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CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
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}
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/**
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* @brief Configures the High Speed Internal oscillator (HSI).
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* @par Full description:
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* If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically
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* switched-on (HSIEN=1) and selected as next clock master
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* (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.\n
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* @param NewState this parameter is the Wake-up Mode state.
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* @retval None
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*/
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inline void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
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{
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/* check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set FHWU bit (HSI oscillator is automatically switched-on) */
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CLK->ICKR |= CLK_ICKR_FHWU;
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} else /* FastHaltWakeup = DISABLE */
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{
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/* Reset FHWU bit */
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_FHWU);
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}
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}
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/**
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* @brief Enable or Disable the External High Speed oscillator (HSE).
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* @param NewState new state of HSEEN, value accepted ENABLE, DISABLE.
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* @retval None
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*/
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inline void CLK_HSECmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set HSEEN bit */
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CLK->ECKR |= CLK_ECKR_HSEEN;
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} else {
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/* Reset HSEEN bit */
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CLK->ECKR &= (uint8_t) (~CLK_ECKR_HSEEN);
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}
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}
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/**
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* @brief Enables or disables the Internal High Speed oscillator (HSI).
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* @param NewState new state of HSIEN, value accepted ENABLE, DISABLE.
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* @retval None
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*/
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inline void CLK_HSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set HSIEN bit */
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CLK->ICKR |= CLK_ICKR_HSIEN;
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} else {
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/* Reset HSIEN bit */
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_HSIEN);
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}
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}
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/**
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* @brief Enables or disables the Internal Low Speed oscillator (LSI).
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* @param NewState new state of LSIEN, value accepted ENABLE, DISABLE.
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* @note Before using the LSI clock you have to enable the option bytes (LSI_EN option bit is set).
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* @retval None
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*/
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inline void CLK_LSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set LSIEN bit */
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CLK->ICKR |= CLK_ICKR_LSIEN;
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} else {
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/* Reset LSIEN bit */
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_LSIEN);
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}
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}
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/**
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* @brief Enables or disablle the Configurable Clock Output (CCO).
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* @param NewState : New state of CCEN bit (CCO register).
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* This parameter can be any of the @ref FunctionalState enumeration.
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* @retval None
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*/
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inline void CLK_CCOCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set CCOEN bit */
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CLK->CCOR |= CLK_CCOR_CCOEN;
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} else {
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/* Reset CCOEN bit */
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CLK->CCOR &= (uint8_t) (~CLK_CCOR_CCOEN);
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}
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}
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/**
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* @brief Starts or Stops manually the clock switch execution.
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* @par Full description:
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* NewState parameter set the SWEN.
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* @param NewState new state of SWEN, value accepted ENABLE, DISABLE.
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* @retval None
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*/
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inline void CLK_ClockSwitchCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Enable the Clock Switch */
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CLK->SWCR |= CLK_SWCR_SWEN;
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} else {
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/* Disable the Clock Switch */
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CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWEN);
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}
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}
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/**
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* @brief Configures the slow active halt wake up
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* @param NewState: specifies the Slow Active Halt wake up state.
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* can be set of the following values:
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* - DISABLE: Slow Active Halt mode disabled;
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* - ENABLE: Slow Active Halt mode enabled.
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* @retval None
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*/
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inline void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
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{
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/* check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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if (NewState != DISABLE) {
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/* Set S_ACTHALT bit */
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CLK->ICKR |= CLK_ICKR_SWUAH;
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} else {
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/* Reset S_ACTHALT bit */
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_SWUAH);
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}
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}
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/**
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* @brief Enables or disables the specified peripheral CLK.
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* @param CLK_Peripheral : This parameter specifies the peripheral clock to gate.
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* This parameter can be any of the @ref CLK_Peripheral_TypeDef enumeration.
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* @param NewState : New state of specified peripheral clock.
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* This parameter can be any of the @ref FunctionalState enumeration.
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* @retval None
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*/
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inline void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONALSTATE_OK(NewState));
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assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
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if (((uint8_t) CLK_Peripheral & (uint8_t) 0x10) == 0x00) {
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if (NewState != DISABLE) {
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/* Enable the peripheral Clock */
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CLK->PCKENR1 |= (uint8_t) ((uint8_t) 1 << ((uint8_t) CLK_Peripheral & (uint8_t) 0x0F));
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} else {
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/* Disable the peripheral Clock */
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CLK->PCKENR1 &= (uint8_t) (~(uint8_t) (((uint8_t) 1 << ((uint8_t) CLK_Peripheral & (uint8_t) 0x0F))));
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}
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} else {
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if (NewState != DISABLE) {
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/* Enable the peripheral Clock */
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CLK->PCKENR2 |= (uint8_t) ((uint8_t) 1 << ((uint8_t) CLK_Peripheral & (uint8_t) 0x0F));
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} else {
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/* Disable the peripheral Clock */
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CLK->PCKENR2 &= (uint8_t) (~(uint8_t) (((uint8_t) 1 << ((uint8_t) CLK_Peripheral & (uint8_t) 0x0F))));
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}
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}
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}
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/**
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* @brief configures the Switch from one clock to another
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* @param CLK_SwitchMode select the clock switch mode.
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* It can be set of the values of @ref CLK_SwitchMode_TypeDef
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* @param CLK_NewClock choice of the future clock.
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* It can be set of the values of @ref CLK_Source_TypeDef
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* @param NewState Enable or Disable the Clock Switch interrupt.
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* @param CLK_CurrentClockState current clock to switch OFF or to keep ON.
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* It can be set of the values of @ref CLK_CurrentClockState_TypeDef
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* @note LSI selected as master clock source only if LSI_EN option bit is set.
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* @retval ErrorStatus this shows the clock switch status (ERROR/SUCCESS).
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*/
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inline ErrorStatus
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CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState,
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CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
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{
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CLK_Source_TypeDef clock_master;
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uint16_t DownCounter = CLK_TIMEOUT;
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ErrorStatus Swif = ERROR;
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/* Check the parameters */
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assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
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assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
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assert_param(IS_FUNCTIONALSTATE_OK(ITState));
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assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
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/* Current clock master saving */
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clock_master = (CLK_Source_TypeDef) CLK->CMSR;
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/* Automatic switch mode management */
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if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO) {
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/* Enables Clock switch */
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CLK->SWCR |= CLK_SWCR_SWEN;
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/* Enables or Disables Switch interrupt */
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if (ITState != DISABLE) {
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CLK->SWCR |= CLK_SWCR_SWIEN;
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} else {
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CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWIEN);
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}
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/* Selection of the target clock source */
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CLK->SWR = (uint8_t) CLK_NewClock;
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/* Wait until the target clock source is ready */
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while ((((CLK->SWCR & CLK_SWCR_SWBSY) != 0) && (DownCounter != 0))) {
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DownCounter--;
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}
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if (DownCounter != 0) {
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Swif = SUCCESS;
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} else {
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Swif = ERROR;
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}
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} else /* CLK_SwitchMode == CLK_SWITCHMODE_MANUAL */
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{
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/* Enables or Disables Switch interrupt if required */
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if (ITState != DISABLE) {
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CLK->SWCR |= CLK_SWCR_SWIEN;
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} else {
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CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWIEN);
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}
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/* Selection of the target clock source */
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CLK->SWR = (uint8_t) CLK_NewClock;
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|
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/* Wait until the target clock source is ready */
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while ((((CLK->SWCR & CLK_SWCR_SWIF) != 0) && (DownCounter != 0))) {
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DownCounter--;
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}
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if (DownCounter != 0) {
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/* Enables Clock switch */
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CLK->SWCR |= CLK_SWCR_SWEN;
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Swif = SUCCESS;
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} else {
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Swif = ERROR;
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}
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}
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if (Swif != ERROR) {
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/* Switch OFF current clock if required */
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if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && (clock_master == CLK_SOURCE_HSI)) {
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_HSIEN);
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} else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && (clock_master == CLK_SOURCE_LSI)) {
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CLK->ICKR &= (uint8_t) (~CLK_ICKR_LSIEN);
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} else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && (clock_master == CLK_SOURCE_HSE)) {
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CLK->ECKR &= (uint8_t) (~CLK_ECKR_HSEEN);
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}
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}
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return (Swif);
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}
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|
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/**
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* @brief Configures the HSI clock dividers.
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* @param HSIPrescaler : Specifies the HSI clock divider to apply.
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* This parameter can be any of the @ref CLK_Prescaler_TypeDef enumeration.
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* @retval None
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*/
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inline void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
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{
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/* check the parameters */
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assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
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|
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/* Clear High speed internal clock prescaler */
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CLK->CKDIVR &= (uint8_t) (~CLK_CKDIVR_HSIDIV);
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|
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/* Set High speed internal clock prescaler */
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CLK->CKDIVR |= (uint8_t) HSIPrescaler;
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}
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|
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/**
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* @brief Output the selected clock on a dedicated I/O pin.
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* @param CLK_CCO : Specifies the clock source.
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* This parameter can be any of the @ref CLK_Output_TypeDef enumeration.
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* @retval None
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|
* @par Required preconditions:
|
|
* The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register \n
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* to be set as input with pull-up or push-pull output.
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*/
|
|
inline void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
|
|
{
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/* check the parameters */
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assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
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|
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/* Clears of the CCO type bits part */
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CLK->CCOR &= (uint8_t) (~CLK_CCOR_CCOSEL);
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|
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/* Selects the source provided on cco_ck output */
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CLK->CCOR |= (uint8_t) CLK_CCO;
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|
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/* Enable the clock output */
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CLK->CCOR |= CLK_CCOR_CCOEN;
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}
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|
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/**
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|
* @brief Enables or disables the specified CLK interrupts.
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|
* @param CLK_IT This parameter specifies the interrupt sources.
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|
* It can be one of the values of @ref CLK_IT_TypeDef.
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|
* @param NewState New state of the Interrupt.
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* Value accepted ENABLE, DISABLE.
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* @retval None
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*/
|
|
inline void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
|
|
{
|
|
/* check the parameters */
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|
assert_param(IS_FUNCTIONALSTATE_OK(NewState));
|
|
assert_param(IS_CLK_IT_OK(CLK_IT));
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|
|
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if (NewState != DISABLE) {
|
|
switch (CLK_IT) {
|
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case CLK_IT_SWIF: /* Enable the clock switch interrupt */
|
|
CLK->SWCR |= CLK_SWCR_SWIEN;
|
|
break;
|
|
case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
|
|
CLK->CSSR |= CLK_CSSR_CSSDIE;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else /*(NewState == DISABLE)*/
|
|
{
|
|
switch (CLK_IT) {
|
|
case CLK_IT_SWIF: /* Disable the clock switch interrupt */
|
|
CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWIEN);
|
|
break;
|
|
case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
|
|
CLK->CSSR &= (uint8_t) (~CLK_CSSR_CSSDIE);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the HSI and CPU clock dividers.
|
|
* @param ClockPrescaler Specifies the HSI or CPU clock divider to apply.
|
|
* @retval None
|
|
*/
|
|
inline void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler)
|
|
{
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_PRESCALER_OK(CLK_Prescaler));
|
|
|
|
if (((uint8_t) CLK_Prescaler & (uint8_t) 0x80) == 0x00) /* Bit7 = 0 means HSI divider */
|
|
{
|
|
CLK->CKDIVR &= (uint8_t) (~CLK_CKDIVR_HSIDIV);
|
|
CLK->CKDIVR |= (uint8_t) ((uint8_t) CLK_Prescaler & (uint8_t) CLK_CKDIVR_HSIDIV);
|
|
} else /* Bit7 = 1 means CPU divider */
|
|
{
|
|
CLK->CKDIVR &= (uint8_t) (~CLK_CKDIVR_CPUDIV);
|
|
CLK->CKDIVR |= (uint8_t) ((uint8_t) CLK_Prescaler & (uint8_t) CLK_CKDIVR_CPUDIV);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the SWIM clock frequency on the fly.
|
|
* @param CLK_SWIMDivider Specifies the SWIM clock divider to apply.
|
|
* can be one of the value of @ref CLK_SWIMDivider_TypeDef
|
|
* @retval None
|
|
*/
|
|
inline void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
|
|
{
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
|
|
|
|
if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2) {
|
|
/* SWIM clock is not divided by 2 */
|
|
CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
|
|
} else /* CLK_SWIMDivider == CLK_SWIMDIVIDER_2 */
|
|
{
|
|
/* SWIM clock is divided by 2 */
|
|
CLK->SWIMCCR &= (uint8_t) (~CLK_SWIMCCR_SWIMDIV);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the Clock Security System.
|
|
* @par Full description:
|
|
* once CSS is enabled it cannot be disabled until the next reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
inline void CLK_ClockSecuritySystemEnable(void)
|
|
{
|
|
/* Set CSSEN bit */
|
|
CLK->CSSR |= CLK_CSSR_CSSEN;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the clock source used as system clock.
|
|
* @param None
|
|
* @retval Clock source used.
|
|
* can be one of the values of @ref CLK_Source_TypeDef
|
|
*/
|
|
inline CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
|
|
{
|
|
return ((CLK_Source_TypeDef) CLK->CMSR);
|
|
}
|
|
|
|
/**
|
|
* @brief This function returns the frequencies of different on chip clocks.
|
|
* @param None
|
|
* @retval the master clock frequency
|
|
*/
|
|
inline uint32_t CLK_GetClockFreq(void)
|
|
{
|
|
// static const CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}; /*!< Holds the different HSI Divider factors */
|
|
uint32_t clockfrequency = 0;
|
|
CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
|
|
uint8_t tmp = 0, presc = 0;
|
|
|
|
/* Get CLK source. */
|
|
clocksource = (CLK_Source_TypeDef) CLK->CMSR;
|
|
|
|
if (clocksource == CLK_SOURCE_HSI) {
|
|
tmp = (uint8_t) (CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
|
|
tmp = (uint8_t) (tmp >> 3);
|
|
presc = (uint8_t)(1<<tmp);// HSIDivFactor[tmp]; // CHANGED
|
|
clockfrequency = HSI_VALUE / presc;
|
|
} else if (clocksource == CLK_SOURCE_LSI) {
|
|
clockfrequency = LSI_VALUE;
|
|
} else {
|
|
clockfrequency = HSE_VALUE;
|
|
}
|
|
|
|
return ((uint32_t) clockfrequency);
|
|
}
|
|
|
|
/**
|
|
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
|
|
* @par Full description:
|
|
* @param CLK_HSICalibrationValue calibration trimming value.
|
|
* can be one of the values of @ref CLK_HSITrimValue_TypeDef
|
|
* @retval None
|
|
*/
|
|
inline void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
|
|
{
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
|
|
|
|
/* Store the new value */
|
|
CLK->HSITRIMR = (uint8_t) ((uint8_t) (CLK->HSITRIMR & (uint8_t) (~CLK_HSITRIMR_HSITRIM)) |
|
|
((uint8_t) CLK_HSICalibrationValue));
|
|
}
|
|
|
|
/**
|
|
* @brief Reset the SWBSY flag (SWICR Register)
|
|
* @par Full description:
|
|
* This function reset SWBSY flag in order to reset clock switch operations (target
|
|
* oscillator is broken, stabilization is longing too much, etc.). If at the same time \n
|
|
* software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
inline void CLK_SYSCLKEmergencyClear(void)
|
|
{
|
|
CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWBSY);
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified CLK flag is set or not.
|
|
* @par Full description:
|
|
* @param CLK_FLAG Flag to check.
|
|
* can be one of the values of @ref CLK_Flag_TypeDef
|
|
* @retval FlagStatus, status of the checked flag
|
|
*/
|
|
inline FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
|
|
{
|
|
uint16_t statusreg = 0;
|
|
uint8_t tmpreg = 0;
|
|
FlagStatus bitstatus = RESET;
|
|
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
|
|
|
|
/* Get the CLK register index */
|
|
statusreg = (uint16_t) ((uint16_t) CLK_FLAG & (uint16_t) 0xFF00);
|
|
|
|
|
|
if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
|
|
{
|
|
tmpreg = CLK->ICKR;
|
|
} else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
|
|
{
|
|
tmpreg = CLK->ECKR;
|
|
} else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
|
|
{
|
|
tmpreg = CLK->SWCR;
|
|
} else if (statusreg == 0x0400) /* The flag to check is in CSS register */
|
|
{
|
|
tmpreg = CLK->CSSR;
|
|
} else /* The flag to check is in CCO register */
|
|
{
|
|
tmpreg = CLK->CCOR;
|
|
}
|
|
|
|
if ((tmpreg & (uint8_t) CLK_FLAG) != (uint8_t) RESET) {
|
|
bitstatus = SET;
|
|
} else {
|
|
bitstatus = RESET;
|
|
}
|
|
|
|
/* Return the flag status */
|
|
return ((FlagStatus) bitstatus);
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified CLK interrupt has is enabled or not.
|
|
* @param CLK_IT specifies the CLK interrupt.
|
|
* can be one of the values of @ref CLK_IT_TypeDef
|
|
* @retval ITStatus, new state of CLK_IT (SET or RESET).
|
|
*/
|
|
inline ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
|
|
{
|
|
ITStatus bitstatus = RESET;
|
|
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_IT_OK(CLK_IT));
|
|
|
|
if (CLK_IT == CLK_IT_SWIF) {
|
|
/* Check the status of the clock switch interrupt */
|
|
if ((CLK->SWCR & (uint8_t) CLK_IT) == (uint8_t) 0x0C) {
|
|
bitstatus = SET;
|
|
} else {
|
|
bitstatus = RESET;
|
|
}
|
|
} else /* CLK_IT == CLK_IT_CSSDIE */
|
|
{
|
|
/* Check the status of the security system detection interrupt */
|
|
if ((CLK->CSSR & (uint8_t) CLK_IT) == (uint8_t) 0x0C) {
|
|
bitstatus = SET;
|
|
} else {
|
|
bitstatus = RESET;
|
|
}
|
|
}
|
|
|
|
/* Return the CLK_IT status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the CLK's interrupt pending bits.
|
|
* @param CLK_IT specifies the interrupt pending bits.
|
|
* can be one of the values of @ref CLK_IT_TypeDef
|
|
* @retval None
|
|
*/
|
|
inline void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
|
|
{
|
|
/* check the parameters */
|
|
assert_param(IS_CLK_IT_OK(CLK_IT));
|
|
|
|
if (CLK_IT == (uint8_t) CLK_IT_CSSD) {
|
|
/* Clear the status of the security system detection interrupt */
|
|
CLK->CSSR &= (uint8_t) (~CLK_CSSR_CSSD);
|
|
} else /* CLK_PendingBit == (uint8_t)CLK_IT_SWIF */
|
|
{
|
|
/* Clear the status of the clock switch interrupt */
|
|
CLK->SWCR &= (uint8_t) (~CLK_SWCR_SWIF);
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* __STM8S_CLK_H */
|
|
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|