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96 lines
4.1 KiB
96 lines
4.1 KiB
;********************************************************************************
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; FILE : INI_WWDG.S
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; AUTHOR : Petr Dousa, Ondrej Hruska
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; DATE : 10/2015
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; DESCR : Control registers and bit masks for WWDG
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;
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; Window WATCHDOG (WWDG)
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;
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; Independent WATCHDOG (IWDG)
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;
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; Part of an assembler library for STM32L100, based on the STM32 CMSIS.
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; Developed for educational purposes at the Department of Measure of CTU in Prague.
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; See the LICENSE file for detailed terms of use.
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;********************************************************************************
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;****************************************************************************
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;*
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;* REGISTERS
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;*
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;****************************************************************************
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; Window Watchdog
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WWDG_CR EQU (_WWDG + 0x00) ; WWDG Control register,
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WWDG_CFR EQU (_WWDG + 0x04) ; WWDG Configuration register,
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WWDG_SR EQU (_WWDG + 0x08) ; WWDG Status register,
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; Independent Watchdog
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IWDG_KR EQU (_IWDG + 0x00) ; Key register,
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IWDG_PR EQU (_IWDG + 0x04) ; Prescaler register,
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IWDG_RLR EQU (_IWDG + 0x08) ; Reload register,
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IWDG_SR EQU (_IWDG + 0x0C) ; Status register,
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;****************************************************************************
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;*
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;* BIT MASKS AND DEFINITIONS
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;*
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;****************************************************************************
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;****************** Bit definition for WWDG_CR register *******************
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WWDG_CR_T EQU 0x7F ; T[6:0] bits (7-Bit counter (MSB to LSB))
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WWDG_CR_T0 EQU 0x01 ; Bit 0
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WWDG_CR_T1 EQU 0x02 ; Bit 1
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WWDG_CR_T2 EQU 0x04 ; Bit 2
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WWDG_CR_T3 EQU 0x08 ; Bit 3
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WWDG_CR_T4 EQU 0x10 ; Bit 4
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WWDG_CR_T5 EQU 0x20 ; Bit 5
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WWDG_CR_T6 EQU 0x40 ; Bit 6
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WWDG_CR_WDGA EQU 0x80 ; Activation bit
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;****************** Bit definition for WWDG_CFR register ******************
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WWDG_CFR_W EQU 0x007F ; W[6:0] bits (7-bit window value)
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WWDG_CFR_W0 EQU 0x0001 ; Bit 0
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WWDG_CFR_W1 EQU 0x0002 ; Bit 1
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WWDG_CFR_W2 EQU 0x0004 ; Bit 2
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WWDG_CFR_W3 EQU 0x0008 ; Bit 3
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WWDG_CFR_W4 EQU 0x0010 ; Bit 4
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WWDG_CFR_W5 EQU 0x0020 ; Bit 5
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WWDG_CFR_W6 EQU 0x0040 ; Bit 6
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WWDG_CFR_WDGTB EQU 0x0180 ; WDGTB[1:0] bits (Timer Base)
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WWDG_CFR_WDGTB0 EQU 0x0080 ; Bit 0
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WWDG_CFR_WDGTB1 EQU 0x0100 ; Bit 1
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WWDG_CFR_EWI EQU 0x0200 ; Early Wakeup Interrupt
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;****************** Bit definition for WWDG_SR register *******************
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WWDG_SR_EWIF EQU 0x01 ; Early Wakeup Interrupt Flag
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;****************** Bit definition for IWDG_KR register *******************
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IWDG_KR_KEY EQU 0xFFFF ; Key value (write only, read 0000h)
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;****************** Bit definition for IWDG_PR register *******************
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IWDG_PR_PR EQU 0x07 ; PR[2:0] (Prescaler divider)
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IWDG_PR_PR_0 EQU 0x01 ; Bit 0
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IWDG_PR_PR_1 EQU 0x02 ; Bit 1
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IWDG_PR_PR_2 EQU 0x04 ; Bit 2
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;****************** Bit definition for IWDG_RLR register ******************
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IWDG_RLR_RL EQU 0x0FFF ; Watchdog counter reload value
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;****************** Bit definition for IWDG_SR register *******************
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IWDG_SR_PVU EQU 0x01 ; Watchdog prescaler value update
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IWDG_SR_RVU EQU 0x02 ; Watchdog counter reload value update
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END
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