From 32bb59cec0b0badd2b9a709b57be8a165caa61a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Hru=C5=A1ka?= Date: Tue, 20 Oct 2015 09:11:42 +0200 Subject: [PATCH] Converted all _BITS to peripheral module files. Added TODO about missing registers. --- lib/{INI_BITS_ADC.s => INI_ADC.s} | 50 +- lib/{INI_BITS_AES.s => INI_AES.s} | 35 +- lib/INI_BITS_IWDG.s | 33 - lib/{INI_BITS_COMP.s => INI_COMP.s} | 20 +- lib/{INI_BITS_CRC.s => INI_CRC.s} | 27 +- lib/{INI_BITS_DAC.s => INI_DAC.s} | 48 +- lib/{INI_BITS_DBGMCU.s => INI_DBGMCU.s} | 23 +- lib/{INI_BITS_DMA.s => INI_DMA.s} | 107 +++- lib/{INI_BITS_EXTI.s => INI_EXTI.s} | 25 +- lib/{INI_BITS_FLASH.s => INI_FLASH.s} | 45 +- lib/{INI_BITS_FSMC.s => INI_FSMC.s} | 27 +- lib/{INI_BITS_I2C.s => INI_I2C.s} | 41 +- lib/{INI_BITS_LCD.s => INI_LCD.s} | 26 +- lib/{INI_BITS_NVIC.s => INI_NVIC.s} | 68 ++- lib/{INI_BITS_OPAMP.s => INI_OPAMP.s} | 22 +- lib/{INI_BITS_PWR.s => INI_PWR.s} | 21 +- lib/{INI_BITS_RCC.s => INI_RCC.s} | 34 +- lib/INI_REGS.s | 777 ------------------------ lib/{INI_BITS_RI.s => INI_RI.s} | 41 +- lib/{INI_BITS_RTC.s => INI_RTC.s} | 73 ++- lib/{INI_BITS_SDIO.s => INI_SDIO.s} | 37 +- lib/{INI_BITS_SPI.s => INI_SPI.s} | 53 +- lib/{INI_BITS_SYSCFG.s => INI_SYSCFG.s} | 25 +- lib/{INI_BITS_TIM.s => INI_TIM.s} | 216 ++++++- lib/{INI_BITS_USART.s => INI_USART.s} | 67 +- lib/{INI_BITS_USB.s => INI_USB.s} | 18 +- lib/{INI_BITS_WWDG.s => INI_WDG.s} | 52 +- lib/TODO.txt | 8 + main.asm | 9 +- 29 files changed, 1133 insertions(+), 895 deletions(-) rename lib/{INI_BITS_ADC.s => INI_ADC.s} (94%) rename lib/{INI_BITS_AES.s => INI_AES.s} (76%) delete mode 100644 lib/INI_BITS_IWDG.s rename lib/{INI_BITS_COMP.s => INI_COMP.s} (87%) rename lib/{INI_BITS_CRC.s => INI_CRC.s} (68%) rename lib/{INI_BITS_DAC.s => INI_DAC.s} (80%) rename lib/{INI_BITS_DBGMCU.s => INI_DBGMCU.s} (87%) rename lib/{INI_BITS_DMA.s => INI_DMA.s} (79%) rename lib/{INI_BITS_EXTI.s => INI_EXTI.s} (94%) rename lib/{INI_BITS_FLASH.s => INI_FLASH.s} (75%) rename lib/{INI_BITS_FSMC.s => INI_FSMC.s} (97%) rename lib/{INI_BITS_I2C.s => INI_I2C.s} (82%) rename lib/{INI_BITS_LCD.s => INI_LCD.s} (87%) rename lib/{INI_BITS_NVIC.s => INI_NVIC.s} (80%) rename lib/{INI_BITS_OPAMP.s => INI_OPAMP.s} (89%) rename lib/{INI_BITS_PWR.s => INI_PWR.s} (87%) rename lib/{INI_BITS_RCC.s => INI_RCC.s} (94%) delete mode 100644 lib/INI_REGS.s rename lib/{INI_BITS_RI.s => INI_RI.s} (93%) rename lib/{INI_BITS_RTC.s => INI_RTC.s} (84%) rename lib/{INI_BITS_SDIO.s => INI_SDIO.s} (89%) rename lib/{INI_BITS_SPI.s => INI_SPI.s} (71%) rename lib/{INI_BITS_SYSCFG.s => INI_SYSCFG.s} (91%) rename lib/{INI_BITS_TIM.s => INI_TIM.s} (58%) rename lib/{INI_BITS_USART.s => INI_USART.s} (68%) rename lib/{INI_BITS_USB.s => INI_USB.s} (99%) rename lib/{INI_BITS_WWDG.s => INI_WDG.s} (58%) create mode 100644 lib/TODO.txt diff --git a/lib/INI_BITS_ADC.s b/lib/INI_ADC.s similarity index 94% rename from lib/INI_BITS_ADC.s rename to lib/INI_ADC.s index 22cce4c..4aac5a3 100644 --- a/lib/INI_BITS_ADC.s +++ b/lib/INI_ADC.s @@ -4,16 +4,60 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro ADC ; +; Analog to Digital Converter (ADC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Analog to Digital Converter (ADC) -; +;* +;* REGISTERS +;* ;**************************************************************************** + +; ADC common config + +ADC_CSR EQU (_ADCC + 0x000) ; ADC common status register, +ADC_CCR EQU (_ADCC + 0x004) ; ADC common control register, + +; ADC1 + +ADC_SR EQU (_ADC1 + 0x00) ; ADC status register, +ADC_CR1 EQU (_ADC1 + 0x04) ; ADC control register 1, +ADC_CR2 EQU (_ADC1 + 0x08) ; ADC control register 2, +ADC_SMPR1 EQU (_ADC1 + 0x0C) ; ADC sample time register 1, +ADC_SMPR2 EQU (_ADC1 + 0x10) ; ADC sample time register 2, +ADC_SMPR3 EQU (_ADC1 + 0x14) ; ADC sample time register 3, +ADC_JOFR1 EQU (_ADC1 + 0x18) ; ADC injected channel data offset register 1, +ADC_JOFR2 EQU (_ADC1 + 0x1C) ; ADC injected channel data offset register 2, +ADC_JOFR3 EQU (_ADC1 + 0x20) ; ADC injected channel data offset register 3, +ADC_JOFR4 EQU (_ADC1 + 0x24) ; ADC injected channel data offset register 4, +ADC_HTR EQU (_ADC1 + 0x28) ; ADC watchdog higher threshold register, +ADC_LTR EQU (_ADC1 + 0x2C) ; ADC watchdog lower threshold register, +ADC_SQR1 EQU (_ADC1 + 0x30) ; ADC regular sequence register 1, +ADC_SQR2 EQU (_ADC1 + 0x34) ; ADC regular sequence register 2, +ADC_SQR3 EQU (_ADC1 + 0x38) ; ADC regular sequence register 3, +ADC_SQR4 EQU (_ADC1 + 0x3C) ; ADC regular sequence register 4, +ADC_SQR5 EQU (_ADC1 + 0x40) ; ADC regular sequence register 5, +ADC_JSQR EQU (_ADC1 + 0x44) ; ADC injected sequence register, +ADC_JDR1 EQU (_ADC1 + 0x48) ; ADC injected data register 1, +ADC_JDR2 EQU (_ADC1 + 0x4C) ; ADC injected data register 2, +ADC_JDR3 EQU (_ADC1 + 0x50) ; ADC injected data register 3, +ADC_JDR4 EQU (_ADC1 + 0x54) ; ADC injected data register 4, +ADC_DR EQU (_ADC1 + 0x58) ; ADC regular data register, +ADC_SMPR0 EQU (_ADC1 + 0x5C) ; ADC sample time register 0, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;******************* Bit definition for ADC_SR register ******************* ADC_SR_AWD EQU 0x00000001 ; Analog watchdog flag ADC_SR_EOC EQU 0x00000002 ; End of conversion diff --git a/lib/INI_BITS_AES.s b/lib/INI_AES.s similarity index 76% rename from lib/INI_BITS_AES.s rename to lib/INI_AES.s index 32b093a..a3082a1 100644 --- a/lib/INI_BITS_AES.s +++ b/lib/INI_AES.s @@ -2,20 +2,45 @@ ; SOUBOR : INI_BITS_AES.S ; AUTOR : Petr Dousa, Ondrej Hruska ; DATUM : 10/2015 -; POPIS : Bitove masky ridicich registru pro AES (crypto) +; POPIS : Bitove masky ridicich registru pro AES (crypto); +; ! Modul je pouze v STM32L162 ! ; -; ! Modul je pouze v STM32L162 ! +; Advanced Encryption Standard (AES) ; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Advanced Encryption Standard (AES) -; +;* +;* REGISTERS +;* +;**************************************************************************** + + +; AES crypto module + +AES_CR EQU (_AES + 0x00) ; AES control register, +AES_SR EQU (_AES + 0x04) ; AES status register, +AES_DINR_REG EQU (_AES + 0x08) ; AES data input register, +AES_DOUTR_REG EQU (_AES + 0x0C) ; AES data output register, +AES_KEYR0_REG EQU (_AES + 0x10) ; AES key register 0, +AES_KEYR1_REG EQU (_AES + 0x14) ; AES key register 1, +AES_KEYR2_REG EQU (_AES + 0x18) ; AES key register 2, +AES_KEYR3_REG EQU (_AES + 0x1C) ; AES key register 3, +AES_IVR0_REG EQU (_AES + 0x20) ; AES initialization vector register 0, +AES_IVR1_REG EQU (_AES + 0x24) ; AES initialization vector register 1, +AES_IVR2_REG EQU (_AES + 0x28) ; AES initialization vector register 2, +AES_IVR3_REG EQU (_AES + 0x2C) ; AES initialization vector register 3, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;****************** Bit definition for AES_CR register ******************** AES_CR_EN EQU 0x00000001 ; AES Enable AES_CR_DATATYPE EQU 0x00000006 ; Data type selection diff --git a/lib/INI_BITS_IWDG.s b/lib/INI_BITS_IWDG.s deleted file mode 100644 index c448ee8..0000000 --- a/lib/INI_BITS_IWDG.s +++ /dev/null @@ -1,33 +0,0 @@ -;******************************************************************************** -; SOUBOR : INI_BITS_IWDG.S -; AUTOR : Petr Dousa, Ondrej Hruska -; DATUM : 10/2015 -; POPIS : Bitove masky ridicich registru pro IWDG -; -; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. -;******************************************************************************** - - -;**************************************************************************** -; -; Independent WATCHDOG (IWDG) -; -;**************************************************************************** - -;****************** Bit definition for IWDG_KR register ******************* -IWDG_KR_KEY EQU 0xFFFF ; Key value (write only, read 0000h) - -;****************** Bit definition for IWDG_PR register ******************* -IWDG_PR_PR EQU 0x07 ; PR[2:0] (Prescaler divider) -IWDG_PR_PR_0 EQU 0x01 ; Bit 0 -IWDG_PR_PR_1 EQU 0x02 ; Bit 1 -IWDG_PR_PR_2 EQU 0x04 ; Bit 2 - -;****************** Bit definition for IWDG_RLR register ****************** -IWDG_RLR_RL EQU 0x0FFF ; Watchdog counter reload value - -;****************** Bit definition for IWDG_SR register ******************* -IWDG_SR_PVU EQU 0x01 ; Watchdog prescaler value update -IWDG_SR_RVU EQU 0x02 ; Watchdog counter reload value update - - END diff --git a/lib/INI_BITS_COMP.s b/lib/INI_COMP.s similarity index 87% rename from lib/INI_BITS_COMP.s rename to lib/INI_COMP.s index 7c384cb..1cdaea0 100644 --- a/lib/INI_BITS_COMP.s +++ b/lib/INI_COMP.s @@ -4,16 +4,30 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro COMP (analogovy komparator) ; +; Analog Comparators (COMP) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Analog Comparators (COMP) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; Comparator + +COMP_CSR EQU (_COMP + 0x00) ; COMP comparator control and status register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;***************** Bit definition for COMP_CSR register ******************* COMP_CSR_10KPU EQU 0x00000001 ; 10K pull-up resistor COMP_CSR_400KPU EQU 0x00000002 ; 400K pull-up resistor diff --git a/lib/INI_BITS_CRC.s b/lib/INI_CRC.s similarity index 68% rename from lib/INI_BITS_CRC.s rename to lib/INI_CRC.s index a49e74e..1758e77 100644 --- a/lib/INI_BITS_CRC.s +++ b/lib/INI_CRC.s @@ -1,26 +1,45 @@ ;******************************************************************************** -; SOUBOR : INI_BITS_CRC.S +; SOUBOR : INI_CRC.S ; AUTOR : Petr Dousa, Ondrej Hruska ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro CRC (checksum generator) ; +; CRC calculation unit (CRC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; CRC calculation unit (CRC) -; +;* +;* REGISTERS +;* ;**************************************************************************** +; CRC module + +CRC_DR EQU (_CRC + 0x00) ; CRC Data register, +CRC_IDR EQU (_CRC + 0x04) ; CRC Independent data register, +CRC_CR EQU (_CRC + 0x08) ; CRC Control register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for CRC_DR register ******************** + CRC_DR_DR EQU 0xFFFFFFFF ; Data register bits ;****************** Bit definition for CRC_IDR register ******************* + CRC_IDR_IDR EQU 0xFF ; General-purpose 8-bit data register bits ;******************* Bit definition for CRC_CR register ******************* + CRC_CR_RESET EQU 0x00000001 ; RESET bit END diff --git a/lib/INI_BITS_DAC.s b/lib/INI_DAC.s similarity index 80% rename from lib/INI_BITS_DAC.s rename to lib/INI_DAC.s index 8315c24..ee44af8 100644 --- a/lib/INI_BITS_DAC.s +++ b/lib/INI_DAC.s @@ -4,17 +4,45 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro DAC (digitalne-analogovy prevodnik) ; +; Digital to Analog Converter (DAC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Digital to Analog Converter (DAC) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; D/A converter + +DAC_CR EQU (_DAC + 0x00) ; DAC control register, +DAC_SWTRIGR EQU (_DAC + 0x04) ; DAC software trigger register, +DAC_DHR12R1 EQU (_DAC + 0x08) ; DAC channel1 12-bit right-aligned data holding register, +DAC_DHR12L1 EQU (_DAC + 0x0C) ; DAC channel1 12-bit left aligned data holding register, +DAC_DHR8R1 EQU (_DAC + 0x10) ; DAC channel1 8-bit right aligned data holding register, +DAC_DHR12R2 EQU (_DAC + 0x14) ; DAC channel2 12-bit right aligned data holding register, +DAC_DHR12L2 EQU (_DAC + 0x18) ; DAC channel2 12-bit left aligned data holding register, +DAC_DHR8R2 EQU (_DAC + 0x1C) ; DAC channel2 8-bit right-aligned data holding register, +DAC_DHR12RD EQU (_DAC + 0x20) ; Dual DAC 12-bit right-aligned data holding register, +DAC_DHR12LD EQU (_DAC + 0x24) ; DUAL DAC 12-bit left aligned data holding register, +DAC_DHR8RD EQU (_DAC + 0x28) ; DUAL DAC 8-bit right aligned data holding register, +DAC_DOR1 EQU (_DAC + 0x2C) ; DAC channel1 data output register, +DAC_DOR2 EQU (_DAC + 0x30) ; DAC channel2 data output register, +DAC_SR EQU (_DAC + 0x34) ; DAC status register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;******************* Bit definition for DAC_CR register ******************* + DAC_CR_EN1 EQU 0x00000001 ; DAC channel1 enable DAC_CR_BOFF1 EQU 0x00000002 ; DAC channel1 output buffer disable DAC_CR_TEN1 EQU 0x00000004 ; DAC channel1 Trigger enable @@ -57,47 +85,61 @@ DAC_CR_MAMP2_3 EQU 0x08000000 ; Bit 3 DAC_CR_DMAEN2 EQU 0x10000000 ; DAC channel2 DMA enabled DAC_CR_DMAUDRIE2 EQU 0x20000000 ; DAC channel2 DMA underrun interrupt enable + ;**************** Bit definition for DAC_SWTRIGR register ***************** + DAC_SWTRIGR_SWTRIG1 EQU 0x01 ; DAC channel1 software trigger DAC_SWTRIGR_SWTRIG2 EQU 0x02 ; DAC channel2 software trigger ;**************** Bit definition for DAC_DHR12R1 register ***************** + DAC_DHR12R1_DACC1DHR EQU 0x0FFF ; DAC channel1 12-bit Right aligned data ;**************** Bit definition for DAC_DHR12L1 register ***************** + DAC_DHR12L1_DACC1DHR EQU 0xFFF0 ; DAC channel1 12-bit Left aligned data ;***************** Bit definition for DAC_DHR8R1 register ***************** + DAC_DHR8R1_DACC1DHR EQU 0xFF ; DAC channel1 8-bit Right aligned data ;**************** Bit definition for DAC_DHR12R2 register ***************** + DAC_DHR12R2_DACC2DHR EQU 0x0FFF ; DAC channel2 12-bit Right aligned data ;**************** Bit definition for DAC_DHR12L2 register ***************** + DAC_DHR12L2_DACC2DHR EQU 0xFFF0 ; DAC channel2 12-bit Left aligned data ;***************** Bit definition for DAC_DHR8R2 register ***************** + DAC_DHR8R2_DACC2DHR EQU 0xFF ; DAC channel2 8-bit Right aligned data ;**************** Bit definition for DAC_DHR12RD register ***************** + DAC_DHR12RD_DACC1DHR EQU 0x00000FFF ; DAC channel1 12-bit Right aligned data DAC_DHR12RD_DACC2DHR EQU 0x0FFF0000 ; DAC channel2 12-bit Right aligned data ;**************** Bit definition for DAC_DHR12LD register ***************** + DAC_DHR12LD_DACC1DHR EQU 0x0000FFF0 ; DAC channel1 12-bit Left aligned data DAC_DHR12LD_DACC2DHR EQU 0xFFF00000 ; DAC channel2 12-bit Left aligned data ;***************** Bit definition for DAC_DHR8RD register ***************** + DAC_DHR8RD_DACC1DHR EQU 0x00FF ; DAC channel1 8-bit Right aligned data DAC_DHR8RD_DACC2DHR EQU 0xFF00 ; DAC channel2 8-bit Right aligned data ;****************** Bit definition for DAC_DOR1 register ****************** + DAC_DOR1_DACC1DOR EQU 0x0FFF ; DAC channel1 data output ;****************** Bit definition for DAC_DOR2 register ****************** + DAC_DOR2_DACC2DOR EQU 0x0FFF ; DAC channel2 data output ;******************* Bit definition for DAC_SR register ******************* + DAC_SR_DMAUDR1 EQU 0x00002000 ; DAC channel1 DMA underrun flag DAC_SR_DMAUDR2 EQU 0x20000000 ; DAC channel2 DMA underrun flag diff --git a/lib/INI_BITS_DBGMCU.s b/lib/INI_DBGMCU.s similarity index 87% rename from lib/INI_BITS_DBGMCU.s rename to lib/INI_DBGMCU.s index a5b3dc3..7fb2b81 100644 --- a/lib/INI_BITS_DBGMCU.s +++ b/lib/INI_DBGMCU.s @@ -4,16 +4,33 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro DBGMCU (Debug MCU control) ; +; Debug MCU (DBGMCU) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Debug MCU (DBGMCU) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; DBGMCU + +DBGMCU_IDCODE EQU (_DBGMCU + 0x00) ; MCU device ID code, +DBGMCU_CR EQU (_DBGMCU + 0x04) ; Debug MCU configuration register, +DBGMCU_APB1FZ EQU (_DBGMCU + 0x08) ; Debug MCU APB1 freeze register, +DBGMCU_APB2FZ EQU (_DBGMCU + 0x0C) ; Debug MCU APB2 freeze register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;*************** Bit definition for DBGMCU_IDCODE register **************** DBGMCU_IDCODE_DEV_ID EQU 0x00000FFF ; Device Identifier diff --git a/lib/INI_BITS_DMA.s b/lib/INI_DMA.s similarity index 79% rename from lib/INI_BITS_DMA.s rename to lib/INI_DMA.s index 582ca6e..1b95bfe 100644 --- a/lib/INI_BITS_DMA.s +++ b/lib/INI_DMA.s @@ -4,16 +4,117 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro DMA (Direct memory access) ; +; DMA Controller (DMA) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; DMA Controller (DMA) -; +;* +;* REGISTERS +;* ;**************************************************************************** + +; DMA 1 + +; Status registers +DMA1_ISR EQU (_DMA1 + 0x00) ; DMA interrupt status register, +DMA1_IFCR EQU (_DMA1 + 0x04) ; DMA interrupt flag clear register, + +; Channel bases +_DMA1_CH1 EQU (_DMA1 + 0x0008) +_DMA1_CH2 EQU (_DMA1 + 0x001C) +_DMA1_CH3 EQU (_DMA1 + 0x0030) +_DMA1_CH4 EQU (_DMA1 + 0x0044) +_DMA1_CH5 EQU (_DMA1 + 0x0058) +_DMA1_CH6 EQU (_DMA1 + 0x006C) +_DMA1_CH7 EQU (_DMA1 + 0x0080) + +DMA1_CH1_CCR EQU (_DMA1_CH1 + 0x00) ; DMA channel x configuration register +DMA1_CH1_CNDTR EQU (_DMA1_CH1 + 0x04) ; DMA channel x number of data register +DMA1_CH1_CPAR EQU (_DMA1_CH1 + 0x08) ; DMA channel x peripheral address register +DMA1_CH1_CMAR EQU (_DMA1_CH1 + 0x0C) ; DMA channel x memory address register + +DMA1_CH2_CCR EQU (_DMA1_CH2 + 0x00) ; DMA channel x configuration register +DMA1_CH2_CNDTR EQU (_DMA1_CH2 + 0x04) ; DMA channel x number of data register +DMA1_CH2_CPAR EQU (_DMA1_CH2 + 0x08) ; DMA channel x peripheral address register +DMA1_CH2_CMAR EQU (_DMA1_CH2 + 0x0C) ; DMA channel x memory address register + +DMA1_CH3_CCR EQU (_DMA1_CH3 + 0x00) ; DMA channel x configuration register +DMA1_CH3_CNDTR EQU (_DMA1_CH3 + 0x04) ; DMA channel x number of data register +DMA1_CH3_CPAR EQU (_DMA1_CH3 + 0x08) ; DMA channel x peripheral address register +DMA1_CH3_CMAR EQU (_DMA1_CH3 + 0x0C) ; DMA channel x memory address register + +DMA1_CH4_CCR EQU (_DMA1_CH4 + 0x00) ; DMA channel x configuration register +DMA1_CH4_CNDTR EQU (_DMA1_CH4 + 0x04) ; DMA channel x number of data register +DMA1_CH4_CPAR EQU (_DMA1_CH4 + 0x08) ; DMA channel x peripheral address register +DMA1_CH4_CMAR EQU (_DMA1_CH4 + 0x0C) ; DMA channel x memory address register + +DMA1_CH5_CCR EQU (_DMA1_CH5 + 0x00) ; DMA channel x configuration register +DMA1_CH5_CNDTR EQU (_DMA1_CH5 + 0x04) ; DMA channel x number of data register +DMA1_CH5_CPAR EQU (_DMA1_CH5 + 0x08) ; DMA channel x peripheral address register +DMA1_CH5_CMAR EQU (_DMA1_CH5 + 0x0C) ; DMA channel x memory address register + +DMA1_CH6_CCR EQU (_DMA1_CH6 + 0x00) ; DMA channel x configuration register +DMA1_CH6_CNDTR EQU (_DMA1_CH6 + 0x04) ; DMA channel x number of data register +DMA1_CH6_CPAR EQU (_DMA1_CH6 + 0x08) ; DMA channel x peripheral address register +DMA1_CH6_CMAR EQU (_DMA1_CH6 + 0x0C) ; DMA channel x memory address register + +DMA1_CH7_CCR EQU (_DMA1_CH7 + 0x00) ; DMA channel x configuration register +DMA1_CH7_CNDTR EQU (_DMA1_CH7 + 0x04) ; DMA channel x number of data register +DMA1_CH7_CPAR EQU (_DMA1_CH7 + 0x08) ; DMA channel x peripheral address register +DMA1_CH7_CMAR EQU (_DMA1_CH7 + 0x0C) ; DMA channel x memory address register + + +; DMA 2 + +; Status registers +DMA2_ISR EQU (_DMA2 + 0x00) ; DMA interrupt status register, +DMA2_IFCR EQU (_DMA2 + 0x04) ; DMA interrupt flag clear register, + +; Channel bases +_DMA2_CH1 EQU (_DMA2 + 0x0008) +_DMA2_CH2 EQU (_DMA2 + 0x001C) +_DMA2_CH3 EQU (_DMA2 + 0x0030) +_DMA2_CH4 EQU (_DMA2 + 0x0044) +_DMA2_CH5 EQU (_DMA2 + 0x0058) + +DMA2_CH1_CCR EQU (_DMA2_CH1 + 0x00) ; DMA channel x configuration register +DMA2_CH1_CNDTR EQU (_DMA2_CH1 + 0x04) ; DMA channel x number of data register +DMA2_CH1_CPAR EQU (_DMA2_CH1 + 0x08) ; DMA channel x peripheral address register +DMA2_CH1_CMAR EQU (_DMA2_CH1 + 0x0C) ; DMA channel x memory address register + +DMA2_CH2_CCR EQU (_DMA2_CH2 + 0x00) ; DMA channel x configuration register +DMA2_CH2_CNDTR EQU (_DMA2_CH2 + 0x04) ; DMA channel x number of data register +DMA2_CH2_CPAR EQU (_DMA2_CH2 + 0x08) ; DMA channel x peripheral address register +DMA2_CH2_CMAR EQU (_DMA2_CH2 + 0x0C) ; DMA channel x memory address register + +DMA2_CH3_CCR EQU (_DMA2_CH3 + 0x00) ; DMA channel x configuration register +DMA2_CH3_CNDTR EQU (_DMA2_CH3 + 0x04) ; DMA channel x number of data register +DMA2_CH3_CPAR EQU (_DMA2_CH3 + 0x08) ; DMA channel x peripheral address register +DMA2_CH3_CMAR EQU (_DMA2_CH3 + 0x0C) ; DMA channel x memory address register + +DMA2_CH4_CCR EQU (_DMA2_CH4 + 0x00) ; DMA channel x configuration register +DMA2_CH4_CNDTR EQU (_DMA2_CH4 + 0x04) ; DMA channel x number of data register +DMA2_CH4_CPAR EQU (_DMA2_CH4 + 0x08) ; DMA channel x peripheral address register +DMA2_CH4_CMAR EQU (_DMA2_CH4 + 0x0C) ; DMA channel x memory address register + +DMA2_CH5_CCR EQU (_DMA2_CH5 + 0x00) ; DMA channel x configuration register +DMA2_CH5_CNDTR EQU (_DMA2_CH5 + 0x04) ; DMA channel x number of data register +DMA2_CH5_CPAR EQU (_DMA2_CH5 + 0x08) ; DMA channel x peripheral address register +DMA2_CH5_CMAR EQU (_DMA2_CH5 + 0x0C) ; DMA channel x memory address register + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for DMA_ISR register ******************* DMA_ISR_GIF1 EQU 0x00000001 ; Channel 1 Global interrupt flag DMA_ISR_TCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete flag diff --git a/lib/INI_BITS_EXTI.s b/lib/INI_EXTI.s similarity index 94% rename from lib/INI_BITS_EXTI.s rename to lib/INI_EXTI.s index 78be0c6..c98b43f 100644 --- a/lib/INI_BITS_EXTI.s +++ b/lib/INI_EXTI.s @@ -1,17 +1,34 @@ ;******************************************************************************** -; SOUBOR : INI_BITS_EXTI.S +; SOUBOR : INI_EXTI.S ; AUTOR : Petr Dousa, Ondrej Hruska ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro EXTI (ext. interrupt) ; +; External Interrupt/Event Controller (EXTI) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** +;**************************************************************************** +;* +;* REGISTERS +;* +;**************************************************************************** + +; External interrupt control registers + +EXTI_IMR EQU (_EXTI + 0x00) ; EXTI interrupt mask register, +EXTI_EMR EQU (_EXTI + 0x04) ; EXTI event mask register, +EXTI_RTSR EQU (_EXTI + 0x08) ; EXTI rising edge trigger selection register, +EXTI_FTSR EQU (_EXTI + 0x0C) ; EXTI Falling edge trigger selection register, +EXTI_SWIER EQU (_EXTI + 0x10) ; EXTI software interrupt event register, +EXTI_PR EQU (_EXTI + 0x14) ; EXTI pending register, + ;**************************************************************************** -; -; External Interrupt/Event Controller (EXTI) -; +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** ;****************** Bit definition for EXTI_IMR register ****************** diff --git a/lib/INI_BITS_FLASH.s b/lib/INI_FLASH.s similarity index 75% rename from lib/INI_BITS_FLASH.s rename to lib/INI_FLASH.s index 9696e93..2d8f77e 100644 --- a/lib/INI_BITS_FLASH.s +++ b/lib/INI_FLASH.s @@ -4,16 +4,53 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro FLASH ; +; FLASH, DATA EEPROM and Option Bytes Registers +; (FLASH, DATA_EEPROM, OB) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; FLASH, DATA EEPROM and Option Bytes Registers -; EQU (FLASH, DATA_EEPROM, OB) -; +;* +;* REGISTERS +;* +;**************************************************************************** + + +; FLASH registers + +FLASH_ACR EQU (_FLASH + 0x00) ; Access control register, +FLASH_PECR EQU (_FLASH + 0x04) ; Program/erase control register, +FLASH_PDKEYR EQU (_FLASH + 0x08) ; Power down key register, +FLASH_PEKEYR EQU (_FLASH + 0x0c) ; Program/erase key register, +FLASH_PRGKEYR EQU (_FLASH + 0x10) ; Program memory key register, +FLASH_OPTKEYR EQU (_FLASH + 0x14) ; Option byte key register, +FLASH_SR EQU (_FLASH + 0x18) ; Status register, +FLASH_OBR EQU (_FLASH + 0x1c) ; Option byte register, +FLASH_WRPR EQU (_FLASH + 0x20) ; Write protection register, +FLASH_WRPR1 EQU (_FLASH + 0x28) ; Write protection register 1, +FLASH_WRPR2 EQU (_FLASH + 0x2C) ; Write protection register 2, + +; FLASH option bytes + +OB_RDP EQU (_OB + 0x00) ; Read protection register, +OB_USER EQU (_OB + 0x04) ; user register, +OB_WRP01 EQU (_OB + 0x08) ; write protection register 0 1, +OB_WRP23 EQU (_OB + 0x0C) ; write protection register 2 3, +OB_WRP45 EQU (_OB + 0x10) ; write protection register 4 5, +OB_WRP67 EQU (_OB + 0x14) ; write protection register 6 7, +OB_WRP89 EQU (_OB + 0x18) ; write protection register 8 9, +OB_WRP1011 EQU (_OB + 0x1C) ; write protection register 10 11, + + + ;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + ;****************** Bit definition for FLASH_ACR register ***************** FLASH_ACR_LATENCY EQU 0x00000001 ; Latency diff --git a/lib/INI_BITS_FSMC.s b/lib/INI_FSMC.s similarity index 97% rename from lib/INI_BITS_FSMC.s rename to lib/INI_FSMC.s index 50bb1bf..6b6dfb8 100644 --- a/lib/INI_BITS_FSMC.s +++ b/lib/INI_FSMC.s @@ -4,14 +4,35 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro FSMC (ext. memory communication) ; +; Flexible Static Memory Controller +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Flexible Static Memory Controller -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; FSMC +_FSMC_B1 EQU (_FSMC + 0x0000) ; FSMC Bank1 registers base address +_FSMC_B1E EQU (_FSMC + 0x0104) ; FSMC Bank1E registers base address + +; Bank 1 +FSMC_B1_BTCR EQU (_FSMC_B1 + 0x00) ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), + +; Bank 2 +FSMC_B1E_BWTR EQU (_FSMC_B1E + 0x104) ; NOR/PSRAM write timing registers, + +; TODO missing some registers + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** ;***************** Bit definition for FSMC_BCR1 register ****************** diff --git a/lib/INI_BITS_I2C.s b/lib/INI_I2C.s similarity index 82% rename from lib/INI_BITS_I2C.s rename to lib/INI_I2C.s index 0a5cbeb..934c241 100644 --- a/lib/INI_BITS_I2C.s +++ b/lib/INI_I2C.s @@ -4,16 +4,51 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro I2C ; +; Inter-integrated Circuit Interface (I2C) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Inter-integrated Circuit Interface (I2C) -; +;* +;* REGISTERS +;* ;**************************************************************************** + +; I2C 1 + +I2C1_CR1 EQU (_I2C1 + 0x00) ; I2C1 Control register 1, +I2C1_CR2 EQU (_I2C1 + 0x04) ; I2C1 Control register 2, +I2C1_OAR1 EQU (_I2C1 + 0x08) ; I2C1 Own address register 1, +I2C1_OAR2 EQU (_I2C1 + 0x0C) ; I2C1 Own address register 2, +I2C1_DR EQU (_I2C1 + 0x10) ; I2C1 Data register, +I2C1_SR1 EQU (_I2C1 + 0x14) ; I2C1 Status register 1, +I2C1_SR2 EQU (_I2C1 + 0x18) ; I2C1 Status register 2, +I2C1_CCR EQU (_I2C1 + 0x1C) ; I2C1 Clock control register, +I2C1_TRISE EQU (_I2C1 + 0x20) ; I2C1 TRISE register, + +; I2C 2 + +I2C2_CR1 EQU (_I2C2 + 0x00) ; I2C2 Control register 1, +I2C2_CR2 EQU (_I2C2 + 0x04) ; I2C2 Control register 2, +I2C2_OAR1 EQU (_I2C2 + 0x08) ; I2C2 Own address register 1, +I2C2_OAR2 EQU (_I2C2 + 0x0C) ; I2C2 Own address register 2, +I2C2_DR EQU (_I2C2 + 0x10) ; I2C2 Data register, +I2C2_SR1 EQU (_I2C2 + 0x14) ; I2C2 Status register 1, +I2C2_SR2 EQU (_I2C2 + 0x18) ; I2C2 Status register 2, +I2C2_CCR EQU (_I2C2 + 0x1C) ; I2C2 Clock control register, +I2C2_TRISE EQU (_I2C2 + 0x20) ; I2C2 TRISE register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for I2C_CR1 register ******************* I2C_CR1_PE EQU 0x0001 ; Peripheral Enable I2C_CR1_SMBUS EQU 0x0002 ; SMBus Mode diff --git a/lib/INI_BITS_LCD.s b/lib/INI_LCD.s similarity index 87% rename from lib/INI_BITS_LCD.s rename to lib/INI_LCD.s index 7c16f89..447db55 100644 --- a/lib/INI_BITS_LCD.s +++ b/lib/INI_LCD.s @@ -4,16 +4,36 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro LCD ; +; LCD Controller (LCD) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; LCD Controller (LCD) -; +;* +;* REGISTERS +;* +;**************************************************************************** + + +; LCD config + +LCD_CR EQU (_LCD + 0x00) ; LCD control register, +LCD_FCR EQU (_LCD + 0x04) ; LCD frame control register, +LCD_SR EQU (_LCD + 0x08) ; LCD status register, +LCD_CLR EQU (_LCD + 0x0C) ; LCD clear register, +LCD_RAM EQU (_LCD + 0x14) ; LCD display memory, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;****************** Bit definition for LCD_CR register ******************** LCD_CR_LCDEN EQU 0x00000001 ; LCD Enable Bit LCD_CR_VSEL EQU 0x00000002 ; Voltage source selector Bit diff --git a/lib/INI_BITS_NVIC.s b/lib/INI_NVIC.s similarity index 80% rename from lib/INI_BITS_NVIC.s rename to lib/INI_NVIC.s index 4219865..4100b61 100644 --- a/lib/INI_BITS_NVIC.s +++ b/lib/INI_NVIC.s @@ -4,15 +4,77 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro NVIC (system preruseni) ; +; Nested Vectored Interrupt Controller (NVIC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Nested Vectored Interrupt Controller (NVIC) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; NVIC + +NVIC_ISER0 EQU (_NVIC + 0x000) ; (R/W) Interrupt Set Enable Register +NVIC_ISER1 EQU (_NVIC + 0x004) ; (R/W) Interrupt Set Enable Register +NVIC_ISER2 EQU (_NVIC + 0x008) ; (R/W) Interrupt Set Enable Register +NVIC_ISER3 EQU (_NVIC + 0x00C) ; (R/W) Interrupt Set Enable Register +NVIC_ISER4 EQU (_NVIC + 0x010) ; (R/W) Interrupt Set Enable Register +NVIC_ISER5 EQU (_NVIC + 0x014) ; (R/W) Interrupt Set Enable Register +NVIC_ISER6 EQU (_NVIC + 0x018) ; (R/W) Interrupt Set Enable Register +NVIC_ISER7 EQU (_NVIC + 0x01C) ; (R/W) Interrupt Set Enable Register +NVIC_ISER8 EQU (_NVIC + 0x020) ; (R/W) Interrupt Set Enable Register + +NVIC_ICER0 EQU (_NVIC + 0x080) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER1 EQU (_NVIC + 0x084) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER2 EQU (_NVIC + 0x088) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER3 EQU (_NVIC + 0x08C) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER4 EQU (_NVIC + 0x090) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER5 EQU (_NVIC + 0x094) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER6 EQU (_NVIC + 0x098) ; (R/W) Interrupt Clear Enable Register +NVIC_ICER7 EQU (_NVIC + 0x09C) ; (R/W) Interrupt Clear Enable Register + +NVIC_ISPR0 EQU (_NVIC + 0x100) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR1 EQU (_NVIC + 0x104) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR2 EQU (_NVIC + 0x108) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR3 EQU (_NVIC + 0x10C) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR4 EQU (_NVIC + 0x110) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR5 EQU (_NVIC + 0x114) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR6 EQU (_NVIC + 0x118) ; (R/W) Interrupt Set Pending Register +NVIC_ISPR7 EQU (_NVIC + 0x11C) ; (R/W) Interrupt Set Pending Register + +NVIC_ICPR0 EQU (_NVIC + 0x180) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR1 EQU (_NVIC + 0x184) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR2 EQU (_NVIC + 0x188) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR3 EQU (_NVIC + 0x18C) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR4 EQU (_NVIC + 0x190) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR5 EQU (_NVIC + 0x194) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR6 EQU (_NVIC + 0x198) ; (R/W) Interrupt Clear Pending Register +NVIC_ICPR7 EQU (_NVIC + 0x19C) ; (R/W) Interrupt Clear Pending Register + +NVIC_IABR0 EQU (_NVIC + 0x200) ; (R/W) Interrupt Active bit Register +NVIC_IABR1 EQU (_NVIC + 0x204) ; (R/W) Interrupt Active bit Register +NVIC_IABR2 EQU (_NVIC + 0x208) ; (R/W) Interrupt Active bit Register +NVIC_IABR3 EQU (_NVIC + 0x20C) ; (R/W) Interrupt Active bit Register +NVIC_IABR4 EQU (_NVIC + 0x210) ; (R/W) Interrupt Active bit Register +NVIC_IABR5 EQU (_NVIC + 0x214) ; (R/W) Interrupt Active bit Register +NVIC_IABR6 EQU (_NVIC + 0x218) ; (R/W) Interrupt Active bit Register +NVIC_IABR7 EQU (_NVIC + 0x21C) ; (R/W) Interrupt Active bit Register + +NVIC_IP EQU (_NVIC + 0x300) ; (R/W) Interrupt Priority Register (8Bit wide) +240 +NVIC_STIR EQU (_NVIC + 0xE00) ; ( /W) Software Trigger Interrupt Register + + + ;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + ;***************** Bit definition for NVIC_ISER register ****************** NVIC_ISER_SETENA EQU 0xFFFFFFFF ; Interrupt set enable bits diff --git a/lib/INI_BITS_OPAMP.s b/lib/INI_OPAMP.s similarity index 89% rename from lib/INI_BITS_OPAMP.s rename to lib/INI_OPAMP.s index e98f554..9667be7 100644 --- a/lib/INI_BITS_OPAMP.s +++ b/lib/INI_OPAMP.s @@ -4,16 +4,32 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro OPAMP ; +; Operational Amplifier (OPAMP) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Operational Amplifier (OPAMP) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; Op Amplifier module + +OPAMP_CSR EQU (_OPAMP + 0x00) ; OPAMP control/status register, +OPAMP_OTR EQU (_OPAMP + 0x04) ; OPAMP offset trimming register for normal mode, +OPAMP_LPOTR EQU (_OPAMP + 0x08) ; OPAMP offset trimming register for low power mode, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;****************** Bit definition for OPAMP_CSR register ***************** OPAMP_CSR_OPA1PD EQU 0x00000001 ; OPAMP1 disable OPAMP_CSR_S3SEL1 EQU 0x00000002 ; Switch 3 for OPAMP1 Enable diff --git a/lib/INI_BITS_PWR.s b/lib/INI_PWR.s similarity index 87% rename from lib/INI_BITS_PWR.s rename to lib/INI_PWR.s index 687acd3..6dc8a9f 100644 --- a/lib/INI_BITS_PWR.s +++ b/lib/INI_PWR.s @@ -4,16 +4,31 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro PWR (napajeni, sleep...) ; +; Power Control (PWR) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Power Control (PWR) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; Power control registers + +PWR_CR EQU (_PWR + 0x00) ; PWR power control register, +PWR_CSR EQU (_PWR + 0x04) ; PWR power control/status register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;******************* Bit definition for PWR_CR register ******************* PWR_CR_LPSDSR EQU 0x0001 ; Low-power deepsleep/sleep/low power run PWR_CR_PDDS EQU 0x0002 ; Power Down Deepsleep diff --git a/lib/INI_BITS_RCC.s b/lib/INI_RCC.s similarity index 94% rename from lib/INI_BITS_RCC.s rename to lib/INI_RCC.s index b746e9b..c878e6f 100644 --- a/lib/INI_BITS_RCC.s +++ b/lib/INI_RCC.s @@ -4,16 +4,44 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro RCC (nastaveni hodin) ; +; Reset and Clock Control (RCC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** +;**************************************************************************** +;* +;* REGISTERS +;* +;**************************************************************************** + + +; RCC registers + +RCC_CR EQU (_RCC + 0x00) ; RCC clock control register, +RCC_ICSCR EQU (_RCC + 0x04) ; RCC Internal clock sources calibration register, +RCC_CFGR EQU (_RCC + 0x08) ; RCC Clock configuration register, +RCC_CIR EQU (_RCC + 0x0C) ; RCC Clock interrupt register, +RCC_AHBRSTR EQU (_RCC + 0x10) ; RCC AHB peripheral reset register, +RCC_APB2RSTR EQU (_RCC + 0x14) ; RCC APB2 peripheral reset register, +RCC_APB1RSTR EQU (_RCC + 0x18) ; RCC APB1 peripheral reset register, +RCC_AHBENR EQU (_RCC + 0x1C) ; RCC AHB peripheral clock enable register, +RCC_APB2ENR EQU (_RCC + 0x20) ; RCC APB2 peripheral clock enable register, +RCC_APB1ENR EQU (_RCC + 0x24) ; RCC APB1 peripheral clock enable register, +RCC_AHBLPENR EQU (_RCC + 0x28) ; RCC AHB peripheral clock enable in low power mode register, +RCC_APB2LPENR EQU (_RCC + 0x2C) ; RCC APB2 peripheral clock enable in low power mode register, +RCC_APB1LPENR EQU (_RCC + 0x30) ; RCC APB1 peripheral clock enable in low power mode register, +RCC_CSR EQU (_RCC + 0x34) ; RCC Control/status register, + + ;**************************************************************************** -; -; Reset and Clock Control (RCC) -; +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;******************* Bit definition for RCC_CR register ******************* RCC_CR_HSION EQU 0x00000001 ; Internal High Speed clock enable RCC_CR_HSIRDY EQU 0x00000002 ; Internal High Speed clock ready flag diff --git a/lib/INI_REGS.s b/lib/INI_REGS.s deleted file mode 100644 index 45541fb..0000000 --- a/lib/INI_REGS.s +++ /dev/null @@ -1,777 +0,0 @@ -;******************************************************************************** -; SOUBOR : INI_REGS.S -; AUTOR : Petr Dousa, Ondrej Hruska -; DATUM : 10/2015 -; POPIS : Pojmenovane adresy ridicich registru -; -; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. -;******************************************************************************** - -; ----------------------- Peripherals ------------------------ - -; Special system control registers - -; SCB - - -; NVIC - -NVIC_ISER0 EQU (_NVIC + 0x000) ; (R/W) Interrupt Set Enable Register -NVIC_ISER1 EQU (_NVIC + 0x004) ; (R/W) Interrupt Set Enable Register -NVIC_ISER2 EQU (_NVIC + 0x008) ; (R/W) Interrupt Set Enable Register -NVIC_ISER3 EQU (_NVIC + 0x00C) ; (R/W) Interrupt Set Enable Register -NVIC_ISER4 EQU (_NVIC + 0x010) ; (R/W) Interrupt Set Enable Register -NVIC_ISER5 EQU (_NVIC + 0x014) ; (R/W) Interrupt Set Enable Register -NVIC_ISER6 EQU (_NVIC + 0x018) ; (R/W) Interrupt Set Enable Register -NVIC_ISER7 EQU (_NVIC + 0x01C) ; (R/W) Interrupt Set Enable Register -NVIC_ISER8 EQU (_NVIC + 0x020) ; (R/W) Interrupt Set Enable Register - -NVIC_ICER0 EQU (_NVIC + 0x080) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER1 EQU (_NVIC + 0x084) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER2 EQU (_NVIC + 0x088) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER3 EQU (_NVIC + 0x08C) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER4 EQU (_NVIC + 0x090) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER5 EQU (_NVIC + 0x094) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER6 EQU (_NVIC + 0x098) ; (R/W) Interrupt Clear Enable Register -NVIC_ICER7 EQU (_NVIC + 0x09C) ; (R/W) Interrupt Clear Enable Register - -NVIC_ISPR0 EQU (_NVIC + 0x100) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR1 EQU (_NVIC + 0x104) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR2 EQU (_NVIC + 0x108) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR3 EQU (_NVIC + 0x10C) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR4 EQU (_NVIC + 0x110) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR5 EQU (_NVIC + 0x114) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR6 EQU (_NVIC + 0x118) ; (R/W) Interrupt Set Pending Register -NVIC_ISPR7 EQU (_NVIC + 0x11C) ; (R/W) Interrupt Set Pending Register - -NVIC_ICPR0 EQU (_NVIC + 0x180) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR1 EQU (_NVIC + 0x184) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR2 EQU (_NVIC + 0x188) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR3 EQU (_NVIC + 0x18C) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR4 EQU (_NVIC + 0x190) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR5 EQU (_NVIC + 0x194) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR6 EQU (_NVIC + 0x198) ; (R/W) Interrupt Clear Pending Register -NVIC_ICPR7 EQU (_NVIC + 0x19C) ; (R/W) Interrupt Clear Pending Register - -NVIC_IABR0 EQU (_NVIC + 0x200) ; (R/W) Interrupt Active bit Register -NVIC_IABR1 EQU (_NVIC + 0x204) ; (R/W) Interrupt Active bit Register -NVIC_IABR2 EQU (_NVIC + 0x208) ; (R/W) Interrupt Active bit Register -NVIC_IABR3 EQU (_NVIC + 0x20C) ; (R/W) Interrupt Active bit Register -NVIC_IABR4 EQU (_NVIC + 0x210) ; (R/W) Interrupt Active bit Register -NVIC_IABR5 EQU (_NVIC + 0x214) ; (R/W) Interrupt Active bit Register -NVIC_IABR6 EQU (_NVIC + 0x218) ; (R/W) Interrupt Active bit Register -NVIC_IABR7 EQU (_NVIC + 0x21C) ; (R/W) Interrupt Active bit Register - -NVIC_IP EQU (_NVIC + 0x300) ; (R/W) Interrupt Priority Register (8Bit wide) +240 -NVIC_STIR EQU (_NVIC + 0xE00) ; ( /W) Software Trigger Interrupt Register - - - -; Timer 2 - -TIM2_CR1 EQU (_TIM2 + 0x00) ; TIM control register 1, -TIM2_CR2 EQU (_TIM2 + 0x04) ; TIM control register 2, -TIM2_SMCR EQU (_TIM2 + 0x08) ; TIM slave mode control register, -TIM2_DIER EQU (_TIM2 + 0x0C) ; TIM DMA/interrupt enable register, -TIM2_SR EQU (_TIM2 + 0x10) ; TIM status register, -TIM2_EGR EQU (_TIM2 + 0x14) ; TIM event generation register, -TIM2_CCMR1 EQU (_TIM2 + 0x18) ; TIM capture/compare mode register 1, -TIM2_CCMR2 EQU (_TIM2 + 0x1C) ; TIM capture/compare mode register 2, -TIM2_CCER EQU (_TIM2 + 0x20) ; TIM capture/compare enable register, -TIM2_CNT EQU (_TIM2 + 0x24) ; TIM counter register, -TIM2_PSC EQU (_TIM2 + 0x28) ; TIM prescaler, -TIM2_ARR EQU (_TIM2 + 0x2C) ; TIM auto-reload register, -TIM2_CCR1 EQU (_TIM2 + 0x34) ; TIM capture/compare register 1, -TIM2_CCR2 EQU (_TIM2 + 0x38) ; TIM capture/compare register 2, -TIM2_CCR3 EQU (_TIM2 + 0x3C) ; TIM capture/compare register 3, -TIM2_CCR4 EQU (_TIM2 + 0x40) ; TIM capture/compare register 4, -TIM2_DCR EQU (_TIM2 + 0x48) ; TIM DMA control register, -TIM2_DMAR EQU (_TIM2 + 0x4C) ; TIM DMA address for full transfer, -TIM2_OR EQU (_TIM2 + 0x50) ; TIM option register, - -; Timer 3 - -TIM3_CR1 EQU (_TIM3 + 0x00) ; TIM control register 1, -TIM3_CR2 EQU (_TIM3 + 0x04) ; TIM control register 2, -TIM3_SMCR EQU (_TIM3 + 0x08) ; TIM slave mode control register, -TIM3_DIER EQU (_TIM3 + 0x0C) ; TIM DMA/interrupt enable register, -TIM3_SR EQU (_TIM3 + 0x10) ; TIM status register, -TIM3_EGR EQU (_TIM3 + 0x14) ; TIM event generation register, -TIM3_CCMR1 EQU (_TIM3 + 0x18) ; TIM capture/compare mode register 1, -TIM3_CCMR2 EQU (_TIM3 + 0x1C) ; TIM capture/compare mode register 2, -TIM3_CCER EQU (_TIM3 + 0x20) ; TIM capture/compare enable register, -TIM3_CNT EQU (_TIM3 + 0x24) ; TIM counter register, -TIM3_PSC EQU (_TIM3 + 0x28) ; TIM prescaler, -TIM3_ARR EQU (_TIM3 + 0x2C) ; TIM auto-reload register, -TIM3_CCR1 EQU (_TIM3 + 0x34) ; TIM capture/compare register 1, -TIM3_CCR2 EQU (_TIM3 + 0x38) ; TIM capture/compare register 2, -TIM3_CCR3 EQU (_TIM3 + 0x3C) ; TIM capture/compare register 3, -TIM3_CCR4 EQU (_TIM3 + 0x40) ; TIM capture/compare register 4, -TIM3_DCR EQU (_TIM3 + 0x48) ; TIM DMA control register, -TIM3_DMAR EQU (_TIM3 + 0x4C) ; TIM DMA address for full transfer, -TIM3_OR EQU (_TIM3 + 0x50) ; TIM option register, - -; Timer 4 - -TIM4_CR1 EQU (_TIM4 + 0x00) ; TIM control register 1, -TIM4_CR2 EQU (_TIM4 + 0x04) ; TIM control register 2, -TIM4_SMCR EQU (_TIM4 + 0x08) ; TIM slave mode control register, -TIM4_DIER EQU (_TIM4 + 0x0C) ; TIM DMA/interrupt enable register, -TIM4_SR EQU (_TIM4 + 0x10) ; TIM status register, -TIM4_EGR EQU (_TIM4 + 0x14) ; TIM event generation register, -TIM4_CCMR1 EQU (_TIM4 + 0x18) ; TIM capture/compare mode register 1, -TIM4_CCMR2 EQU (_TIM4 + 0x1C) ; TIM capture/compare mode register 2, -TIM4_CCER EQU (_TIM4 + 0x20) ; TIM capture/compare enable register, -TIM4_CNT EQU (_TIM4 + 0x24) ; TIM counter register, -TIM4_PSC EQU (_TIM4 + 0x28) ; TIM prescaler, -TIM4_ARR EQU (_TIM4 + 0x2C) ; TIM auto-reload register, -TIM4_CCR1 EQU (_TIM4 + 0x34) ; TIM capture/compare register 1, -TIM4_CCR2 EQU (_TIM4 + 0x38) ; TIM capture/compare register 2, -TIM4_CCR3 EQU (_TIM4 + 0x3C) ; TIM capture/compare register 3, -TIM4_CCR4 EQU (_TIM4 + 0x40) ; TIM capture/compare register 4, -TIM4_DCR EQU (_TIM4 + 0x48) ; TIM DMA control register, -TIM4_DMAR EQU (_TIM4 + 0x4C) ; TIM DMA address for full transfer, -TIM4_OR EQU (_TIM4 + 0x50) ; TIM option register, - -; Timer 5 - -TIM5_CR1 EQU (_TIM5 + 0x00) ; TIM control register 1, -TIM5_CR2 EQU (_TIM5 + 0x04) ; TIM control register 2, -TIM5_SMCR EQU (_TIM5 + 0x08) ; TIM slave mode control register, -TIM5_DIER EQU (_TIM5 + 0x0C) ; TIM DMA/interrupt enable register, -TIM5_SR EQU (_TIM5 + 0x10) ; TIM status register, -TIM5_EGR EQU (_TIM5 + 0x14) ; TIM event generation register, -TIM5_CCMR1 EQU (_TIM5 + 0x18) ; TIM capture/compare mode register 1, -TIM5_CCMR2 EQU (_TIM5 + 0x1C) ; TIM capture/compare mode register 2, -TIM5_CCER EQU (_TIM5 + 0x20) ; TIM capture/compare enable register, -TIM5_CNT EQU (_TIM5 + 0x24) ; TIM counter register, -TIM5_PSC EQU (_TIM5 + 0x28) ; TIM prescaler, -TIM5_ARR EQU (_TIM5 + 0x2C) ; TIM auto-reload register, -TIM5_CCR1 EQU (_TIM5 + 0x34) ; TIM capture/compare register 1, -TIM5_CCR2 EQU (_TIM5 + 0x38) ; TIM capture/compare register 2, -TIM5_CCR3 EQU (_TIM5 + 0x3C) ; TIM capture/compare register 3, -TIM5_CCR4 EQU (_TIM5 + 0x40) ; TIM capture/compare register 4, -TIM5_DCR EQU (_TIM5 + 0x48) ; TIM DMA control register, -TIM5_DMAR EQU (_TIM5 + 0x4C) ; TIM DMA address for full transfer, -TIM5_OR EQU (_TIM5 + 0x50) ; TIM option register, - -; Timer 6 - -TIM6_CR1 EQU (_TIM6 + 0x00) ; TIM control register 1, -TIM6_CR2 EQU (_TIM6 + 0x04) ; TIM control register 2, -TIM6_SMCR EQU (_TIM6 + 0x08) ; TIM slave mode control register, -TIM6_DIER EQU (_TIM6 + 0x0C) ; TIM DMA/interrupt enable register, -TIM6_SR EQU (_TIM6 + 0x10) ; TIM status register, -TIM6_EGR EQU (_TIM6 + 0x14) ; TIM event generation register, -TIM6_CCMR1 EQU (_TIM6 + 0x18) ; TIM capture/compare mode register 1, -TIM6_CCMR2 EQU (_TIM6 + 0x1C) ; TIM capture/compare mode register 2, -TIM6_CCER EQU (_TIM6 + 0x20) ; TIM capture/compare enable register, -TIM6_CNT EQU (_TIM6 + 0x24) ; TIM counter register, -TIM6_PSC EQU (_TIM6 + 0x28) ; TIM prescaler, -TIM6_ARR EQU (_TIM6 + 0x2C) ; TIM auto-reload register, -TIM6_CCR1 EQU (_TIM6 + 0x34) ; TIM capture/compare register 1, -TIM6_CCR2 EQU (_TIM6 + 0x38) ; TIM capture/compare register 2, -TIM6_CCR3 EQU (_TIM6 + 0x3C) ; TIM capture/compare register 3, -TIM6_CCR4 EQU (_TIM6 + 0x40) ; TIM capture/compare register 4, -TIM6_DCR EQU (_TIM6 + 0x48) ; TIM DMA control register, -TIM6_DMAR EQU (_TIM6 + 0x4C) ; TIM DMA address for full transfer, -TIM6_OR EQU (_TIM6 + 0x50) ; TIM option register, - -; Timer 7 - -TIM7_CR1 EQU (_TIM7 + 0x00) ; TIM control register 1, -TIM7_CR2 EQU (_TIM7 + 0x04) ; TIM control register 2, -TIM7_SMCR EQU (_TIM7 + 0x08) ; TIM slave mode control register, -TIM7_DIER EQU (_TIM7 + 0x0C) ; TIM DMA/interrupt enable register, -TIM7_SR EQU (_TIM7 + 0x10) ; TIM status register, -TIM7_EGR EQU (_TIM7 + 0x14) ; TIM event generation register, -TIM7_CCMR1 EQU (_TIM7 + 0x18) ; TIM capture/compare mode register 1, -TIM7_CCMR2 EQU (_TIM7 + 0x1C) ; TIM capture/compare mode register 2, -TIM7_CCER EQU (_TIM7 + 0x20) ; TIM capture/compare enable register, -TIM7_CNT EQU (_TIM7 + 0x24) ; TIM counter register, -TIM7_PSC EQU (_TIM7 + 0x28) ; TIM prescaler, -TIM7_ARR EQU (_TIM7 + 0x2C) ; TIM auto-reload register, -TIM7_CCR1 EQU (_TIM7 + 0x34) ; TIM capture/compare register 1, -TIM7_CCR2 EQU (_TIM7 + 0x38) ; TIM capture/compare register 2, -TIM7_CCR3 EQU (_TIM7 + 0x3C) ; TIM capture/compare register 3, -TIM7_CCR4 EQU (_TIM7 + 0x40) ; TIM capture/compare register 4, -TIM7_DCR EQU (_TIM7 + 0x48) ; TIM DMA control register, -TIM7_DMAR EQU (_TIM7 + 0x4C) ; TIM DMA address for full transfer, -TIM7_OR EQU (_TIM7 + 0x50) ; TIM option register, - -; Timer 9 - -TIM9_CR1 EQU (_TIM9 + 0x00) ; TIM control register 1, -TIM9_CR2 EQU (_TIM9 + 0x04) ; TIM control register 2, -TIM9_SMCR EQU (_TIM9 + 0x08) ; TIM slave mode control register, -TIM9_DIER EQU (_TIM9 + 0x0C) ; TIM DMA/interrupt enable register, -TIM9_SR EQU (_TIM9 + 0x10) ; TIM status register, -TIM9_EGR EQU (_TIM9 + 0x14) ; TIM event generation register, -TIM9_CCMR1 EQU (_TIM9 + 0x18) ; TIM capture/compare mode register 1, -TIM9_CCMR2 EQU (_TIM9 + 0x1C) ; TIM capture/compare mode register 2, -TIM9_CCER EQU (_TIM9 + 0x20) ; TIM capture/compare enable register, -TIM9_CNT EQU (_TIM9 + 0x24) ; TIM counter register, -TIM9_PSC EQU (_TIM9 + 0x28) ; TIM prescaler, -TIM9_ARR EQU (_TIM9 + 0x2C) ; TIM auto-reload register, -TIM9_CCR1 EQU (_TIM9 + 0x34) ; TIM capture/compare register 1, -TIM9_CCR2 EQU (_TIM9 + 0x38) ; TIM capture/compare register 2, -TIM9_CCR3 EQU (_TIM9 + 0x3C) ; TIM capture/compare register 3, -TIM9_CCR4 EQU (_TIM9 + 0x40) ; TIM capture/compare register 4, -TIM9_DCR EQU (_TIM9 + 0x48) ; TIM DMA control register, -TIM9_DMAR EQU (_TIM9 + 0x4C) ; TIM DMA address for full transfer, -TIM9_OR EQU (_TIM9 + 0x50) ; TIM option register, - -; Timer 10 - -TIM10_CR1 EQU (_TIM10 + 0x00) ; TIM control register 1, -TIM10_CR2 EQU (_TIM10 + 0x04) ; TIM control register 2, -TIM10_SMCR EQU (_TIM10 + 0x08) ; TIM slave mode control register, -TIM10_DIER EQU (_TIM10 + 0x0C) ; TIM DMA/interrupt enable register, -TIM10_SR EQU (_TIM10 + 0x10) ; TIM status register, -TIM10_EGR EQU (_TIM10 + 0x14) ; TIM event generation register, -TIM10_CCMR1 EQU (_TIM10 + 0x18) ; TIM capture/compare mode register 1, -TIM10_CCMR2 EQU (_TIM10 + 0x1C) ; TIM capture/compare mode register 2, -TIM10_CCER EQU (_TIM10 + 0x20) ; TIM capture/compare enable register, -TIM10_CNT EQU (_TIM10 + 0x24) ; TIM counter register, -TIM10_PSC EQU (_TIM10 + 0x28) ; TIM prescaler, -TIM10_ARR EQU (_TIM10 + 0x2C) ; TIM auto-reload register, -TIM10_CCR1 EQU (_TIM10 + 0x34) ; TIM capture/compare register 1, -TIM10_CCR2 EQU (_TIM10 + 0x38) ; TIM capture/compare register 2, -TIM10_CCR3 EQU (_TIM10 + 0x3C) ; TIM capture/compare register 3, -TIM10_CCR4 EQU (_TIM10 + 0x40) ; TIM capture/compare register 4, -TIM10_DCR EQU (_TIM10 + 0x48) ; TIM DMA control register, -TIM10_DMAR EQU (_TIM10 + 0x4C) ; TIM DMA address for full transfer, -TIM10_OR EQU (_TIM10 + 0x50) ; TIM option register, - -; Timer 11 - -TIM11_CR1 EQU (_TIM11 + 0x00) ; TIM control register 1, -TIM11_CR2 EQU (_TIM11 + 0x04) ; TIM control register 2, -TIM11_SMCR EQU (_TIM11 + 0x08) ; TIM slave mode control register, -TIM11_DIER EQU (_TIM11 + 0x0C) ; TIM DMA/interrupt enable register, -TIM11_SR EQU (_TIM11 + 0x10) ; TIM status register, -TIM11_EGR EQU (_TIM11 + 0x14) ; TIM event generation register, -TIM11_CCMR1 EQU (_TIM11 + 0x18) ; TIM capture/compare mode register 1, -TIM11_CCMR2 EQU (_TIM11 + 0x1C) ; TIM capture/compare mode register 2, -TIM11_CCER EQU (_TIM11 + 0x20) ; TIM capture/compare enable register, -TIM11_CNT EQU (_TIM11 + 0x24) ; TIM counter register, -TIM11_PSC EQU (_TIM11 + 0x28) ; TIM prescaler, -TIM11_ARR EQU (_TIM11 + 0x2C) ; TIM auto-reload register, -TIM11_CCR1 EQU (_TIM11 + 0x34) ; TIM capture/compare register 1, -TIM11_CCR2 EQU (_TIM11 + 0x38) ; TIM capture/compare register 2, -TIM11_CCR3 EQU (_TIM11 + 0x3C) ; TIM capture/compare register 3, -TIM11_CCR4 EQU (_TIM11 + 0x40) ; TIM capture/compare register 4, -TIM11_DCR EQU (_TIM11 + 0x48) ; TIM DMA control register, -TIM11_DMAR EQU (_TIM11 + 0x4C) ; TIM DMA address for full transfer, -TIM11_OR EQU (_TIM11 + 0x50) ; TIM option register, - - -; LCD config - -LCD_CR EQU (_LCD + 0x00) ; LCD control register, -LCD_FCR EQU (_LCD + 0x04) ; LCD frame control register, -LCD_SR EQU (_LCD + 0x08) ; LCD status register, -LCD_CLR EQU (_LCD + 0x0C) ; LCD clear register, -LCD_RAM EQU (_LCD + 0x14) ; LCD display memory, - - -; RTC - -RTC_TR EQU (_RTC + 0x00) ; RTC time register, -RTC_DR EQU (_RTC + 0x04) ; RTC date register, -RTC_CR EQU (_RTC + 0x08) ; RTC control register, -RTC_ISR EQU (_RTC + 0x0C) ; RTC initialization and status register, -RTC_PRER EQU (_RTC + 0x10) ; RTC prescaler register, -RTC_WUTR EQU (_RTC + 0x14) ; RTC wakeup timer register, -RTC_CALIBR EQU (_RTC + 0x18) ; RTC calibration register, -RTC_ALRMAR EQU (_RTC + 0x1C) ; RTC alarm A register, -RTC_ALRMBR EQU (_RTC + 0x20) ; RTC alarm B register, -RTC_WPR EQU (_RTC + 0x24) ; RTC write protection register, -RTC_SSR EQU (_RTC + 0x28) ; RTC sub second register, -RTC_SHIFTR EQU (_RTC + 0x2C) ; RTC shift control register, -RTC_TSTR EQU (_RTC + 0x30) ; RTC time stamp time register, -RTC_TSDR EQU (_RTC + 0x34) ; RTC time stamp date register, -RTC_TSSSR EQU (_RTC + 0x38) ; RTC time-stamp sub second register, -RTC_CALR EQU (_RTC + 0x3C) ; RRTC calibration register, -RTC_TAFCR EQU (_RTC + 0x40) ; RTC tamper and alternate function configuration register, -RTC_ALRMASSR EQU (_RTC + 0x44) ; RTC alarm A sub second register, -RTC_ALRMBSSR EQU (_RTC + 0x48) ; RTC alarm B sub second register, -RTC_BKP0R_REG EQU (_RTC + 0x50) ; RTC backup register 0, -RTC_BKP1R_REG EQU (_RTC + 0x54) ; RTC backup register 1, -RTC_BKP2R_REG EQU (_RTC + 0x58) ; RTC backup register 2, -RTC_BKP3R_REG EQU (_RTC + 0x5C) ; RTC backup register 3, -RTC_BKP4R_REG EQU (_RTC + 0x60) ; RTC backup register 4, -RTC_BKP5R_REG EQU (_RTC + 0x64) ; RTC backup register 5, -RTC_BKP6R_REG EQU (_RTC + 0x68) ; RTC backup register 6, -RTC_BKP7R_REG EQU (_RTC + 0x6C) ; RTC backup register 7, -RTC_BKP8R_REG EQU (_RTC + 0x70) ; RTC backup register 8, -RTC_BKP9R_REG EQU (_RTC + 0x74) ; RTC backup register 9, -RTC_BKP10R_REG EQU (_RTC + 0x78) ; RTC backup register 10, -RTC_BKP11R_REG EQU (_RTC + 0x7C) ; RTC backup register 11, -RTC_BKP12R_REG EQU (_RTC + 0x80) ; RTC backup register 12, -RTC_BKP13R_REG EQU (_RTC + 0x84) ; RTC backup register 13, -RTC_BKP14R_REG EQU (_RTC + 0x88) ; RTC backup register 14, -RTC_BKP15R_REG EQU (_RTC + 0x8C) ; RTC backup register 15, -RTC_BKP16R_REG EQU (_RTC + 0x90) ; RTC backup register 16, -RTC_BKP17R_REG EQU (_RTC + 0x94) ; RTC backup register 17, -RTC_BKP18R_REG EQU (_RTC + 0x98) ; RTC backup register 18, -RTC_BKP19R_REG EQU (_RTC + 0x9C) ; RTC backup register 19, -RTC_BKP20R_REG EQU (_RTC + 0xA0) ; RTC backup register 20, -RTC_BKP21R_REG EQU (_RTC + 0xA4) ; RTC backup register 21, -RTC_BKP22R_REG EQU (_RTC + 0xA8) ; RTC backup register 22, -RTC_BKP23R_REG EQU (_RTC + 0xAC) ; RTC backup register 23, -RTC_BKP24R_REG EQU (_RTC + 0xB0) ; RTC backup register 24, -RTC_BKP25R_REG EQU (_RTC + 0xB4) ; RTC backup register 25, -RTC_BKP26R_REG EQU (_RTC + 0xB8) ; RTC backup register 26, -RTC_BKP27R_REG EQU (_RTC + 0xBC) ; RTC backup register 27, -RTC_BKP28R_REG EQU (_RTC + 0xC0) ; RTC backup register 28, -RTC_BKP29R_REG EQU (_RTC + 0xC4) ; RTC backup register 29, -RTC_BKP30R_REG EQU (_RTC + 0xC8) ; RTC backup register 30, -RTC_BKP31R_REG EQU (_RTC + 0xCC) ; RTC backup register 31, - - -; Window Watchdog - -WWDG_CR EQU (_WWDG + 0x00) ; WWDG Control register, -WWDG_CFR EQU (_WWDG + 0x04) ; WWDG Configuration register, -WWDG_SR EQU (_WWDG + 0x08) ; WWDG Status register, - - -; Independent Watchdog - -IWDG_KR EQU (_IWDG + 0x00) ; Key register, -IWDG_PR EQU (_IWDG + 0x04) ; Prescaler register, -IWDG_RLR EQU (_IWDG + 0x08) ; Reload register, -IWDG_SR EQU (_IWDG + 0x0C) ; Status register, - - -; SPI 2 - -SPI2_CR1 EQU (_SPI2 + 0x00) ; SPI2 control register 1 (not used in I2S mode), -SPI2_CR2 EQU (_SPI2 + 0x04) ; SPI2 control register 2, -SPI2_SR EQU (_SPI2 + 0x08) ; SPI2 status register, -SPI2_DR EQU (_SPI2 + 0x0C) ; SPI2 data register, -SPI2_CRCPR EQU (_SPI2 + 0x10) ; SPI2 CRC polynomial register (not used in I2S mode), -SPI2_RXCRCR EQU (_SPI2 + 0x14) ; SPI2 RX CRC register (not used in I2S mode), -SPI2_TXCRCR EQU (_SPI2 + 0x18) ; SPI2 TX CRC register (not used in I2S mode), -SPI2_I2SCFGR EQU (_SPI2 + 0x1C) ; SPI2_I2S configuration register, -SPI2_I2SPR EQU (_SPI2 + 0x20) ; SPI2_I2S prescaler register, - -; SPI 3 - -SPI3_CR1 EQU (_SPI3 + 0x00) ; SPI3 control register 1 (not used in I2S mode), -SPI3_CR2 EQU (_SPI3 + 0x04) ; SPI3 control register 2, -SPI3_SR EQU (_SPI3 + 0x08) ; SPI3 status register, -SPI3_DR EQU (_SPI3 + 0x0C) ; SPI3 data register, -SPI3_CRCPR EQU (_SPI3 + 0x10) ; SPI3 CRC polynomial register (not used in I2S mode), -SPI3_RXCRCR EQU (_SPI3 + 0x14) ; SPI3 RX CRC register (not used in I2S mode), -SPI3_TXCRCR EQU (_SPI3 + 0x18) ; SPI3 TX CRC register (not used in I2S mode), -SPI3_I2SCFGR EQU (_SPI3 + 0x1C) ; SPI3_I2S configuration register, -SPI3_I2SPR EQU (_SPI3 + 0x20) ; SPI3_I2S prescaler register, - - -; USART 1 - -USART1_SR EQU (_USART1 + 0x00) ; USART1 Status register, -USART1_DR EQU (_USART1 + 0x04) ; USART1 Data register, -USART1_BRR EQU (_USART1 + 0x08) ; USART1 Baud rate register, -USART1_CR1 EQU (_USART1 + 0x0C) ; USART1 Control register 1, -USART1_CR2 EQU (_USART1 + 0x10) ; USART1 Control register 2, -USART1_CR3 EQU (_USART1 + 0x14) ; USART1 Control register 3, -USART1_GTPR EQU (_USART1 + 0x18) ; USART1 Guard time and prescaler register, - -; USART 2 - -USART2_SR EQU (_USART2 + 0x00) ; USART2 Status register, -USART2_DR EQU (_USART2 + 0x04) ; USART2 Data register, -USART2_BRR EQU (_USART2 + 0x08) ; USART2 Baud rate register, -USART2_CR1 EQU (_USART2 + 0x0C) ; USART2 Control register 1, -USART2_CR2 EQU (_USART2 + 0x10) ; USART2 Control register 2, -USART2_CR3 EQU (_USART2 + 0x14) ; USART2 Control register 3, -USART2_GTPR EQU (_USART2 + 0x18) ; USART2 Guard time and prescaler register, - -; USART 3 - -USART3_SR EQU (_USART3 + 0x00) ; USART3 Status register, -USART3_DR EQU (_USART3 + 0x04) ; USART3 Data register, -USART3_BRR EQU (_USART3 + 0x08) ; USART3 Baud rate register, -USART3_CR1 EQU (_USART3 + 0x0C) ; USART3 Control register 1, -USART3_CR2 EQU (_USART3 + 0x10) ; USART3 Control register 2, -USART3_CR3 EQU (_USART3 + 0x14) ; USART3 Control register 3, -USART3_GTPR EQU (_USART3 + 0x18) ; USART3 Guard time and prescaler register, - -; USART 4 - -UART4_SR EQU (_UART4 + 0x00) ; UART4 Status register, -UART4_DR EQU (_UART4 + 0x04) ; UART4 Data register, -UART4_BRR EQU (_UART4 + 0x08) ; UART4 Baud rate register, -UART4_CR1 EQU (_UART4 + 0x0C) ; UART4 Control register 1, -UART4_CR2 EQU (_UART4 + 0x10) ; UART4 Control register 2, -UART4_CR3 EQU (_UART4 + 0x14) ; UART4 Control register 3, -UART4_GTPR EQU (_UART4 + 0x18) ; UART4 Guard time and prescaler register, - -; USART 5 - -UART5_SR EQU (_UART5 + 0x00) ; UART5 Status register, -UART5_DR EQU (_UART5 + 0x04) ; UART5 Data register, -UART5_BRR EQU (_UART5 + 0x08) ; UART5 Baud rate register, -UART5_CR1 EQU (_UART5 + 0x0C) ; UART5 Control register 1, -UART5_CR2 EQU (_UART5 + 0x10) ; UART5 Control register 2, -UART5_CR3 EQU (_UART5 + 0x14) ; UART5 Control register 3, -UART5_GTPR EQU (_UART5 + 0x18) ; UART5 Guard time and prescaler register, - - -; I2C 1 - -I2C1_CR1 EQU (_I2C1 + 0x00) ; I2C1 Control register 1, -I2C1_CR2 EQU (_I2C1 + 0x04) ; I2C1 Control register 2, -I2C1_OAR1 EQU (_I2C1 + 0x08) ; I2C1 Own address register 1, -I2C1_OAR2 EQU (_I2C1 + 0x0C) ; I2C1 Own address register 2, -I2C1_DR EQU (_I2C1 + 0x10) ; I2C1 Data register, -I2C1_SR1 EQU (_I2C1 + 0x14) ; I2C1 Status register 1, -I2C1_SR2 EQU (_I2C1 + 0x18) ; I2C1 Status register 2, -I2C1_CCR EQU (_I2C1 + 0x1C) ; I2C1 Clock control register, -I2C1_TRISE EQU (_I2C1 + 0x20) ; I2C1 TRISE register, - -; I2C 2 - -I2C2_CR1 EQU (_I2C2 + 0x00) ; I2C2 Control register 1, -I2C2_CR2 EQU (_I2C2 + 0x04) ; I2C2 Control register 2, -I2C2_OAR1 EQU (_I2C2 + 0x08) ; I2C2 Own address register 1, -I2C2_OAR2 EQU (_I2C2 + 0x0C) ; I2C2 Own address register 2, -I2C2_DR EQU (_I2C2 + 0x10) ; I2C2 Data register, -I2C2_SR1 EQU (_I2C2 + 0x14) ; I2C2 Status register 1, -I2C2_SR2 EQU (_I2C2 + 0x18) ; I2C2 Status register 2, -I2C2_CCR EQU (_I2C2 + 0x1C) ; I2C2 Clock control register, -I2C2_TRISE EQU (_I2C2 + 0x20) ; I2C2 TRISE register, - - -; Power control registers - -PWR_CR EQU (_PWR + 0x00) ; PWR power control register, -PWR_CSR EQU (_PWR + 0x04) ; PWR power control/status register, - - -; D/A converter - -DAC_CR EQU (_DAC + 0x00) ; DAC control register, -DAC_SWTRIGR EQU (_DAC + 0x04) ; DAC software trigger register, -DAC_DHR12R1 EQU (_DAC + 0x08) ; DAC channel1 12-bit right-aligned data holding register, -DAC_DHR12L1 EQU (_DAC + 0x0C) ; DAC channel1 12-bit left aligned data holding register, -DAC_DHR8R1 EQU (_DAC + 0x10) ; DAC channel1 8-bit right aligned data holding register, -DAC_DHR12R2 EQU (_DAC + 0x14) ; DAC channel2 12-bit right aligned data holding register, -DAC_DHR12L2 EQU (_DAC + 0x18) ; DAC channel2 12-bit left aligned data holding register, -DAC_DHR8R2 EQU (_DAC + 0x1C) ; DAC channel2 8-bit right-aligned data holding register, -DAC_DHR12RD EQU (_DAC + 0x20) ; Dual DAC 12-bit right-aligned data holding register, -DAC_DHR12LD EQU (_DAC + 0x24) ; DUAL DAC 12-bit left aligned data holding register, -DAC_DHR8RD EQU (_DAC + 0x28) ; DUAL DAC 8-bit right aligned data holding register, -DAC_DOR1 EQU (_DAC + 0x2C) ; DAC channel1 data output register, -DAC_DOR2 EQU (_DAC + 0x30) ; DAC channel2 data output register, -DAC_SR EQU (_DAC + 0x34) ; DAC status register, - - -; Comparator - -COMP_CSR EQU (_COMP + 0x00) ; COMP comparator control and status register, - - -; RI - -RI_ICR EQU (_RI + 0x04) ; RI input capture register, -RI_ASCR1 EQU (_RI + 0x08) ; RI analog switches control register, -RI_ASCR2 EQU (_RI + 0x0C) ; RI analog switch control register 2, -RI_HYSCR1 EQU (_RI + 0x10) ; RI hysteresis control register 1, -RI_HYSCR2 EQU (_RI + 0x14) ; RI Hysteresis control register 2, -RI_HYSCR3 EQU (_RI + 0x18) ; RI Hysteresis control register 3, -RI_HYSCR4 EQU (_RI + 0x1C) ; RI Hysteresis control register 4, -RI_ASMR1 EQU (_RI + 0x20) ; RI Analog switch mode register 1, -RI_CMR1 EQU (_RI + 0x24) ; RI Channel mask register 1, -RI_CICR1 EQU (_RI + 0x28) ; RI Channel identification for capture register 1, -RI_ASMR2 EQU (_RI + 0x2C) ; RI Analog switch mode register 2, -RI_CMR2 EQU (_RI + 0x30) ; RI Channel mask register 2, -RI_CICR2 EQU (_RI + 0x34) ; RI Channel identification for capture register 2, -RI_ASMR3 EQU (_RI + 0x38) ; RI Analog switch mode register 3, -RI_CMR3 EQU (_RI + 0x3C) ; RI Channel mask register 3, -RI_CICR3 EQU (_RI + 0x40) ; RI Channel identification for capture register3 , -RI_ASMR4 EQU (_RI + 0x44) ; RI Analog switch mode register 4, -RI_CMR4 EQU (_RI + 0x48) ; RI Channel mask register 4, -RI_CICR4 EQU (_RI + 0x4C) ; RI Channel identification for capture register 4, -RI_ASMR5 EQU (_RI + 0x50) ; RI Analog switch mode register 5, -RI_CMR5 EQU (_RI + 0x54) ; RI Channel mask register 5, -RI_CICR5 EQU (_RI + 0x58) ; RI Channel identification for capture register 5, - - -; Op Amplifier module - -OPAMP_CSR EQU (_OPAMP + 0x00) ; OPAMP control/status register, -OPAMP_OTR EQU (_OPAMP + 0x04) ; OPAMP offset trimming register for normal mode, -OPAMP_LPOTR EQU (_OPAMP + 0x08) ; OPAMP offset trimming register for low power mode, - - -; Syscfg - -SYSCFG_MEMRMP EQU (_SYSCFG + 0x00) ; SYSCFG memory remap register, -SYSCFG_PMC EQU (_SYSCFG + 0x04) ; SYSCFG peripheral mode configuration register, -SYSCFG_EXTICR1 EQU (_SYSCFG + 0x08) ; SYSCFG external interrupt configuration registers, -SYSCFG_EXTICR2 EQU (_SYSCFG + 0x0C) ; SYSCFG external interrupt configuration registers, -SYSCFG_EXTICR3 EQU (_SYSCFG + 0x10) ; SYSCFG external interrupt configuration registers, -SYSCFG_EXTICR4 EQU (_SYSCFG + 0x14) ; SYSCFG external interrupt configuration registers, - - -; External interrupt control registers - -EXTI_IMR EQU (_EXTI + 0x00) ; EXTI interrupt mask register, -EXTI_EMR EQU (_EXTI + 0x04) ; EXTI event mask register, -EXTI_RTSR EQU (_EXTI + 0x08) ; EXTI rising edge trigger selection register, -EXTI_FTSR EQU (_EXTI + 0x0C) ; EXTI Falling edge trigger selection register, -EXTI_SWIER EQU (_EXTI + 0x10) ; EXTI software interrupt event register, -EXTI_PR EQU (_EXTI + 0x14) ; EXTI pending register, - - -; ADC common config - -ADC_CSR EQU (_ADCC + 0x000) ; ADC common status register, -ADC_CCR EQU (_ADCC + 0x004) ; ADC common control register, - -; ADC1 - -ADC_SR EQU (_ADC1 + 0x00) ; ADC status register, -ADC_CR1 EQU (_ADC1 + 0x04) ; ADC control register 1, -ADC_CR2 EQU (_ADC1 + 0x08) ; ADC control register 2, -ADC_SMPR1 EQU (_ADC1 + 0x0C) ; ADC sample time register 1, -ADC_SMPR2 EQU (_ADC1 + 0x10) ; ADC sample time register 2, -ADC_SMPR3 EQU (_ADC1 + 0x14) ; ADC sample time register 3, -ADC_JOFR1 EQU (_ADC1 + 0x18) ; ADC injected channel data offset register 1, -ADC_JOFR2 EQU (_ADC1 + 0x1C) ; ADC injected channel data offset register 2, -ADC_JOFR3 EQU (_ADC1 + 0x20) ; ADC injected channel data offset register 3, -ADC_JOFR4 EQU (_ADC1 + 0x24) ; ADC injected channel data offset register 4, -ADC_HTR EQU (_ADC1 + 0x28) ; ADC watchdog higher threshold register, -ADC_LTR EQU (_ADC1 + 0x2C) ; ADC watchdog lower threshold register, -ADC_SQR1 EQU (_ADC1 + 0x30) ; ADC regular sequence register 1, -ADC_SQR2 EQU (_ADC1 + 0x34) ; ADC regular sequence register 2, -ADC_SQR3 EQU (_ADC1 + 0x38) ; ADC regular sequence register 3, -ADC_SQR4 EQU (_ADC1 + 0x3C) ; ADC regular sequence register 4, -ADC_SQR5 EQU (_ADC1 + 0x40) ; ADC regular sequence register 5, -ADC_JSQR EQU (_ADC1 + 0x44) ; ADC injected sequence register, -ADC_JDR1 EQU (_ADC1 + 0x48) ; ADC injected data register 1, -ADC_JDR2 EQU (_ADC1 + 0x4C) ; ADC injected data register 2, -ADC_JDR3 EQU (_ADC1 + 0x50) ; ADC injected data register 3, -ADC_JDR4 EQU (_ADC1 + 0x54) ; ADC injected data register 4, -ADC_DR EQU (_ADC1 + 0x58) ; ADC regular data register, -ADC_SMPR0 EQU (_ADC1 + 0x5C) ; ADC sample time register 0, - - -; SD host - -SDIO_POWER EQU (_SDIO + 0x00) ; SDIO power control register, -SDIO_CLKCR EQU (_SDIO + 0x04) ; SDI clock control register, -SDIO_ARG EQU (_SDIO + 0x08) ; SDIO argument register, -SDIO_CMD EQU (_SDIO + 0x0C) ; SDIO command register, -SDIO_RESPCMD EQU (_SDIO + 0x10) ; SDIO command response register, -SDIO_RESP1 EQU (_SDIO + 0x14) ; SDIO response 1 register, -SDIO_RESP2 EQU (_SDIO + 0x18) ; SDIO response 2 register, -SDIO_RESP3 EQU (_SDIO + 0x1C) ; SDIO response 3 register, -SDIO_RESP4 EQU (_SDIO + 0x20) ; SDIO response 4 register, -SDIO_DTIMER EQU (_SDIO + 0x24) ; SDIO data timer register, -SDIO_DLEN EQU (_SDIO + 0x28) ; SDIO data length register, -SDIO_DCTRL EQU (_SDIO + 0x2C) ; SDIO data control register, -SDIO_DCOUNT EQU (_SDIO + 0x30) ; SDIO data counter register, -SDIO_STA EQU (_SDIO + 0x34) ; SDIO status register, -SDIO_ICR EQU (_SDIO + 0x38) ; SDIO interrupt clear register, -SDIO_MASK EQU (_SDIO + 0x3C) ; SDIO mask register, -SDIO_FIFOCNT EQU (_SDIO + 0x48) ; SDIO FIFO counter register, -SDIO_FIFO EQU (_SDIO + 0x80) ; SDIO data FIFO register, - - -; SPI - -SPI1_CR1 EQU (_SPI1 + 0x00) ; SPI1 control register 1 (not used in I2S mode), -SPI1_CR2 EQU (_SPI1 + 0x04) ; SPI1 control register 2, -SPI1_SR EQU (_SPI1 + 0x08) ; SPI1 status register, -SPI1_DR EQU (_SPI1 + 0x0C) ; SPI1 data register, -SPI1_CRCPR EQU (_SPI1 + 0x10) ; SPI1 CRC polynomial register (not used in I2S mode), -SPI1_RXCRCR EQU (_SPI1 + 0x14) ; SPI1 RX CRC register (not used in I2S mode), -SPI1_TXCRCR EQU (_SPI1 + 0x18) ; SPI1 TX CRC register (not used in I2S mode), -SPI1_I2SCFGR EQU (_SPI1 + 0x1C) ; SPI1_I2S configuration register, -SPI1_I2SPR EQU (_SPI1 + 0x20) ; SPI1_I2S prescaler register, - - -; DMA 1 - -; Status registers -DMA1_ISR EQU (_DMA1 + 0x00) ; DMA interrupt status register, -DMA1_IFCR EQU (_DMA1 + 0x04) ; DMA interrupt flag clear register, - -; Channel bases -_DMA1_CH1 EQU (_DMA1 + 0x0008) -_DMA1_CH2 EQU (_DMA1 + 0x001C) -_DMA1_CH3 EQU (_DMA1 + 0x0030) -_DMA1_CH4 EQU (_DMA1 + 0x0044) -_DMA1_CH5 EQU (_DMA1 + 0x0058) -_DMA1_CH6 EQU (_DMA1 + 0x006C) -_DMA1_CH7 EQU (_DMA1 + 0x0080) - -DMA1_CH1_CCR EQU (_DMA1_CH1 + 0x00) ; DMA channel x configuration register -DMA1_CH1_CNDTR EQU (_DMA1_CH1 + 0x04) ; DMA channel x number of data register -DMA1_CH1_CPAR EQU (_DMA1_CH1 + 0x08) ; DMA channel x peripheral address register -DMA1_CH1_CMAR EQU (_DMA1_CH1 + 0x0C) ; DMA channel x memory address register - -DMA1_CH2_CCR EQU (_DMA1_CH2 + 0x00) ; DMA channel x configuration register -DMA1_CH2_CNDTR EQU (_DMA1_CH2 + 0x04) ; DMA channel x number of data register -DMA1_CH2_CPAR EQU (_DMA1_CH2 + 0x08) ; DMA channel x peripheral address register -DMA1_CH2_CMAR EQU (_DMA1_CH2 + 0x0C) ; DMA channel x memory address register - -DMA1_CH3_CCR EQU (_DMA1_CH3 + 0x00) ; DMA channel x configuration register -DMA1_CH3_CNDTR EQU (_DMA1_CH3 + 0x04) ; DMA channel x number of data register -DMA1_CH3_CPAR EQU (_DMA1_CH3 + 0x08) ; DMA channel x peripheral address register -DMA1_CH3_CMAR EQU (_DMA1_CH3 + 0x0C) ; DMA channel x memory address register - -DMA1_CH4_CCR EQU (_DMA1_CH4 + 0x00) ; DMA channel x configuration register -DMA1_CH4_CNDTR EQU (_DMA1_CH4 + 0x04) ; DMA channel x number of data register -DMA1_CH4_CPAR EQU (_DMA1_CH4 + 0x08) ; DMA channel x peripheral address register -DMA1_CH4_CMAR EQU (_DMA1_CH4 + 0x0C) ; DMA channel x memory address register - -DMA1_CH5_CCR EQU (_DMA1_CH5 + 0x00) ; DMA channel x configuration register -DMA1_CH5_CNDTR EQU (_DMA1_CH5 + 0x04) ; DMA channel x number of data register -DMA1_CH5_CPAR EQU (_DMA1_CH5 + 0x08) ; DMA channel x peripheral address register -DMA1_CH5_CMAR EQU (_DMA1_CH5 + 0x0C) ; DMA channel x memory address register - -DMA1_CH6_CCR EQU (_DMA1_CH6 + 0x00) ; DMA channel x configuration register -DMA1_CH6_CNDTR EQU (_DMA1_CH6 + 0x04) ; DMA channel x number of data register -DMA1_CH6_CPAR EQU (_DMA1_CH6 + 0x08) ; DMA channel x peripheral address register -DMA1_CH6_CMAR EQU (_DMA1_CH6 + 0x0C) ; DMA channel x memory address register - -DMA1_CH7_CCR EQU (_DMA1_CH7 + 0x00) ; DMA channel x configuration register -DMA1_CH7_CNDTR EQU (_DMA1_CH7 + 0x04) ; DMA channel x number of data register -DMA1_CH7_CPAR EQU (_DMA1_CH7 + 0x08) ; DMA channel x peripheral address register -DMA1_CH7_CMAR EQU (_DMA1_CH7 + 0x0C) ; DMA channel x memory address register - - -; DMA 2 - -; Status registers -DMA2_ISR EQU (_DMA2 + 0x00) ; DMA interrupt status register, -DMA2_IFCR EQU (_DMA2 + 0x04) ; DMA interrupt flag clear register, - -; Channel bases -_DMA2_CH1 EQU (_DMA2 + 0x0008) -_DMA2_CH2 EQU (_DMA2 + 0x001C) -_DMA2_CH3 EQU (_DMA2 + 0x0030) -_DMA2_CH4 EQU (_DMA2 + 0x0044) -_DMA2_CH5 EQU (_DMA2 + 0x0058) - -DMA2_CH1_CCR EQU (_DMA2_CH1 + 0x00) ; DMA channel x configuration register -DMA2_CH1_CNDTR EQU (_DMA2_CH1 + 0x04) ; DMA channel x number of data register -DMA2_CH1_CPAR EQU (_DMA2_CH1 + 0x08) ; DMA channel x peripheral address register -DMA2_CH1_CMAR EQU (_DMA2_CH1 + 0x0C) ; DMA channel x memory address register - -DMA2_CH2_CCR EQU (_DMA2_CH2 + 0x00) ; DMA channel x configuration register -DMA2_CH2_CNDTR EQU (_DMA2_CH2 + 0x04) ; DMA channel x number of data register -DMA2_CH2_CPAR EQU (_DMA2_CH2 + 0x08) ; DMA channel x peripheral address register -DMA2_CH2_CMAR EQU (_DMA2_CH2 + 0x0C) ; DMA channel x memory address register - -DMA2_CH3_CCR EQU (_DMA2_CH3 + 0x00) ; DMA channel x configuration register -DMA2_CH3_CNDTR EQU (_DMA2_CH3 + 0x04) ; DMA channel x number of data register -DMA2_CH3_CPAR EQU (_DMA2_CH3 + 0x08) ; DMA channel x peripheral address register -DMA2_CH3_CMAR EQU (_DMA2_CH3 + 0x0C) ; DMA channel x memory address register - -DMA2_CH4_CCR EQU (_DMA2_CH4 + 0x00) ; DMA channel x configuration register -DMA2_CH4_CNDTR EQU (_DMA2_CH4 + 0x04) ; DMA channel x number of data register -DMA2_CH4_CPAR EQU (_DMA2_CH4 + 0x08) ; DMA channel x peripheral address register -DMA2_CH4_CMAR EQU (_DMA2_CH4 + 0x0C) ; DMA channel x memory address register - -DMA2_CH5_CCR EQU (_DMA2_CH5 + 0x00) ; DMA channel x configuration register -DMA2_CH5_CNDTR EQU (_DMA2_CH5 + 0x04) ; DMA channel x number of data register -DMA2_CH5_CPAR EQU (_DMA2_CH5 + 0x08) ; DMA channel x peripheral address register -DMA2_CH5_CMAR EQU (_DMA2_CH5 + 0x0C) ; DMA channel x memory address register - - -; RCC registers - -RCC_CR EQU (_RCC + 0x00) ; RCC clock control register, -RCC_ICSCR EQU (_RCC + 0x04) ; RCC Internal clock sources calibration register, -RCC_CFGR EQU (_RCC + 0x08) ; RCC Clock configuration register, -RCC_CIR EQU (_RCC + 0x0C) ; RCC Clock interrupt register, -RCC_AHBRSTR EQU (_RCC + 0x10) ; RCC AHB peripheral reset register, -RCC_APB2RSTR EQU (_RCC + 0x14) ; RCC APB2 peripheral reset register, -RCC_APB1RSTR EQU (_RCC + 0x18) ; RCC APB1 peripheral reset register, -RCC_AHBENR EQU (_RCC + 0x1C) ; RCC AHB peripheral clock enable register, -RCC_APB2ENR EQU (_RCC + 0x20) ; RCC APB2 peripheral clock enable register, -RCC_APB1ENR EQU (_RCC + 0x24) ; RCC APB1 peripheral clock enable register, -RCC_AHBLPENR EQU (_RCC + 0x28) ; RCC AHB peripheral clock enable in low power mode register, -RCC_APB2LPENR EQU (_RCC + 0x2C) ; RCC APB2 peripheral clock enable in low power mode register, -RCC_APB1LPENR EQU (_RCC + 0x30) ; RCC APB1 peripheral clock enable in low power mode register, -RCC_CSR EQU (_RCC + 0x34) ; RCC Control/status register, - - -; CRC module - -CRC_DR EQU (_CRC + 0x00) ; CRC Data register, -CRC_IDR EQU (_CRC + 0x04) ; CRC Independent data register, -CRC_CR EQU (_CRC + 0x08) ; CRC Control register, - - - - -; FLASH registers - -FLASH_ACR EQU (_FLASH + 0x00) ; Access control register, -FLASH_PECR EQU (_FLASH + 0x04) ; Program/erase control register, -FLASH_PDKEYR EQU (_FLASH + 0x08) ; Power down key register, -FLASH_PEKEYR EQU (_FLASH + 0x0c) ; Program/erase key register, -FLASH_PRGKEYR EQU (_FLASH + 0x10) ; Program memory key register, -FLASH_OPTKEYR EQU (_FLASH + 0x14) ; Option byte key register, -FLASH_SR EQU (_FLASH + 0x18) ; Status register, -FLASH_OBR EQU (_FLASH + 0x1c) ; Option byte register, -FLASH_WRPR EQU (_FLASH + 0x20) ; Write protection register, -FLASH_WRPR1 EQU (_FLASH + 0x28) ; Write protection register 1, -FLASH_WRPR2 EQU (_FLASH + 0x2C) ; Write protection register 2, - -; FLASH option bytes - -OB_RDP EQU (_OB + 0x00) ; Read protection register, -OB_USER EQU (_OB + 0x04) ; user register, -OB_WRP01 EQU (_OB + 0x08) ; write protection register 0 1, -OB_WRP23 EQU (_OB + 0x0C) ; write protection register 2 3, -OB_WRP45 EQU (_OB + 0x10) ; write protection register 4 5, -OB_WRP67 EQU (_OB + 0x14) ; write protection register 6 7, -OB_WRP89 EQU (_OB + 0x18) ; write protection register 8 9, -OB_WRP1011 EQU (_OB + 0x1C) ; write protection register 10 11, - - -; AES crypto module - -AES_CR EQU (_AES + 0x00) ; AES control register, -AES_SR EQU (_AES + 0x04) ; AES status register, -AES_DINR_REG EQU (_AES + 0x08) ; AES data input register, -AES_DOUTR_REG EQU (_AES + 0x0C) ; AES data output register, -AES_KEYR0_REG EQU (_AES + 0x10) ; AES key register 0, -AES_KEYR1_REG EQU (_AES + 0x14) ; AES key register 1, -AES_KEYR2_REG EQU (_AES + 0x18) ; AES key register 2, -AES_KEYR3_REG EQU (_AES + 0x1C) ; AES key register 3, -AES_IVR0_REG EQU (_AES + 0x20) ; AES initialization vector register 0, -AES_IVR1_REG EQU (_AES + 0x24) ; AES initialization vector register 1, -AES_IVR2_REG EQU (_AES + 0x28) ; AES initialization vector register 2, -AES_IVR3_REG EQU (_AES + 0x2C) ; AES initialization vector register 3, - - - -; FSMC -_FSMC_B1 EQU (_FSMC + 0x0000) ; FSMC Bank1 registers base address -_FSMC_B1E EQU (_FSMC + 0x0104) ; FSMC Bank1E registers base address - -; Bank 1 -FSMC_B1_BTCR EQU (_FSMC_B1 + 0x00) ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), - -; Bank 2 -FSMC_B1E_BWTR EQU (_FSMC_B1E + 0x104) ; NOR/PSRAM write timing registers, - - -; DBGMCU - -DBGMCU_IDCODE EQU (_DBGMCU + 0x00) ; MCU device ID code, -DBGMCU_CR EQU (_DBGMCU + 0x04) ; Debug MCU configuration register, -DBGMCU_APB1FZ EQU (_DBGMCU + 0x08) ; Debug MCU APB1 freeze register, -DBGMCU_APB2FZ EQU (_DBGMCU + 0x0C) ; Debug MCU APB2 freeze register, - - END diff --git a/lib/INI_BITS_RI.s b/lib/INI_RI.s similarity index 93% rename from lib/INI_BITS_RI.s rename to lib/INI_RI.s index de7482e..5c220b1 100644 --- a/lib/INI_BITS_RI.s +++ b/lib/INI_RI.s @@ -4,16 +4,51 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro RI (analogove propojky) ; +; Routing Interface (RI) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Routing Interface (RI) -; +;* +;* REGISTERS +;* ;**************************************************************************** +; RI + +RI_ICR EQU (_RI + 0x04) ; RI input capture register, +RI_ASCR1 EQU (_RI + 0x08) ; RI analog switches control register, +RI_ASCR2 EQU (_RI + 0x0C) ; RI analog switch control register 2, +RI_HYSCR1 EQU (_RI + 0x10) ; RI hysteresis control register 1, +RI_HYSCR2 EQU (_RI + 0x14) ; RI Hysteresis control register 2, +RI_HYSCR3 EQU (_RI + 0x18) ; RI Hysteresis control register 3, +RI_HYSCR4 EQU (_RI + 0x1C) ; RI Hysteresis control register 4, +RI_ASMR1 EQU (_RI + 0x20) ; RI Analog switch mode register 1, +RI_CMR1 EQU (_RI + 0x24) ; RI Channel mask register 1, +RI_CICR1 EQU (_RI + 0x28) ; RI Channel identification for capture register 1, +RI_ASMR2 EQU (_RI + 0x2C) ; RI Analog switch mode register 2, +RI_CMR2 EQU (_RI + 0x30) ; RI Channel mask register 2, +RI_CICR2 EQU (_RI + 0x34) ; RI Channel identification for capture register 2, +RI_ASMR3 EQU (_RI + 0x38) ; RI Analog switch mode register 3, +RI_CMR3 EQU (_RI + 0x3C) ; RI Channel mask register 3, +RI_CICR3 EQU (_RI + 0x40) ; RI Channel identification for capture register3 , +RI_ASMR4 EQU (_RI + 0x44) ; RI Analog switch mode register 4, +RI_CMR4 EQU (_RI + 0x48) ; RI Channel mask register 4, +RI_CICR4 EQU (_RI + 0x4C) ; RI Channel identification for capture register 4, +RI_ASMR5 EQU (_RI + 0x50) ; RI Analog switch mode register 5, +RI_CMR5 EQU (_RI + 0x54) ; RI Channel mask register 5, +RI_CICR5 EQU (_RI + 0x58) ; RI Channel identification for capture register 5, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;******************* Bit definition for RI_ICR register ******************* RI_ICR_IC1Z EQU 0x0000000F ; IC1Z[3:0] bits (Input Capture 1 select bits) RI_ICR_IC1Z_0 EQU 0x00000001 ; Bit 0 diff --git a/lib/INI_BITS_RTC.s b/lib/INI_RTC.s similarity index 84% rename from lib/INI_BITS_RTC.s rename to lib/INI_RTC.s index ee8359c..63b0b2c 100644 --- a/lib/INI_BITS_RTC.s +++ b/lib/INI_RTC.s @@ -4,16 +4,83 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro RTC (obvod realneho casu) ; +; Real-Time Clock (RTC) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** + ;**************************************************************************** -; -; Real-Time Clock (RTC) -; +;* +;* REGISTERS +;* +;**************************************************************************** + + +; RTC + +RTC_TR EQU (_RTC + 0x00) ; RTC time register, +RTC_DR EQU (_RTC + 0x04) ; RTC date register, +RTC_CR EQU (_RTC + 0x08) ; RTC control register, +RTC_ISR EQU (_RTC + 0x0C) ; RTC initialization and status register, +RTC_PRER EQU (_RTC + 0x10) ; RTC prescaler register, +RTC_WUTR EQU (_RTC + 0x14) ; RTC wakeup timer register, +RTC_CALIBR EQU (_RTC + 0x18) ; RTC calibration register, +RTC_ALRMAR EQU (_RTC + 0x1C) ; RTC alarm A register, +RTC_ALRMBR EQU (_RTC + 0x20) ; RTC alarm B register, +RTC_WPR EQU (_RTC + 0x24) ; RTC write protection register, +RTC_SSR EQU (_RTC + 0x28) ; RTC sub second register, +RTC_SHIFTR EQU (_RTC + 0x2C) ; RTC shift control register, +RTC_TSTR EQU (_RTC + 0x30) ; RTC time stamp time register, +RTC_TSDR EQU (_RTC + 0x34) ; RTC time stamp date register, +RTC_TSSSR EQU (_RTC + 0x38) ; RTC time-stamp sub second register, +RTC_CALR EQU (_RTC + 0x3C) ; RRTC calibration register, +RTC_TAFCR EQU (_RTC + 0x40) ; RTC tamper and alternate function configuration register, +RTC_ALRMASSR EQU (_RTC + 0x44) ; RTC alarm A sub second register, +RTC_ALRMBSSR EQU (_RTC + 0x48) ; RTC alarm B sub second register, +RTC_BKP0R_REG EQU (_RTC + 0x50) ; RTC backup register 0, +RTC_BKP1R_REG EQU (_RTC + 0x54) ; RTC backup register 1, +RTC_BKP2R_REG EQU (_RTC + 0x58) ; RTC backup register 2, +RTC_BKP3R_REG EQU (_RTC + 0x5C) ; RTC backup register 3, +RTC_BKP4R_REG EQU (_RTC + 0x60) ; RTC backup register 4, +RTC_BKP5R_REG EQU (_RTC + 0x64) ; RTC backup register 5, +RTC_BKP6R_REG EQU (_RTC + 0x68) ; RTC backup register 6, +RTC_BKP7R_REG EQU (_RTC + 0x6C) ; RTC backup register 7, +RTC_BKP8R_REG EQU (_RTC + 0x70) ; RTC backup register 8, +RTC_BKP9R_REG EQU (_RTC + 0x74) ; RTC backup register 9, +RTC_BKP10R_REG EQU (_RTC + 0x78) ; RTC backup register 10, +RTC_BKP11R_REG EQU (_RTC + 0x7C) ; RTC backup register 11, +RTC_BKP12R_REG EQU (_RTC + 0x80) ; RTC backup register 12, +RTC_BKP13R_REG EQU (_RTC + 0x84) ; RTC backup register 13, +RTC_BKP14R_REG EQU (_RTC + 0x88) ; RTC backup register 14, +RTC_BKP15R_REG EQU (_RTC + 0x8C) ; RTC backup register 15, +RTC_BKP16R_REG EQU (_RTC + 0x90) ; RTC backup register 16, +RTC_BKP17R_REG EQU (_RTC + 0x94) ; RTC backup register 17, +RTC_BKP18R_REG EQU (_RTC + 0x98) ; RTC backup register 18, +RTC_BKP19R_REG EQU (_RTC + 0x9C) ; RTC backup register 19, +RTC_BKP20R_REG EQU (_RTC + 0xA0) ; RTC backup register 20, +RTC_BKP21R_REG EQU (_RTC + 0xA4) ; RTC backup register 21, +RTC_BKP22R_REG EQU (_RTC + 0xA8) ; RTC backup register 22, +RTC_BKP23R_REG EQU (_RTC + 0xAC) ; RTC backup register 23, +RTC_BKP24R_REG EQU (_RTC + 0xB0) ; RTC backup register 24, +RTC_BKP25R_REG EQU (_RTC + 0xB4) ; RTC backup register 25, +RTC_BKP26R_REG EQU (_RTC + 0xB8) ; RTC backup register 26, +RTC_BKP27R_REG EQU (_RTC + 0xBC) ; RTC backup register 27, +RTC_BKP28R_REG EQU (_RTC + 0xC0) ; RTC backup register 28, +RTC_BKP29R_REG EQU (_RTC + 0xC4) ; RTC backup register 29, +RTC_BKP30R_REG EQU (_RTC + 0xC8) ; RTC backup register 30, +RTC_BKP31R_REG EQU (_RTC + 0xCC) ; RTC backup register 31, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;******************* Bits definition for RTC_TR register ****************** RTC_TR_PM EQU 0x00400000 RTC_TR_HT EQU 0x00300000 diff --git a/lib/INI_BITS_SDIO.s b/lib/INI_SDIO.s similarity index 89% rename from lib/INI_BITS_SDIO.s rename to lib/INI_SDIO.s index d86d04c..a39583e 100644 --- a/lib/INI_BITS_SDIO.s +++ b/lib/INI_SDIO.s @@ -4,16 +4,47 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro SDIO ; +; SD host Interface +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; SD host Interface -; +;* +;* REGISTERS +;* ;**************************************************************************** +; SD host + +SDIO_POWER EQU (_SDIO + 0x00) ; SDIO power control register, +SDIO_CLKCR EQU (_SDIO + 0x04) ; SDI clock control register, +SDIO_ARG EQU (_SDIO + 0x08) ; SDIO argument register, +SDIO_CMD EQU (_SDIO + 0x0C) ; SDIO command register, +SDIO_RESPCMD EQU (_SDIO + 0x10) ; SDIO command response register, +SDIO_RESP1 EQU (_SDIO + 0x14) ; SDIO response 1 register, +SDIO_RESP2 EQU (_SDIO + 0x18) ; SDIO response 2 register, +SDIO_RESP3 EQU (_SDIO + 0x1C) ; SDIO response 3 register, +SDIO_RESP4 EQU (_SDIO + 0x20) ; SDIO response 4 register, +SDIO_DTIMER EQU (_SDIO + 0x24) ; SDIO data timer register, +SDIO_DLEN EQU (_SDIO + 0x28) ; SDIO data length register, +SDIO_DCTRL EQU (_SDIO + 0x2C) ; SDIO data control register, +SDIO_DCOUNT EQU (_SDIO + 0x30) ; SDIO data counter register, +SDIO_STA EQU (_SDIO + 0x34) ; SDIO status register, +SDIO_ICR EQU (_SDIO + 0x38) ; SDIO interrupt clear register, +SDIO_MASK EQU (_SDIO + 0x3C) ; SDIO mask register, +SDIO_FIFOCNT EQU (_SDIO + 0x48) ; SDIO FIFO counter register, +SDIO_FIFO EQU (_SDIO + 0x80) ; SDIO data FIFO register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;***************** Bit definition for SDIO_POWER register ***************** SDIO_POWER_PWRCTRL EQU 0x03 ; PWRCTRL[1:0] bits (Power supply control bits) SDIO_POWER_PWRCTRL_0 EQU 0x01 ; Bit 0 diff --git a/lib/INI_BITS_SPI.s b/lib/INI_SPI.s similarity index 71% rename from lib/INI_BITS_SPI.s rename to lib/INI_SPI.s index 5a396d6..fa094be 100644 --- a/lib/INI_BITS_SPI.s +++ b/lib/INI_SPI.s @@ -4,16 +4,63 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro SPI ; +; Serial Peripheral Interface (SPI) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Serial Peripheral Interface (SPI) -; +;* +;* REGISTERS +;* ;**************************************************************************** +; SPI 1 + +SPI1_CR1 EQU (_SPI1 + 0x00) ; SPI1 control register 1 (not used in I2S mode), +SPI1_CR2 EQU (_SPI1 + 0x04) ; SPI1 control register 2, +SPI1_SR EQU (_SPI1 + 0x08) ; SPI1 status register, +SPI1_DR EQU (_SPI1 + 0x0C) ; SPI1 data register, +SPI1_CRCPR EQU (_SPI1 + 0x10) ; SPI1 CRC polynomial register (not used in I2S mode), +SPI1_RXCRCR EQU (_SPI1 + 0x14) ; SPI1 RX CRC register (not used in I2S mode), +SPI1_TXCRCR EQU (_SPI1 + 0x18) ; SPI1 TX CRC register (not used in I2S mode), +SPI1_I2SCFGR EQU (_SPI1 + 0x1C) ; SPI1_I2S configuration register, +SPI1_I2SPR EQU (_SPI1 + 0x20) ; SPI1_I2S prescaler register, + +; SPI 2 + +SPI2_CR1 EQU (_SPI2 + 0x00) ; SPI2 control register 1 (not used in I2S mode), +SPI2_CR2 EQU (_SPI2 + 0x04) ; SPI2 control register 2, +SPI2_SR EQU (_SPI2 + 0x08) ; SPI2 status register, +SPI2_DR EQU (_SPI2 + 0x0C) ; SPI2 data register, +SPI2_CRCPR EQU (_SPI2 + 0x10) ; SPI2 CRC polynomial register (not used in I2S mode), +SPI2_RXCRCR EQU (_SPI2 + 0x14) ; SPI2 RX CRC register (not used in I2S mode), +SPI2_TXCRCR EQU (_SPI2 + 0x18) ; SPI2 TX CRC register (not used in I2S mode), +SPI2_I2SCFGR EQU (_SPI2 + 0x1C) ; SPI2_I2S configuration register, +SPI2_I2SPR EQU (_SPI2 + 0x20) ; SPI2_I2S prescaler register, + +; SPI 3 + +SPI3_CR1 EQU (_SPI3 + 0x00) ; SPI3 control register 1 (not used in I2S mode), +SPI3_CR2 EQU (_SPI3 + 0x04) ; SPI3 control register 2, +SPI3_SR EQU (_SPI3 + 0x08) ; SPI3 status register, +SPI3_DR EQU (_SPI3 + 0x0C) ; SPI3 data register, +SPI3_CRCPR EQU (_SPI3 + 0x10) ; SPI3 CRC polynomial register (not used in I2S mode), +SPI3_RXCRCR EQU (_SPI3 + 0x14) ; SPI3 RX CRC register (not used in I2S mode), +SPI3_TXCRCR EQU (_SPI3 + 0x18) ; SPI3 TX CRC register (not used in I2S mode), +SPI3_I2SCFGR EQU (_SPI3 + 0x1C) ; SPI3_I2S configuration register, +SPI3_I2SPR EQU (_SPI3 + 0x20) ; SPI3_I2S prescaler register, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for SPI_CR1 register ******************* SPI_CR1_CPHA EQU 0x0001 ; Clock Phase SPI_CR1_CPOL EQU 0x0002 ; Clock Polarity diff --git a/lib/INI_BITS_SYSCFG.s b/lib/INI_SYSCFG.s similarity index 91% rename from lib/INI_BITS_SYSCFG.s rename to lib/INI_SYSCFG.s index 458ee99..9f80782 100644 --- a/lib/INI_BITS_SYSCFG.s +++ b/lib/INI_SYSCFG.s @@ -4,16 +4,35 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro SYSCFG (EXTI routing atd.) ; +; System Configuration (SYSCFG) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; System Configuration (SYSCFG) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; Syscfg + +SYSCFG_MEMRMP EQU (_SYSCFG + 0x00) ; SYSCFG memory remap register, +SYSCFG_PMC EQU (_SYSCFG + 0x04) ; SYSCFG peripheral mode configuration register, +SYSCFG_EXTICR1 EQU (_SYSCFG + 0x08) ; SYSCFG external interrupt configuration registers, +SYSCFG_EXTICR2 EQU (_SYSCFG + 0x0C) ; SYSCFG external interrupt configuration registers, +SYSCFG_EXTICR3 EQU (_SYSCFG + 0x10) ; SYSCFG external interrupt configuration registers, +SYSCFG_EXTICR4 EQU (_SYSCFG + 0x14) ; SYSCFG external interrupt configuration registers, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;**************** Bit definition for SYSCFG_MEMRMP register *************** SYSCFG_MEMRMP_MEM_MODE EQU 0x00000003 ; SYSCFG_Memory Remap Config SYSCFG_MEMRMP_MEM_MODE_0 EQU 0x00000001 ; Bit 0 diff --git a/lib/INI_BITS_TIM.s b/lib/INI_TIM.s similarity index 58% rename from lib/INI_BITS_TIM.s rename to lib/INI_TIM.s index 11d65ef..3e3777b 100644 --- a/lib/INI_BITS_TIM.s +++ b/lib/INI_TIM.s @@ -4,16 +4,226 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro TIM (casovace) ; +; Timers (TIM) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Timers (TIM) -; +;* +;* REGISTERS +;* ;**************************************************************************** + +; Timer 2 + +TIM2_CR1 EQU (_TIM2 + 0x00) ; TIM control register 1, +TIM2_CR2 EQU (_TIM2 + 0x04) ; TIM control register 2, +TIM2_SMCR EQU (_TIM2 + 0x08) ; TIM slave mode control register, +TIM2_DIER EQU (_TIM2 + 0x0C) ; TIM DMA/interrupt enable register, +TIM2_SR EQU (_TIM2 + 0x10) ; TIM status register, +TIM2_EGR EQU (_TIM2 + 0x14) ; TIM event generation register, +TIM2_CCMR1 EQU (_TIM2 + 0x18) ; TIM capture/compare mode register 1, +TIM2_CCMR2 EQU (_TIM2 + 0x1C) ; TIM capture/compare mode register 2, +TIM2_CCER EQU (_TIM2 + 0x20) ; TIM capture/compare enable register, +TIM2_CNT EQU (_TIM2 + 0x24) ; TIM counter register, +TIM2_PSC EQU (_TIM2 + 0x28) ; TIM prescaler, +TIM2_ARR EQU (_TIM2 + 0x2C) ; TIM auto-reload register, +TIM2_CCR1 EQU (_TIM2 + 0x34) ; TIM capture/compare register 1, +TIM2_CCR2 EQU (_TIM2 + 0x38) ; TIM capture/compare register 2, +TIM2_CCR3 EQU (_TIM2 + 0x3C) ; TIM capture/compare register 3, +TIM2_CCR4 EQU (_TIM2 + 0x40) ; TIM capture/compare register 4, +TIM2_DCR EQU (_TIM2 + 0x48) ; TIM DMA control register, +TIM2_DMAR EQU (_TIM2 + 0x4C) ; TIM DMA address for full transfer, +TIM2_OR EQU (_TIM2 + 0x50) ; TIM option register, + +; Timer 3 + +TIM3_CR1 EQU (_TIM3 + 0x00) ; TIM control register 1, +TIM3_CR2 EQU (_TIM3 + 0x04) ; TIM control register 2, +TIM3_SMCR EQU (_TIM3 + 0x08) ; TIM slave mode control register, +TIM3_DIER EQU (_TIM3 + 0x0C) ; TIM DMA/interrupt enable register, +TIM3_SR EQU (_TIM3 + 0x10) ; TIM status register, +TIM3_EGR EQU (_TIM3 + 0x14) ; TIM event generation register, +TIM3_CCMR1 EQU (_TIM3 + 0x18) ; TIM capture/compare mode register 1, +TIM3_CCMR2 EQU (_TIM3 + 0x1C) ; TIM capture/compare mode register 2, +TIM3_CCER EQU (_TIM3 + 0x20) ; TIM capture/compare enable register, +TIM3_CNT EQU (_TIM3 + 0x24) ; TIM counter register, +TIM3_PSC EQU (_TIM3 + 0x28) ; TIM prescaler, +TIM3_ARR EQU (_TIM3 + 0x2C) ; TIM auto-reload register, +TIM3_CCR1 EQU (_TIM3 + 0x34) ; TIM capture/compare register 1, +TIM3_CCR2 EQU (_TIM3 + 0x38) ; TIM capture/compare register 2, +TIM3_CCR3 EQU (_TIM3 + 0x3C) ; TIM capture/compare register 3, +TIM3_CCR4 EQU (_TIM3 + 0x40) ; TIM capture/compare register 4, +TIM3_DCR EQU (_TIM3 + 0x48) ; TIM DMA control register, +TIM3_DMAR EQU (_TIM3 + 0x4C) ; TIM DMA address for full transfer, +TIM3_OR EQU (_TIM3 + 0x50) ; TIM option register, + +; Timer 4 + +TIM4_CR1 EQU (_TIM4 + 0x00) ; TIM control register 1, +TIM4_CR2 EQU (_TIM4 + 0x04) ; TIM control register 2, +TIM4_SMCR EQU (_TIM4 + 0x08) ; TIM slave mode control register, +TIM4_DIER EQU (_TIM4 + 0x0C) ; TIM DMA/interrupt enable register, +TIM4_SR EQU (_TIM4 + 0x10) ; TIM status register, +TIM4_EGR EQU (_TIM4 + 0x14) ; TIM event generation register, +TIM4_CCMR1 EQU (_TIM4 + 0x18) ; TIM capture/compare mode register 1, +TIM4_CCMR2 EQU (_TIM4 + 0x1C) ; TIM capture/compare mode register 2, +TIM4_CCER EQU (_TIM4 + 0x20) ; TIM capture/compare enable register, +TIM4_CNT EQU (_TIM4 + 0x24) ; TIM counter register, +TIM4_PSC EQU (_TIM4 + 0x28) ; TIM prescaler, +TIM4_ARR EQU (_TIM4 + 0x2C) ; TIM auto-reload register, +TIM4_CCR1 EQU (_TIM4 + 0x34) ; TIM capture/compare register 1, +TIM4_CCR2 EQU (_TIM4 + 0x38) ; TIM capture/compare register 2, +TIM4_CCR3 EQU (_TIM4 + 0x3C) ; TIM capture/compare register 3, +TIM4_CCR4 EQU (_TIM4 + 0x40) ; TIM capture/compare register 4, +TIM4_DCR EQU (_TIM4 + 0x48) ; TIM DMA control register, +TIM4_DMAR EQU (_TIM4 + 0x4C) ; TIM DMA address for full transfer, +TIM4_OR EQU (_TIM4 + 0x50) ; TIM option register, + +; Timer 5 + +TIM5_CR1 EQU (_TIM5 + 0x00) ; TIM control register 1, +TIM5_CR2 EQU (_TIM5 + 0x04) ; TIM control register 2, +TIM5_SMCR EQU (_TIM5 + 0x08) ; TIM slave mode control register, +TIM5_DIER EQU (_TIM5 + 0x0C) ; TIM DMA/interrupt enable register, +TIM5_SR EQU (_TIM5 + 0x10) ; TIM status register, +TIM5_EGR EQU (_TIM5 + 0x14) ; TIM event generation register, +TIM5_CCMR1 EQU (_TIM5 + 0x18) ; TIM capture/compare mode register 1, +TIM5_CCMR2 EQU (_TIM5 + 0x1C) ; TIM capture/compare mode register 2, +TIM5_CCER EQU (_TIM5 + 0x20) ; TIM capture/compare enable register, +TIM5_CNT EQU (_TIM5 + 0x24) ; TIM counter register, +TIM5_PSC EQU (_TIM5 + 0x28) ; TIM prescaler, +TIM5_ARR EQU (_TIM5 + 0x2C) ; TIM auto-reload register, +TIM5_CCR1 EQU (_TIM5 + 0x34) ; TIM capture/compare register 1, +TIM5_CCR2 EQU (_TIM5 + 0x38) ; TIM capture/compare register 2, +TIM5_CCR3 EQU (_TIM5 + 0x3C) ; TIM capture/compare register 3, +TIM5_CCR4 EQU (_TIM5 + 0x40) ; TIM capture/compare register 4, +TIM5_DCR EQU (_TIM5 + 0x48) ; TIM DMA control register, +TIM5_DMAR EQU (_TIM5 + 0x4C) ; TIM DMA address for full transfer, +TIM5_OR EQU (_TIM5 + 0x50) ; TIM option register, + +; Timer 6 + +TIM6_CR1 EQU (_TIM6 + 0x00) ; TIM control register 1, +TIM6_CR2 EQU (_TIM6 + 0x04) ; TIM control register 2, +TIM6_SMCR EQU (_TIM6 + 0x08) ; TIM slave mode control register, +TIM6_DIER EQU (_TIM6 + 0x0C) ; TIM DMA/interrupt enable register, +TIM6_SR EQU (_TIM6 + 0x10) ; TIM status register, +TIM6_EGR EQU (_TIM6 + 0x14) ; TIM event generation register, +TIM6_CCMR1 EQU (_TIM6 + 0x18) ; TIM capture/compare mode register 1, +TIM6_CCMR2 EQU (_TIM6 + 0x1C) ; TIM capture/compare mode register 2, +TIM6_CCER EQU (_TIM6 + 0x20) ; TIM capture/compare enable register, +TIM6_CNT EQU (_TIM6 + 0x24) ; TIM counter register, +TIM6_PSC EQU (_TIM6 + 0x28) ; TIM prescaler, +TIM6_ARR EQU (_TIM6 + 0x2C) ; TIM auto-reload register, +TIM6_CCR1 EQU (_TIM6 + 0x34) ; TIM capture/compare register 1, +TIM6_CCR2 EQU (_TIM6 + 0x38) ; TIM capture/compare register 2, +TIM6_CCR3 EQU (_TIM6 + 0x3C) ; TIM capture/compare register 3, +TIM6_CCR4 EQU (_TIM6 + 0x40) ; TIM capture/compare register 4, +TIM6_DCR EQU (_TIM6 + 0x48) ; TIM DMA control register, +TIM6_DMAR EQU (_TIM6 + 0x4C) ; TIM DMA address for full transfer, +TIM6_OR EQU (_TIM6 + 0x50) ; TIM option register, + +; Timer 7 + +TIM7_CR1 EQU (_TIM7 + 0x00) ; TIM control register 1, +TIM7_CR2 EQU (_TIM7 + 0x04) ; TIM control register 2, +TIM7_SMCR EQU (_TIM7 + 0x08) ; TIM slave mode control register, +TIM7_DIER EQU (_TIM7 + 0x0C) ; TIM DMA/interrupt enable register, +TIM7_SR EQU (_TIM7 + 0x10) ; TIM status register, +TIM7_EGR EQU (_TIM7 + 0x14) ; TIM event generation register, +TIM7_CCMR1 EQU (_TIM7 + 0x18) ; TIM capture/compare mode register 1, +TIM7_CCMR2 EQU (_TIM7 + 0x1C) ; TIM capture/compare mode register 2, +TIM7_CCER EQU (_TIM7 + 0x20) ; TIM capture/compare enable register, +TIM7_CNT EQU (_TIM7 + 0x24) ; TIM counter register, +TIM7_PSC EQU (_TIM7 + 0x28) ; TIM prescaler, +TIM7_ARR EQU (_TIM7 + 0x2C) ; TIM auto-reload register, +TIM7_CCR1 EQU (_TIM7 + 0x34) ; TIM capture/compare register 1, +TIM7_CCR2 EQU (_TIM7 + 0x38) ; TIM capture/compare register 2, +TIM7_CCR3 EQU (_TIM7 + 0x3C) ; TIM capture/compare register 3, +TIM7_CCR4 EQU (_TIM7 + 0x40) ; TIM capture/compare register 4, +TIM7_DCR EQU (_TIM7 + 0x48) ; TIM DMA control register, +TIM7_DMAR EQU (_TIM7 + 0x4C) ; TIM DMA address for full transfer, +TIM7_OR EQU (_TIM7 + 0x50) ; TIM option register, + +; Timer 9 + +TIM9_CR1 EQU (_TIM9 + 0x00) ; TIM control register 1, +TIM9_CR2 EQU (_TIM9 + 0x04) ; TIM control register 2, +TIM9_SMCR EQU (_TIM9 + 0x08) ; TIM slave mode control register, +TIM9_DIER EQU (_TIM9 + 0x0C) ; TIM DMA/interrupt enable register, +TIM9_SR EQU (_TIM9 + 0x10) ; TIM status register, +TIM9_EGR EQU (_TIM9 + 0x14) ; TIM event generation register, +TIM9_CCMR1 EQU (_TIM9 + 0x18) ; TIM capture/compare mode register 1, +TIM9_CCMR2 EQU (_TIM9 + 0x1C) ; TIM capture/compare mode register 2, +TIM9_CCER EQU (_TIM9 + 0x20) ; TIM capture/compare enable register, +TIM9_CNT EQU (_TIM9 + 0x24) ; TIM counter register, +TIM9_PSC EQU (_TIM9 + 0x28) ; TIM prescaler, +TIM9_ARR EQU (_TIM9 + 0x2C) ; TIM auto-reload register, +TIM9_CCR1 EQU (_TIM9 + 0x34) ; TIM capture/compare register 1, +TIM9_CCR2 EQU (_TIM9 + 0x38) ; TIM capture/compare register 2, +TIM9_CCR3 EQU (_TIM9 + 0x3C) ; TIM capture/compare register 3, +TIM9_CCR4 EQU (_TIM9 + 0x40) ; TIM capture/compare register 4, +TIM9_DCR EQU (_TIM9 + 0x48) ; TIM DMA control register, +TIM9_DMAR EQU (_TIM9 + 0x4C) ; TIM DMA address for full transfer, +TIM9_OR EQU (_TIM9 + 0x50) ; TIM option register, + +; Timer 10 + +TIM10_CR1 EQU (_TIM10 + 0x00) ; TIM control register 1, +TIM10_CR2 EQU (_TIM10 + 0x04) ; TIM control register 2, +TIM10_SMCR EQU (_TIM10 + 0x08) ; TIM slave mode control register, +TIM10_DIER EQU (_TIM10 + 0x0C) ; TIM DMA/interrupt enable register, +TIM10_SR EQU (_TIM10 + 0x10) ; TIM status register, +TIM10_EGR EQU (_TIM10 + 0x14) ; TIM event generation register, +TIM10_CCMR1 EQU (_TIM10 + 0x18) ; TIM capture/compare mode register 1, +TIM10_CCMR2 EQU (_TIM10 + 0x1C) ; TIM capture/compare mode register 2, +TIM10_CCER EQU (_TIM10 + 0x20) ; TIM capture/compare enable register, +TIM10_CNT EQU (_TIM10 + 0x24) ; TIM counter register, +TIM10_PSC EQU (_TIM10 + 0x28) ; TIM prescaler, +TIM10_ARR EQU (_TIM10 + 0x2C) ; TIM auto-reload register, +TIM10_CCR1 EQU (_TIM10 + 0x34) ; TIM capture/compare register 1, +TIM10_CCR2 EQU (_TIM10 + 0x38) ; TIM capture/compare register 2, +TIM10_CCR3 EQU (_TIM10 + 0x3C) ; TIM capture/compare register 3, +TIM10_CCR4 EQU (_TIM10 + 0x40) ; TIM capture/compare register 4, +TIM10_DCR EQU (_TIM10 + 0x48) ; TIM DMA control register, +TIM10_DMAR EQU (_TIM10 + 0x4C) ; TIM DMA address for full transfer, +TIM10_OR EQU (_TIM10 + 0x50) ; TIM option register, + +; Timer 11 + +TIM11_CR1 EQU (_TIM11 + 0x00) ; TIM control register 1, +TIM11_CR2 EQU (_TIM11 + 0x04) ; TIM control register 2, +TIM11_SMCR EQU (_TIM11 + 0x08) ; TIM slave mode control register, +TIM11_DIER EQU (_TIM11 + 0x0C) ; TIM DMA/interrupt enable register, +TIM11_SR EQU (_TIM11 + 0x10) ; TIM status register, +TIM11_EGR EQU (_TIM11 + 0x14) ; TIM event generation register, +TIM11_CCMR1 EQU (_TIM11 + 0x18) ; TIM capture/compare mode register 1, +TIM11_CCMR2 EQU (_TIM11 + 0x1C) ; TIM capture/compare mode register 2, +TIM11_CCER EQU (_TIM11 + 0x20) ; TIM capture/compare enable register, +TIM11_CNT EQU (_TIM11 + 0x24) ; TIM counter register, +TIM11_PSC EQU (_TIM11 + 0x28) ; TIM prescaler, +TIM11_ARR EQU (_TIM11 + 0x2C) ; TIM auto-reload register, +TIM11_CCR1 EQU (_TIM11 + 0x34) ; TIM capture/compare register 1, +TIM11_CCR2 EQU (_TIM11 + 0x38) ; TIM capture/compare register 2, +TIM11_CCR3 EQU (_TIM11 + 0x3C) ; TIM capture/compare register 3, +TIM11_CCR4 EQU (_TIM11 + 0x40) ; TIM capture/compare register 4, +TIM11_DCR EQU (_TIM11 + 0x48) ; TIM DMA control register, +TIM11_DMAR EQU (_TIM11 + 0x4C) ; TIM DMA address for full transfer, +TIM11_OR EQU (_TIM11 + 0x50) ; TIM option register, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for TIM_CR1 register ******************* TIM_CR1_CEN EQU 0x0001 ; Counter enable TIM_CR1_UDIS EQU 0x0002 ; Update disable diff --git a/lib/INI_BITS_USART.s b/lib/INI_USART.s similarity index 68% rename from lib/INI_BITS_USART.s rename to lib/INI_USART.s index 6b6c98c..05c52a8 100644 --- a/lib/INI_BITS_USART.s +++ b/lib/INI_USART.s @@ -4,16 +4,77 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro USART ; +; Universal Synchronous Asynchronous Receiver Transmitter (USART) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Universal Synchronous Asynchronous Receiver Transmitter (USART) -; +;* +;* REGISTERS +;* ;**************************************************************************** +; USART 1 + +USART1_SR EQU (_USART1 + 0x00) ; USART1 Status register, +USART1_DR EQU (_USART1 + 0x04) ; USART1 Data register, +USART1_BRR EQU (_USART1 + 0x08) ; USART1 Baud rate register, +USART1_CR1 EQU (_USART1 + 0x0C) ; USART1 Control register 1, +USART1_CR2 EQU (_USART1 + 0x10) ; USART1 Control register 2, +USART1_CR3 EQU (_USART1 + 0x14) ; USART1 Control register 3, +USART1_GTPR EQU (_USART1 + 0x18) ; USART1 Guard time and prescaler register, + +; USART 2 + +USART2_SR EQU (_USART2 + 0x00) ; USART2 Status register, +USART2_DR EQU (_USART2 + 0x04) ; USART2 Data register, +USART2_BRR EQU (_USART2 + 0x08) ; USART2 Baud rate register, +USART2_CR1 EQU (_USART2 + 0x0C) ; USART2 Control register 1, +USART2_CR2 EQU (_USART2 + 0x10) ; USART2 Control register 2, +USART2_CR3 EQU (_USART2 + 0x14) ; USART2 Control register 3, +USART2_GTPR EQU (_USART2 + 0x18) ; USART2 Guard time and prescaler register, + +; USART 3 + +USART3_SR EQU (_USART3 + 0x00) ; USART3 Status register, +USART3_DR EQU (_USART3 + 0x04) ; USART3 Data register, +USART3_BRR EQU (_USART3 + 0x08) ; USART3 Baud rate register, +USART3_CR1 EQU (_USART3 + 0x0C) ; USART3 Control register 1, +USART3_CR2 EQU (_USART3 + 0x10) ; USART3 Control register 2, +USART3_CR3 EQU (_USART3 + 0x14) ; USART3 Control register 3, +USART3_GTPR EQU (_USART3 + 0x18) ; USART3 Guard time and prescaler register, + +; USART 4 + +UART4_SR EQU (_UART4 + 0x00) ; UART4 Status register, +UART4_DR EQU (_UART4 + 0x04) ; UART4 Data register, +UART4_BRR EQU (_UART4 + 0x08) ; UART4 Baud rate register, +UART4_CR1 EQU (_UART4 + 0x0C) ; UART4 Control register 1, +UART4_CR2 EQU (_UART4 + 0x10) ; UART4 Control register 2, +UART4_CR3 EQU (_UART4 + 0x14) ; UART4 Control register 3, +UART4_GTPR EQU (_UART4 + 0x18) ; UART4 Guard time and prescaler register, + +; USART 5 + +UART5_SR EQU (_UART5 + 0x00) ; UART5 Status register, +UART5_DR EQU (_UART5 + 0x04) ; UART5 Data register, +UART5_BRR EQU (_UART5 + 0x08) ; UART5 Baud rate register, +UART5_CR1 EQU (_UART5 + 0x0C) ; UART5 Control register 1, +UART5_CR2 EQU (_UART5 + 0x10) ; UART5 Control register 2, +UART5_CR3 EQU (_UART5 + 0x14) ; UART5 Control register 3, +UART5_GTPR EQU (_UART5 + 0x18) ; UART5 Guard time and prescaler register, + + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ;****************** Bit definition for USART_SR register ****************** USART_SR_PE EQU 0x0001 ; Parity Error USART_SR_FE EQU 0x0002 ; Framing Error diff --git a/lib/INI_BITS_USB.s b/lib/INI_USB.s similarity index 99% rename from lib/INI_BITS_USB.s rename to lib/INI_USB.s index b2bc8f0..935f61f 100644 --- a/lib/INI_BITS_USB.s +++ b/lib/INI_USB.s @@ -4,16 +4,28 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro USB ; +; Universal Serial Bus (USB) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Universal Serial Bus (USB) -; +;* +;* REGISTERS +;* ;**************************************************************************** +; TODO where are the registers?? + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* +;**************************************************************************** + + ; Endpoint-specific registers ;****************** Bit definition for USB_EP0R register ****************** USB_EP0R_EA EQU 0x000F ; Endpoint Address diff --git a/lib/INI_BITS_WWDG.s b/lib/INI_WDG.s similarity index 58% rename from lib/INI_BITS_WWDG.s rename to lib/INI_WDG.s index 401eef9..5765aa3 100644 --- a/lib/INI_BITS_WWDG.s +++ b/lib/INI_WDG.s @@ -4,16 +4,42 @@ ; DATUM : 10/2015 ; POPIS : Bitove masky ridicich registru pro WWDG ; +; Window WATCHDOG (WWDG) +; +; Independent WATCHDOG (IWDG) +; ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT. ;******************************************************************************** ;**************************************************************************** -; -; Window WATCHDOG (WWDG) -; +;* +;* REGISTERS +;* +;**************************************************************************** + +; Window Watchdog + +WWDG_CR EQU (_WWDG + 0x00) ; WWDG Control register, +WWDG_CFR EQU (_WWDG + 0x04) ; WWDG Configuration register, +WWDG_SR EQU (_WWDG + 0x08) ; WWDG Status register, + + +; Independent Watchdog + +IWDG_KR EQU (_IWDG + 0x00) ; Key register, +IWDG_PR EQU (_IWDG + 0x04) ; Prescaler register, +IWDG_RLR EQU (_IWDG + 0x08) ; Reload register, +IWDG_SR EQU (_IWDG + 0x0C) ; Status register, + + +;**************************************************************************** +;* +;* BIT MASKS AND DEFINITIONS +;* ;**************************************************************************** + ;****************** Bit definition for WWDG_CR register ******************* WWDG_CR_T EQU 0x7F ; T[6:0] bits (7-Bit counter (MSB to LSB)) WWDG_CR_T0 EQU 0x01 ; Bit 0 @@ -42,7 +68,27 @@ WWDG_CFR_WDGTB1 EQU 0x0100 ; Bit 1 WWDG_CFR_EWI EQU 0x0200 ; Early Wakeup Interrupt + ;****************** Bit definition for WWDG_SR register ******************* WWDG_SR_EWIF EQU 0x01 ; Early Wakeup Interrupt Flag + + +;****************** Bit definition for IWDG_KR register ******************* +IWDG_KR_KEY EQU 0xFFFF ; Key value (write only, read 0000h) + +;****************** Bit definition for IWDG_PR register ******************* +IWDG_PR_PR EQU 0x07 ; PR[2:0] (Prescaler divider) +IWDG_PR_PR_0 EQU 0x01 ; Bit 0 +IWDG_PR_PR_1 EQU 0x02 ; Bit 1 +IWDG_PR_PR_2 EQU 0x04 ; Bit 2 + +;****************** Bit definition for IWDG_RLR register ****************** +IWDG_RLR_RL EQU 0x0FFF ; Watchdog counter reload value + +;****************** Bit definition for IWDG_SR register ******************* +IWDG_SR_PVU EQU 0x01 ; Watchdog prescaler value update +IWDG_SR_RVU EQU 0x02 ; Watchdog counter reload value update + + END diff --git a/lib/TODO.txt b/lib/TODO.txt new file mode 100644 index 0000000..9af332a --- /dev/null +++ b/lib/TODO.txt @@ -0,0 +1,8 @@ + +Missing registers in FSMC + +Missing registers in USB + +maybe others I didn't notice. + +-mightypork diff --git a/main.asm b/main.asm index 30ec9cf..10fc9a5 100644 --- a/main.asm +++ b/main.asm @@ -14,15 +14,14 @@ ;* Include library files ;*************************************************************************************************** - ; Register addresses + ; Base library file GET lib/INI_BASE.s - GET lib/INI_REGS.s ;deprecated TODO remove when definitions moved to other files - ; Bit presets + ; Peripheral modules GET lib/INI_GPIO.s GET lib/INI_SYSTICK.s - GET lib/INI_BITS_RCC.s ;legacy FIXME - GET lib/INI_BITS_FLASH.s ;legacy FIXME + GET lib/INI_RCC.s + GET lib/INI_FLASH.s ;***************************************************************************************************