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Ondřej Hruška 5 years ago
commit
fe17c2029f
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      README.md
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      registers/README.md
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      registers/gen/README.txt
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      registers/gen/to_asm_f031x.py
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      registers/gen/to_asm_f042x.py
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      registers/gen/to_asm_f100xx.py
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      registers/gen/to_asm_f303x.py
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      registers/gen/to_asm_f303xE.py
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      registers/gen/to_asm_f30x.py
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      registers/gen/to_asm_l100.py
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      registers/gen/to_json.py
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      registers/sfr_f042x.asm
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      registers/sfr_f100xx.asm
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      registers/sfr_f303x.asm
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      registers/sfr_f303xE.asm
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      registers/sfr_f30x.asm
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      registers/sfr_systick.asm
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      startup_scripts/README.md
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+ 14 - 0
README.md View File

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1
+STM32 assembler examples
2
+========================
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+
4
+This project provides examples for programming the STM32 microcontrollers in ARM assembler.
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+
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+Please visit the project folders for additional information (they contain separate READMEs).
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+
8
+License
9
+-------
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+
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+Unless otherwise specified (as is the case with the startup scripts), all files in this repository
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+are subject to the MIT license.
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+
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+For details, refer to the LICENSE file.

+ 49 - 0
registers/README.md View File

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1
+Register definitions
2
+====================
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+
4
+Those files provide definitions of register addresses and bit field mapping.
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+
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+Include the appropriate file using the `   GET 'filename.asm'` directive in your
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+main file.
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+
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+Example
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+-------
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+
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+```asm
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+; GPIOA base address:
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+GPIOA_BASE                     EQU 0x48000000
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+
16
+; GPIOA registers:
17
+
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+GPIOA_MODER                    EQU (GPIOA_BASE + 0x0) ; GPIO port mode register
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+GPIOA_OTYPER                   EQU (GPIOA_BASE + 0x4) ; GPIO port output type register
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+; ...
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+
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+; GPIO_MODER fields:
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+
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+GPIO_MODER_MODER15             EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
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+GPIO_MODER_MODER15_ofs         EQU 30
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+GPIO_MODER_MODER15_len         EQU 2
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+GPIO_MODER_MODER14             EQU 0x30000000 ; Port x configuration bits (y = 0..15)
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+GPIO_MODER_MODER14_ofs         EQU 28
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+GPIO_MODER_MODER14_len         EQU 2
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+; ...
31
+```
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+
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+Registers for a peripheral are named `<peripheral>_<register>`.
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+
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+Bit fields are named `<peripheral>_<register>_<field>`, and the field length and offset 
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+are available in the `_len` and `_ofs` constants.
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+
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+Notice how the peripheral is called `GPIOA`, but firlds are named `GPIO_...`. That is because
39
+all GPIOs have the same register structure, so they also share the same field definitions.
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+
41
+Generating
42
+----------
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+
44
+The definition files are in a large part generated from the CMSIS SVD files, with just a few manual modifications.
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+
46
+See the `gen/` folder for more info on how this conversion works.
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+
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+The register or bit field naming may differ from the datasheet, which is ST's fault. Feel free to correct those mistakes and **submit a pull request**.
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+

+ 13 - 0
registers/gen/README.txt View File

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+
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+Scripts for converting .svd to assembler definitions (EQU).
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+
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+Before use, you have to install the `cmsis-svd` python module.
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+
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+https://github.com/posborne/cmsis-svd
7
+
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+---
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+
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+At the top of the script is some configuration that has to be
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+adjusted for your particular SVD.
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+
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+The produced file may also need some manual tweaking.

+ 207 - 0
registers/gen/to_asm_f031x.py View File

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+
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+from cmsis_svd.parser import SVDParser
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+import json
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+import re
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+
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+# ------------------------------------
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+
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+svd_name = 'STM32F031x.svd'
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+
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+want_ofs = True
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+want_len = True
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+
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+# Do not print poripheral field definitions (same as first instance)
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+no_print_fields = [
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+	'GPIOB',
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+	'GPIOC',
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+	'GPIOD',
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+	'GPIOE',
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+	'GPIOA',
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+	'GPIOG',
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+	'USART2',
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+	'USART3',
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+	'ADC2',
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+	'ADC3',
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+	'ADC4',
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+	'ADC34',
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+	'I2C2',
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+	'I2C3',
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+	'SPI2',
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+	'SPI3',
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+]
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+
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+# Same registers as... (points to first instance)
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+same_regs_as = {
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+	'GPIOB': 'GPIOF',
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+	'GPIOC': 'GPIOF',
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+	'GPIOD': 'GPIOF',
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+	'GPIOE': 'GPIOF',
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+	'GPIOA': 'GPIOF',
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+	'GPIOG': 'GPIOF',
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+	'GPIOH': 'GPIOF',
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+	'USART2': 'USART1',
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+	'USART3': 'USART1',
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+	'TIM4': 'TIM3',
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+	'DAC2': 'DAC1',
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+	'ADC2': 'ADC1',
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+	'ADC3': 'ADC1',
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+	'ADC4': 'ADC1',
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+	'ADC34': 'ADC12',
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+	'I2C2': 'I2C1',
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+	'I2C3': 'I2C1',
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+	'SPI2': 'SPI1',
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+	'SPI3': 'SPI1',
54
+}
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+
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+# Rename peripheral when building field definitions
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+# Used for multiple instances (build fields only for the first)
58
+periph_rename_for_field = {
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+	'GPIOF': 'GPIO',
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+	'USART1': 'USART',
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+	'DAC1': 'DAC',
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+	'ADC12': 'ADCC',
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+	'I2C1': 'I2C',
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+	'SPI1': 'SPI'
65
+}
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+
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+# Rename peripheral when generating (bad name in SVD)
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+periph_rename = {
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+	'ADC1_2': 'ADC12',
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+	'ADC3_4': 'ADC34',
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+	'Flash': 'FLASH'
72
+}
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+
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+
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+
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+
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+# ------------------------------------
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+
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+base_line = "{0:<30} EQU {1:#x}"
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+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
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+field_line = "{0:<30} EQU {1:#010x}"
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+field_ofs_line = "{0:<30} EQU {1:#d}"
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+field_len_line = field_ofs_line
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+
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+def comment_str(x):
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+	if x is None:
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+		return ''
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+
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+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
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+
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+def comment(x):
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+	print(comment_str(x))
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+
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+def banner(x):
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+	comment('==== {:=<55}'.format("%s " % x))
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+
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+def caption(x):
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+	print()
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+	comment('---- {:-<55}'.format("%s " % x))
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+
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+def comment(x):
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+	print(comment_str(x))
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+
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+
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+# ------------------------------------
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+
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+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
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+device = parser.get_device()
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+
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+print()
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+banner('%s PERIPHERALS' % device.name)
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+comment('')
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+comment('CTU Prague, FEL, Department of Measurement')
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+comment('')
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+comment('-' * 60)
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+comment('')
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+comment('Generated from "%s"' % svd_name)
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+comment('')
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+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
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+comment('    https://github.com/posborne/cmsis-svd')
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+comment('ASM building script (c) Ondrej Hruska, 2016')
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+comment('')
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+comment('=' * 60)
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+print()
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+
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+
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+
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+# periph registers
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+def print_registers(peripheral, pname=None):
130
+	if pname is None:
131
+		pname = periph_rename.get(peripheral.name, peripheral.name)
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+
133
+	for register in peripheral.registers:
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+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
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+		comment(register.description)
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+
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+
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+# periph fields
139
+def print_fields(peripheral, pname=None):
140
+	if pname is None:
141
+		pname = periph_rename.get(peripheral.name, peripheral.name)
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+
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+	for register in peripheral.registers:
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+
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+		print()
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+		comment('%s_%s fields:' % (pname, register.name))
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+		print()
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+
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+		for field in register.fields:
150
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
151
+
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+			f_pname = periph_rename_for_field.get(pname, pname)
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+
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+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
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+			comment(field.description)
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+
157
+			if want_ofs:
158
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
159
+
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+			if want_len:
161
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
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+
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+		print()
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+
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+
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+# Print the list
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+
168
+periph_dict = {}
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+
170
+for peripheral in device.peripherals:
171
+
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+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
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+
174
+	# add to a dict for referencing by name
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+	periph_dict[periph_name] = peripheral
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+
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+	# -----
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+	caption(periph_name)
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+	comment('Desc: %s' % peripheral.description)
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+
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+	print()
182
+	comment('%s base address:' % periph_name)
183
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
184
+
185
+
186
+	print()
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+	comment('%s registers:' % periph_name)
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+	print()
189
+
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+	# Registers
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+	if periph_name in same_regs_as:
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+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
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+	else:
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+		print_registers(peripheral)
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+
196
+
197
+	if periph_name in no_print_fields:
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+		comment('Fields the same as in the first instance.')
199
+		continue
200
+
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+	# Fields
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+	if periph_name in same_regs_as:
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+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
204
+	else:
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+		print_fields(peripheral)
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+
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+print('    END\n')

+ 207 - 0
registers/gen/to_asm_f042x.py View File

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1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+svd_name = 'STM32F042x.svd'
9
+
10
+want_ofs = True
11
+want_len = True
12
+
13
+# Do not print poripheral field definitions (same as first instance)
14
+no_print_fields = [
15
+	'GPIOB',
16
+	'GPIOC',
17
+	'GPIOD',
18
+	'GPIOE',
19
+	'GPIOA',
20
+	'GPIOG',
21
+	'USART2',
22
+	'USART3',
23
+	'ADC2',
24
+	'ADC3',
25
+	'ADC4',
26
+	'ADC34',
27
+	'I2C2',
28
+	'I2C3',
29
+	'SPI2',
30
+	'SPI3',
31
+]
32
+
33
+# Same registers as... (points to first instance)
34
+same_regs_as = {
35
+	'GPIOB': 'GPIOF',
36
+	'GPIOC': 'GPIOF',
37
+	'GPIOD': 'GPIOF',
38
+	'GPIOE': 'GPIOF',
39
+	'GPIOA': 'GPIOF',
40
+	'GPIOG': 'GPIOF',
41
+	'GPIOH': 'GPIOF',
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+	'USART2': 'USART1',
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+	'USART3': 'USART1',
44
+	'TIM4': 'TIM3',
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+	'DAC2': 'DAC1',
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+	'ADC2': 'ADC1',
47
+	'ADC3': 'ADC1',
48
+	'ADC4': 'ADC1',
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+	'ADC34': 'ADC12',
50
+	'I2C2': 'I2C1',
51
+	'I2C3': 'I2C1',
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+	'SPI2': 'SPI1',
53
+	'SPI3': 'SPI1',
54
+}
55
+
56
+# Rename peripheral when building field definitions
57
+# Used for multiple instances (build fields only for the first)
58
+periph_rename_for_field = {
59
+	'GPIOF': 'GPIO',
60
+	'USART1': 'USART',
61
+	'DAC1': 'DAC',
62
+	'ADC12': 'ADCC',
63
+	'I2C1': 'I2C',
64
+	'SPI1': 'SPI'
65
+}
66
+
67
+# Rename peripheral when generating (bad name in SVD)
68
+periph_rename = {
69
+	'ADC1_2': 'ADC12',
70
+	'ADC3_4': 'ADC34',
71
+	'Flash': 'FLASH'
72
+}
73
+
74
+
75
+
76
+
77
+# ------------------------------------
78
+
79
+base_line = "{0:<30} EQU {1:#x}"
80
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
81
+field_line = "{0:<30} EQU {1:#010x}"
82
+field_ofs_line = "{0:<30} EQU {1:#d}"
83
+field_len_line = field_ofs_line
84
+
85
+def comment_str(x):
86
+	if x is None:
87
+		return ''
88
+
89
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
90
+
91
+def comment(x):
92
+	print(comment_str(x))
93
+
94
+def banner(x):
95
+	comment('==== {:=<55}'.format("%s " % x))
96
+
97
+def caption(x):
98
+	print()
99
+	comment('---- {:-<55}'.format("%s " % x))
100
+
101
+def comment(x):
102
+	print(comment_str(x))
103
+
104
+
105
+# ------------------------------------
106
+
107
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
108
+device = parser.get_device()
109
+
110
+print()
111
+banner('%s PERIPHERALS' % device.name)
112
+comment('')
113
+comment('CTU Prague, FEL, Department of Measurement')
114
+comment('')
115
+comment('-' * 60)
116
+comment('')
117
+comment('Generated from "%s"' % svd_name)
118
+comment('')
119
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
120
+comment('    https://github.com/posborne/cmsis-svd')
121
+comment('ASM building script (c) Ondrej Hruska, 2016')
122
+comment('')
123
+comment('=' * 60)
124
+print()
125
+
126
+
127
+
128
+# periph registers
129
+def print_registers(peripheral, pname=None):
130
+	if pname is None:
131
+		pname = periph_rename.get(peripheral.name, peripheral.name)
132
+
133
+	for register in peripheral.registers:
134
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
135
+		comment(register.description)
136
+
137
+
138
+# periph fields
139
+def print_fields(peripheral, pname=None):
140
+	if pname is None:
141
+		pname = periph_rename.get(peripheral.name, peripheral.name)
142
+
143
+	for register in peripheral.registers:
144
+
145
+		print()
146
+		comment('%s_%s fields:' % (pname, register.name))
147
+		print()
148
+
149
+		for field in register.fields:
150
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
151
+
152
+			f_pname = periph_rename_for_field.get(pname, pname)
153
+
154
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
155
+			comment(field.description)
156
+
157
+			if want_ofs:
158
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
159
+
160
+			if want_len:
161
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
162
+
163
+		print()
164
+
165
+
166
+# Print the list
167
+
168
+periph_dict = {}
169
+
170
+for peripheral in device.peripherals:
171
+
172
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
173
+
174
+	# add to a dict for referencing by name
175
+	periph_dict[periph_name] = peripheral
176
+
177
+	# -----
178
+	caption(periph_name)
179
+	comment('Desc: %s' % peripheral.description)
180
+
181
+	print()
182
+	comment('%s base address:' % periph_name)
183
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
184
+
185
+
186
+	print()
187
+	comment('%s registers:' % periph_name)
188
+	print()
189
+
190
+	# Registers
191
+	if periph_name in same_regs_as:
192
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
193
+	else:
194
+		print_registers(peripheral)
195
+
196
+
197
+	if periph_name in no_print_fields:
198
+		comment('Fields the same as in the first instance.')
199
+		continue
200
+
201
+	# Fields
202
+	if periph_name in same_regs_as:
203
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
204
+	else:
205
+		print_fields(peripheral)
206
+
207
+print('    END\n')

+ 230 - 0
registers/gen/to_asm_f100xx.py View File

@@ -0,0 +1,230 @@
1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+# ~ $ ls /usr/lib/python3.5/site-packages/cmsis_svd/data/STMicro/
9
+# Contents.txt    STM32F091x.svd   STM32F105xx.svd  STM32F303xE.svd  STM32F401x.svd   STM32F437x.svd    STM32L053x.svd   STM32L15xxxA.svd
10
+# License.html    STM32F0xx.svd    STM32F107xx.svd  STM32F303x.svd   STM32F40x.svd    STM32F439x.svd    STM32L062x.svd   STM32L1xx.svd
11
+# STM32F030.svd   STM32F100xx.svd  STM32F20x.svd    STM32F30x.svd    STM32F411xx.svd  STM32F446x.svd    STM32L063x.svd   STM32L4x6.svd
12
+# STM32F031x.svd  STM32F101xx.svd  STM32F21x.svd    STM32F334x.svd   STM32F41x.svd    STM32F46_79x.svd  STM32L100.svd    STM32W108.svd
13
+# STM32F042x.svd  STM32F102xx.svd  STM32F301x.svd   STM32F37x.svd    STM32F427x.svd   STM32L051x.svd    STM32L15xC.svd
14
+# STM32F072x.svd  STM32F103xx.svd  STM32F302x.svd   STM32F401xE.svd  STM32F429x.svd   STM32L052x.svd    STM32L15xxE.svd
15
+
16
+
17
+svd_name = 'STM32F100xx.svd'
18
+
19
+want_ofs = True
20
+want_len = True
21
+
22
+# Do not print poripheral field definitions (same as first instance)
23
+no_print_fields = [
24
+	'GPIOB',
25
+	'GPIOC',
26
+	'GPIOD',
27
+	'GPIOE',
28
+	'GPIOF',
29
+	'GPIOG',
30
+	'GPIOH',
31
+	'USART2',
32
+	'USART3',
33
+	'USART4',
34
+	'USART5',
35
+	'SPI2',
36
+	'SPI3',
37
+	'TIM3',
38
+	'DAC2',
39
+	'SPI2',
40
+	'SPI3',
41
+	'ADC2',
42
+	'ADC3',
43
+	'ADC4',
44
+	'ADC34',
45
+	'I2C2',
46
+	'I2C3',
47
+]
48
+
49
+# Rename peripheral when building field definitions
50
+# Used for multiple instances (build fields only for the first)
51
+periph_rename_for_field = {
52
+	'GPIOA': 'GPIO',
53
+	'USART1': 'USART',
54
+	'DAC1': 'DAC',
55
+	'SPI1': 'SPI',
56
+	'ADC1': 'ADC',
57
+	'ADC12': 'ADCC',
58
+	'I2C1': 'I2C'
59
+}
60
+
61
+# Same registers as... (points to first instance)
62
+same_regs_as = {
63
+	'GPIOB': 'GPIOA',
64
+	'GPIOC': 'GPIOA',
65
+	'GPIOD': 'GPIOA',
66
+	'GPIOE': 'GPIOA',
67
+	'GPIOF': 'GPIOA',
68
+	'GPIOG': 'GPIOA',
69
+	'GPIOH': 'GPIOA',
70
+	'USART2': 'USART1',
71
+	'USART3': 'USART1',
72
+	'USART4': 'USART1',
73
+	'USART5': 'USART1',
74
+	'DAC2': 'DAC1',
75
+	'SPI2': 'SPI1',
76
+	'SPI3': 'SPI1',
77
+	'ADC2': 'ADC1',
78
+	'ADC3': 'ADC1',
79
+	'ADC4': 'ADC1',
80
+	'I2C2': 'I2C1',
81
+	'I2C3': 'I2C1',
82
+	'ADC34': 'ADC12',
83
+	'ADC2': 'ADC1',
84
+	'ADC3': 'ADC1',
85
+	'ADC4': 'ADC1',
86
+	'TIM3': 'TIM2',
87
+	'TIM4': 'TIM2',
88
+}
89
+
90
+# Rename peripheral when generating (bad name in SVD)
91
+periph_rename = {
92
+	'ADC1_2': 'ADC12',
93
+	'ADC3_4': 'ADC34',
94
+	'Flash': 'FLASH'
95
+}
96
+
97
+
98
+
99
+
100
+# ------------------------------------
101
+
102
+base_line = "{0:<30} EQU {1:#x}"
103
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
104
+field_line = "{0:<30} EQU {1:#010x}"
105
+field_ofs_line = "{0:<30} EQU {1:#d}"
106
+field_len_line = field_ofs_line
107
+
108
+def comment_str(x):
109
+	if x is None:
110
+		return ''
111
+
112
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
113
+
114
+def comment(x):
115
+	print(comment_str(x))
116
+
117
+def banner(x):
118
+	comment('==== {:=<55}'.format("%s " % x))
119
+
120
+def caption(x):
121
+	print()
122
+	comment('---- {:-<55}'.format("%s " % x))
123
+
124
+def comment(x):
125
+	print(comment_str(x))
126
+
127
+
128
+# ------------------------------------
129
+
130
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
131
+device = parser.get_device()
132
+
133
+print()
134
+banner('%s PERIPHERALS' % device.name)
135
+comment('')
136
+comment('CTU Prague, FEL, Department of Measurement')
137
+comment('')
138
+comment('-' * 60)
139
+comment('')
140
+comment('Generated from "%s"' % svd_name)
141
+comment('')
142
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
143
+comment('    https://github.com/posborne/cmsis-svd')
144
+comment('ASM building script (c) Ondrej Hruska, 2016')
145
+comment('')
146
+comment('=' * 60)
147
+print()
148
+
149
+
150
+
151
+# periph registers
152
+def print_registers(peripheral, pname=None):
153
+	if pname is None:
154
+		pname = periph_rename.get(peripheral.name, peripheral.name)
155
+
156
+	for register in peripheral.registers:
157
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
158
+		comment(register.description)
159
+
160
+
161
+# periph fields
162
+def print_fields(peripheral, pname=None):
163
+	if pname is None:
164
+		pname = periph_rename.get(peripheral.name, peripheral.name)
165
+
166
+	for register in peripheral.registers:
167
+
168
+		print()
169
+		comment('%s_%s fields:' % (pname, register.name))
170
+		print()
171
+
172
+		for field in register.fields:
173
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
174
+
175
+			f_pname = periph_rename_for_field.get(pname, pname)
176
+
177
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
178
+			comment(field.description)
179
+
180
+			if want_ofs:
181
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
182
+
183
+			if want_len:
184
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
185
+
186
+		print()
187
+
188
+
189
+# Print the list
190
+
191
+periph_dict = {}
192
+
193
+for peripheral in device.peripherals:
194
+
195
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
196
+
197
+	# add to a dict for referencing by name
198
+	periph_dict[periph_name] = peripheral
199
+
200
+	# -----
201
+	caption(periph_name)
202
+	comment('Desc: %s' % peripheral.description)
203
+
204
+	print()
205
+	comment('%s base address:' % periph_name)
206
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
207
+
208
+
209
+	print()
210
+	comment('%s registers:' % periph_name)
211
+	print()
212
+
213
+	# Registers
214
+	if periph_name in same_regs_as:
215
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
216
+	else:
217
+		print_registers(peripheral)
218
+
219
+
220
+	if periph_name in no_print_fields:
221
+		comment('Fields the same as in the first instance.')
222
+		continue
223
+
224
+	# Fields
225
+	if periph_name in same_regs_as:
226
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
227
+	else:
228
+		print_fields(peripheral)
229
+
230
+print('    END\n')

+ 189 - 0
registers/gen/to_asm_f303x.py View File

@@ -0,0 +1,189 @@
1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+svd_name = 'STM32F303x.svd'
9
+
10
+want_ofs = True
11
+want_len = True
12
+
13
+# Do not print poripheral field definitions (same as first instance)
14
+no_print_fields = [
15
+	'GPIOB',
16
+	'GPIOC',
17
+	'GPIOD',
18
+	'GPIOG',
19
+	'GPIOF',
20
+	'USART2',
21
+	'USART3',
22
+	'ADC2'
23
+]
24
+
25
+# Same registers as... (points to first instance)
26
+same_regs_as = {
27
+	'GPIOB': 'GPIOA',
28
+	'GPIOC': 'GPIOA',
29
+	'GPIOD': 'GPIOA',
30
+	'GPIOE': 'GPIOA',
31
+	'GPIOF': 'GPIOA',
32
+	'GPIOG': 'GPIOG',
33
+	'USART2': 'USART1',
34
+	'USART3': 'USART1',
35
+	'TIM3': 'TIM2',
36
+	'DAC2': 'DAC1',
37
+	'ADC2': 'ADC1'
38
+}
39
+
40
+# Rename peripheral when building field definitions
41
+# Used for multiple instances (build fields only for the first)
42
+periph_rename_for_field = {
43
+	'GPIOA': 'GPIO',
44
+	'USART1': 'USART',
45
+	'DAC1': 'DAC',
46
+	'ADC12': 'ADCC',
47
+	'I2C1': 'I2C'
48
+}
49
+
50
+# Rename peripheral when generating (bad name in SVD)
51
+periph_rename = {
52
+	'ADC1_2': 'ADC12',
53
+	'Flash': 'FLASH'
54
+}
55
+
56
+
57
+
58
+
59
+# ------------------------------------
60
+
61
+base_line = "{0:<30} EQU {1:#x}"
62
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
63
+field_line = "{0:<30} EQU {1:#010x}"
64
+field_ofs_line = "{0:<30} EQU {1:#d}"
65
+field_len_line = field_ofs_line
66
+
67
+def comment_str(x):
68
+	if x is None:
69
+		return ''
70
+
71
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
72
+
73
+def comment(x):
74
+	print(comment_str(x))
75
+
76
+def banner(x):
77
+	comment('==== {:=<55}'.format("%s " % x))
78
+
79
+def caption(x):
80
+	print()
81
+	comment('---- {:-<55}'.format("%s " % x))
82
+
83
+def comment(x):
84
+	print(comment_str(x))
85
+
86
+
87
+# ------------------------------------
88
+
89
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
90
+device = parser.get_device()
91
+
92
+print()
93
+banner('%s PERIPHERALS' % device.name)
94
+comment('')
95
+comment('CTU Prague, FEL, Department of Measurement')
96
+comment('')
97
+comment('-' * 60)
98
+comment('')
99
+comment('Generated from "%s"' % svd_name)
100
+comment('')
101
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
102
+comment('    https://github.com/posborne/cmsis-svd')
103
+comment('ASM building script (c) Ondrej Hruska, 2016')
104
+comment('')
105
+comment('=' * 60)
106
+print()
107
+
108
+
109
+
110
+# periph registers
111
+def print_registers(peripheral, pname=None):
112
+	if pname is None:
113
+		pname = periph_rename.get(peripheral.name, peripheral.name)
114
+
115
+	for register in peripheral.registers:
116
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
117
+		comment(register.description)
118
+
119
+
120
+# periph fields
121
+def print_fields(peripheral, pname=None):
122
+	if pname is None:
123
+		pname = periph_rename.get(peripheral.name, peripheral.name)
124
+
125
+	for register in peripheral.registers:
126
+
127
+		print()
128
+		comment('%s_%s fields:' % (pname, register.name))
129
+		print()
130
+
131
+		for field in register.fields:
132
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
133
+
134
+			f_pname = periph_rename_for_field.get(pname, pname)
135
+
136
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
137
+			comment(field.description)
138
+
139
+			if want_ofs:
140
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
141
+
142
+			if want_len:
143
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
144
+
145
+		print()
146
+
147
+
148
+# Print the list
149
+
150
+periph_dict = {}
151
+
152
+for peripheral in device.peripherals:
153
+
154
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
155
+
156
+	# add to a dict for referencing by name
157
+	periph_dict[periph_name] = peripheral
158
+
159
+	# -----
160
+	caption(periph_name)
161
+	comment('Desc: %s' % peripheral.description)
162
+
163
+	print()
164
+	comment('%s base address:' % periph_name)
165
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
166
+
167
+
168
+	print()
169
+	comment('%s registers:' % periph_name)
170
+	print()
171
+
172
+	# Registers
173
+	if periph_name in same_regs_as:
174
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
175
+	else:
176
+		print_registers(peripheral)
177
+
178
+
179
+	if periph_name in no_print_fields:
180
+		comment('Fields the same as in the first instance.')
181
+		continue
182
+
183
+	# Fields
184
+	if periph_name in same_regs_as:
185
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
186
+	else:
187
+		print_fields(peripheral)
188
+
189
+print('    END\n')

+ 230 - 0
registers/gen/to_asm_f303xE.py View File

@@ -0,0 +1,230 @@
1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+# ~ $ ls /usr/lib/python3.5/site-packages/cmsis_svd/data/STMicro/
9
+# Contents.txt    STM32F091x.svd   STM32F105xx.svd  STM32F303xE.svd  STM32F401x.svd   STM32F437x.svd    STM32L053x.svd   STM32L15xxxA.svd
10
+# License.html    STM32F0xx.svd    STM32F107xx.svd  STM32F303x.svd   STM32F40x.svd    STM32F439x.svd    STM32L062x.svd   STM32L1xx.svd
11
+# STM32F030.svd   STM32F100xx.svd  STM32F20x.svd    STM32F30x.svd    STM32F411xx.svd  STM32F446x.svd    STM32L063x.svd   STM32L4x6.svd
12
+# STM32F031x.svd  STM32F101xx.svd  STM32F21x.svd    STM32F334x.svd   STM32F41x.svd    STM32F46_79x.svd  STM32L100.svd    STM32W108.svd
13
+# STM32F042x.svd  STM32F102xx.svd  STM32F301x.svd   STM32F37x.svd    STM32F427x.svd   STM32L051x.svd    STM32L15xC.svd
14
+# STM32F072x.svd  STM32F103xx.svd  STM32F302x.svd   STM32F401xE.svd  STM32F429x.svd   STM32L052x.svd    STM32L15xxE.svd
15
+
16
+
17
+svd_name = 'STM32F303xE.svd'
18
+
19
+want_ofs = True
20
+want_len = True
21
+
22
+# Do not print poripheral field definitions (same as first instance)
23
+no_print_fields = [
24
+	'GPIOB',
25
+	'GPIOC',
26
+	'GPIOD',
27
+	'GPIOE',
28
+	'GPIOF',
29
+	'GPIOG',
30
+	'GPIOH',
31
+	'USART2',
32
+	'USART3',
33
+	'USART4',
34
+	'USART5',
35
+	'SPI2',
36
+	'SPI3',
37
+	'TIM3',
38
+	'DAC2',
39
+	'SPI2',
40
+	'SPI3',
41
+	'ADC2',
42
+	'ADC3',
43
+	'ADC4',
44
+	'ADC34',
45
+	'I2C2',
46
+	'I2C3',
47
+]
48
+
49
+# Rename peripheral when building field definitions
50
+# Used for multiple instances (build fields only for the first)
51
+periph_rename_for_field = {
52
+	'GPIOA': 'GPIO',
53
+	'USART1': 'USART',
54
+	'DAC1': 'DAC',
55
+	'SPI1': 'SPI',
56
+	'ADC1': 'ADC',
57
+	'ADC12': 'ADCC',
58
+	'I2C1': 'I2C'
59
+}
60
+
61
+# Same registers as... (points to first instance)
62
+same_regs_as = {
63
+	'GPIOB': 'GPIOA',
64
+	'GPIOC': 'GPIOA',
65
+	'GPIOD': 'GPIOA',
66
+	'GPIOE': 'GPIOA',
67
+	'GPIOF': 'GPIOA',
68
+	'GPIOG': 'GPIOA',
69
+	'GPIOH': 'GPIOA',
70
+	'USART2': 'USART1',
71
+	'USART3': 'USART1',
72
+	'USART4': 'USART1',
73
+	'USART5': 'USART1',
74
+	'DAC2': 'DAC1',
75
+	'SPI2': 'SPI1',
76
+	'SPI3': 'SPI1',
77
+	'ADC2': 'ADC1',
78
+	'ADC3': 'ADC1',
79
+	'ADC4': 'ADC1',
80
+	'I2C2': 'I2C1',
81
+	'I2C3': 'I2C1',
82
+	'ADC34': 'ADC12',
83
+	'ADC2': 'ADC1',
84
+	'ADC3': 'ADC1',
85
+	'ADC4': 'ADC1',
86
+	'TIM3': 'TIM2',
87
+	'TIM4': 'TIM2',
88
+}
89
+
90
+# Rename peripheral when generating (bad name in SVD)
91
+periph_rename = {
92
+	'ADC1_2': 'ADC12',
93
+	'ADC3_4': 'ADC34',
94
+	'Flash': 'FLASH'
95
+}
96
+
97
+
98
+
99
+
100
+# ------------------------------------
101
+
102
+base_line = "{0:<30} EQU {1:#x}"
103
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
104
+field_line = "{0:<30} EQU {1:#010x}"
105
+field_ofs_line = "{0:<30} EQU {1:#d}"
106
+field_len_line = field_ofs_line
107
+
108
+def comment_str(x):
109
+	if x is None:
110
+		return ''
111
+
112
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
113
+
114
+def comment(x):
115
+	print(comment_str(x))
116
+
117
+def banner(x):
118
+	comment('==== {:=<55}'.format("%s " % x))
119
+
120
+def caption(x):
121
+	print()
122
+	comment('---- {:-<55}'.format("%s " % x))
123
+
124
+def comment(x):
125
+	print(comment_str(x))
126
+
127
+
128
+# ------------------------------------
129
+
130
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
131
+device = parser.get_device()
132
+
133
+print()
134
+banner('%s PERIPHERALS' % device.name)
135
+comment('')
136
+comment('CTU Prague, FEL, Department of Measurement')
137
+comment('')
138
+comment('-' * 60)
139
+comment('')
140
+comment('Generated from "%s"' % svd_name)
141
+comment('')
142
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
143
+comment('    https://github.com/posborne/cmsis-svd')
144
+comment('ASM building script (c) Ondrej Hruska, 2016')
145
+comment('')
146
+comment('=' * 60)
147
+print()
148
+
149
+
150
+
151
+# periph registers
152
+def print_registers(peripheral, pname=None):
153
+	if pname is None:
154
+		pname = periph_rename.get(peripheral.name, peripheral.name)
155
+
156
+	for register in peripheral.registers:
157
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
158
+		comment(register.description)
159
+
160
+
161
+# periph fields
162
+def print_fields(peripheral, pname=None):
163
+	if pname is None:
164
+		pname = periph_rename.get(peripheral.name, peripheral.name)
165
+
166
+	for register in peripheral.registers:
167
+
168
+		print()
169
+		comment('%s_%s fields:' % (pname, register.name))
170
+		print()
171
+
172
+		for field in register.fields:
173
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
174
+
175
+			f_pname = periph_rename_for_field.get(pname, pname)
176
+
177
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
178
+			comment(field.description)
179
+
180
+			if want_ofs:
181
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
182
+
183
+			if want_len:
184
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
185
+
186
+		print()
187
+
188
+
189
+# Print the list
190
+
191
+periph_dict = {}
192
+
193
+for peripheral in device.peripherals:
194
+
195
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
196
+
197
+	# add to a dict for referencing by name
198
+	periph_dict[periph_name] = peripheral
199
+
200
+	# -----
201
+	caption(periph_name)
202
+	comment('Desc: %s' % peripheral.description)
203
+
204
+	print()
205
+	comment('%s base address:' % periph_name)
206
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
207
+
208
+
209
+	print()
210
+	comment('%s registers:' % periph_name)
211
+	print()
212
+
213
+	# Registers
214
+	if periph_name in same_regs_as:
215
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
216
+	else:
217
+		print_registers(peripheral)
218
+
219
+
220
+	if periph_name in no_print_fields:
221
+		comment('Fields the same as in the first instance.')
222
+		continue
223
+
224
+	# Fields
225
+	if periph_name in same_regs_as:
226
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
227
+	else:
228
+		print_fields(peripheral)
229
+
230
+print('    END\n')

+ 206 - 0
registers/gen/to_asm_f30x.py View File

@@ -0,0 +1,206 @@
1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+svd_name = 'STM32F30x.svd'
9
+
10
+want_ofs = True
11
+want_len = True
12
+
13
+# Do not print poripheral field definitions (same as first instance)
14
+no_print_fields = [
15
+	'GPIOB',
16
+	'GPIOC',
17
+	'GPIOD',
18
+	'GPIOE',
19
+	'GPIOF',
20
+	'GPIOG',
21
+	'USART2',
22
+	'USART3',
23
+	'ADC2',
24
+	'ADC3',
25
+	'ADC4',
26
+	'ADC34',
27
+	'I2C2',
28
+	'I2C3',
29
+	'SPI2',
30
+	'SPI3',
31
+]
32
+
33
+# Same registers as... (points to first instance)
34
+same_regs_as = {
35
+	'GPIOB': 'GPIOA',
36
+	'GPIOC': 'GPIOA',
37
+	'GPIOD': 'GPIOA',
38
+	'GPIOE': 'GPIOA',
39
+	'GPIOF': 'GPIOA',
40
+	'GPIOG': 'GPIOG',
41
+	'GPIOH': 'GPIOH',
42
+	'USART2': 'USART1',
43
+	'USART3': 'USART1',
44
+	'TIM4': 'TIM3',
45
+	'DAC2': 'DAC1',
46
+	'ADC2': 'ADC1',
47
+	'ADC3': 'ADC1',
48
+	'ADC4': 'ADC1',
49
+	'ADC34': 'ADC12',
50
+	'I2C2': 'I2C1',
51
+	'I2C3': 'I2C1',
52
+	'SPI2': 'SPI1',
53
+	'SPI3': 'SPI1',
54
+}
55
+
56
+# Rename peripheral when building field definitions
57
+# Used for multiple instances (build fields only for the first)
58
+periph_rename_for_field = {
59
+	'GPIOA': 'GPIO',
60
+	'USART1': 'USART',
61
+	'DAC1': 'DAC',
62
+	'ADC12': 'ADCC',
63
+	'I2C1': 'I2C'
64
+}
65
+
66
+# Rename peripheral when generating (bad name in SVD)
67
+periph_rename = {
68
+	'ADC1_2': 'ADC12',
69
+	'ADC3_4': 'ADC34',
70
+	'Flash': 'FLASH'
71
+}
72
+
73
+
74
+
75
+
76
+# ------------------------------------
77
+
78
+base_line = "{0:<30} EQU {1:#x}"
79
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
80
+field_line = "{0:<30} EQU {1:#010x}"
81
+field_ofs_line = "{0:<30} EQU {1:#d}"
82
+field_len_line = field_ofs_line
83
+
84
+def comment_str(x):
85
+	if x is None:
86
+		return ''
87
+
88
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
89
+
90
+def comment(x):
91
+	print(comment_str(x))
92
+
93
+def banner(x):
94
+	comment('==== {:=<55}'.format("%s " % x))
95
+
96
+def caption(x):
97
+	print()
98
+	comment('---- {:-<55}'.format("%s " % x))
99
+
100
+def comment(x):
101
+	print(comment_str(x))
102
+
103
+
104
+# ------------------------------------
105
+
106
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
107
+device = parser.get_device()
108
+
109
+print()
110
+banner('%s PERIPHERALS' % device.name)
111
+comment('')
112
+comment('CTU Prague, FEL, Department of Measurement')
113
+comment('')
114
+comment('-' * 60)
115
+comment('')
116
+comment('Generated from "%s"' % svd_name)
117
+comment('')
118
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
119
+comment('    https://github.com/posborne/cmsis-svd')
120
+comment('ASM building script (c) Ondrej Hruska, 2016')
121
+comment('')
122
+comment('=' * 60)
123
+print()
124
+
125
+
126
+
127
+# periph registers
128
+def print_registers(peripheral, pname=None):
129
+	if pname is None:
130
+		pname = periph_rename.get(peripheral.name, peripheral.name)
131
+
132
+	for register in peripheral.registers:
133
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
134
+		comment(register.description)
135
+
136
+
137
+# periph fields
138
+def print_fields(peripheral, pname=None):
139
+	if pname is None:
140
+		pname = periph_rename.get(peripheral.name, peripheral.name)
141
+
142
+	for register in peripheral.registers:
143
+
144
+		print()
145
+		comment('%s_%s fields:' % (pname, register.name))
146
+		print()
147
+
148
+		for field in register.fields:
149
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
150
+
151
+			f_pname = periph_rename_for_field.get(pname, pname)
152
+
153
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
154
+			comment(field.description)
155
+
156
+			if want_ofs:
157
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
158
+
159
+			if want_len:
160
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
161
+
162
+		print()
163
+
164
+
165
+# Print the list
166
+
167
+periph_dict = {}
168
+
169
+for peripheral in device.peripherals:
170
+
171
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
172
+
173
+	# add to a dict for referencing by name
174
+	periph_dict[periph_name] = peripheral
175
+
176
+	# -----
177
+	caption(periph_name)
178
+	comment('Desc: %s' % peripheral.description)
179
+
180
+	print()
181
+	comment('%s base address:' % periph_name)
182
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
183
+
184
+
185
+	print()
186
+	comment('%s registers:' % periph_name)
187
+	print()
188
+
189
+	# Registers
190
+	if periph_name in same_regs_as:
191
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
192
+	else:
193
+		print_registers(peripheral)
194
+
195
+
196
+	if periph_name in no_print_fields:
197
+		comment('Fields the same as in the first instance.')
198
+		continue
199
+
200
+	# Fields
201
+	if periph_name in same_regs_as:
202
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
203
+	else:
204
+		print_fields(peripheral)
205
+
206
+print('    END\n')

+ 207 - 0
registers/gen/to_asm_l100.py View File

@@ -0,0 +1,207 @@
1
+
2
+from cmsis_svd.parser import SVDParser
3
+import json
4
+import re
5
+
6
+# ------------------------------------
7
+
8
+svd_name = 'STM32L100.svd'
9
+
10
+want_ofs = True
11
+want_len = True
12
+
13
+# Do not print poripheral field definitions (same as first instance)
14
+no_print_fields = [
15
+	'GPIOB',
16
+	'GPIOC',
17
+	'GPIOD',
18
+	'GPIOE',
19
+	'GPIOF',
20
+	'GPIOG',
21
+	'USART2',
22
+	'USART3',
23
+	'ADC2',
24
+	'ADC3',
25
+	'ADC4',
26
+	'ADC34',
27
+	'I2C2',
28
+	'I2C3',
29
+	'SPI2',
30
+	'SPI3',
31
+]
32
+
33
+# Same registers as... (points to first instance)
34
+same_regs_as = {
35
+	'GPIOB': 'GPIOA',
36
+	'GPIOC': 'GPIOA',
37
+	'GPIOD': 'GPIOA',
38
+	'GPIOE': 'GPIOA',
39
+	'GPIOF': 'GPIOA',
40
+	'GPIOG': 'GPIOG',
41
+	'GPIOH': 'GPIOH',
42
+	'USART2': 'USART1',
43
+	'USART3': 'USART1',
44
+	'TIM4': 'TIM3',
45
+	'DAC2': 'DAC1',
46
+	'ADC2': 'ADC1',
47
+	'ADC3': 'ADC1',
48
+	'ADC4': 'ADC1',
49
+	'ADC34': 'ADC12',
50
+	'I2C2': 'I2C1',
51
+	'I2C3': 'I2C1',
52
+	'SPI2': 'SPI1',
53
+	'SPI3': 'SPI1',
54
+}
55
+
56
+# Rename peripheral when building field definitions
57
+# Used for multiple instances (build fields only for the first)
58
+periph_rename_for_field = {
59
+	'GPIOA': 'GPIO',
60
+	'USART1': 'USART',
61
+	'DAC1': 'DAC',
62
+	'ADC12': 'ADCC',
63
+	'I2C1': 'I2C',
64
+	'SPI1': 'SPI',
65
+}
66
+
67
+# Rename peripheral when generating (bad name in SVD)
68
+periph_rename = {
69
+	'ADC1_2': 'ADC12',
70
+	'ADC3_4': 'ADC34',
71
+	'Flash': 'FLASH'
72
+}
73
+
74
+
75
+
76
+
77
+# ------------------------------------
78
+
79
+base_line = "{0:<30} EQU {1:#x}"
80
+reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})"
81
+field_line = "{0:<30} EQU {1:#010x}"
82
+field_ofs_line = "{0:<30} EQU {1:#d}"
83
+field_len_line = field_ofs_line
84
+
85
+def comment_str(x):
86
+	if x is None:
87
+		return ''
88
+
89
+	return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' '))
90
+
91
+def comment(x):
92
+	print(comment_str(x))
93
+
94
+def banner(x):
95
+	comment('==== {:=<55}'.format("%s " % x))
96
+
97
+def caption(x):
98
+	print()
99
+	comment('---- {:-<55}'.format("%s " % x))
100
+
101
+def comment(x):
102
+	print(comment_str(x))
103
+
104
+
105
+# ------------------------------------
106
+
107
+parser = SVDParser.for_packaged_svd('STMicro', svd_name)
108
+device = parser.get_device()
109
+
110
+print()
111
+banner('%s PERIPHERALS' % device.name)
112
+comment('')
113
+comment('CTU Prague, FEL, Department of Measurement')
114
+comment('')
115
+comment('-' * 60)
116
+comment('')
117
+comment('Generated from "%s"' % svd_name)
118
+comment('')
119
+comment('SVD parsing library (c) Paul Osborne, 2015-2016')
120
+comment('    https://github.com/posborne/cmsis-svd')
121
+comment('ASM building script (c) Ondrej Hruska, 2016')
122
+comment('')
123
+comment('=' * 60)
124
+print()
125
+
126
+
127
+
128
+# periph registers
129
+def print_registers(peripheral, pname=None):
130
+	if pname is None:
131
+		pname = periph_rename.get(peripheral.name, peripheral.name)
132
+
133
+	for register in peripheral.registers:
134
+		print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ')
135
+		comment(register.description)
136
+
137
+
138
+# periph fields
139
+def print_fields(peripheral, pname=None):
140
+	if pname is None:
141
+		pname = periph_rename.get(peripheral.name, peripheral.name)
142
+
143
+	for register in peripheral.registers:
144
+
145
+		print()
146
+		comment('%s_%s fields:' % (pname, register.name))
147
+		print()
148
+
149
+		for field in register.fields:
150
+			mask = ((1 << field.bit_width) - 1) << field.bit_offset
151
+
152
+			f_pname = periph_rename_for_field.get(pname, pname)
153
+
154
+			print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ')
155
+			comment(field.description)
156
+
157
+			if want_ofs:
158
+				print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset))
159
+
160
+			if want_len:
161
+				print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width))
162
+
163
+		print()
164
+
165
+
166
+# Print the list
167
+
168
+periph_dict = {}
169
+
170
+for peripheral in device.peripherals:
171
+
172
+	periph_name = periph_rename.get(peripheral.name, peripheral.name)
173
+
174
+	# add to a dict for referencing by name
175
+	periph_dict[periph_name] = peripheral
176
+
177
+	# -----
178
+	caption(periph_name)
179
+	comment('Desc: %s' % peripheral.description)
180
+
181
+	print()
182
+	comment('%s base address:' % periph_name)
183
+	print(base_line.format("%s_BASE" % periph_name, peripheral.base_address))
184
+
185
+
186
+	print()
187
+	comment('%s registers:' % periph_name)
188
+	print()
189
+
190
+	# Registers
191
+	if periph_name in same_regs_as:
192
+		print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name)
193
+	else:
194
+		print_registers(peripheral)
195
+
196
+
197
+	if periph_name in no_print_fields:
198
+		comment('Fields the same as in the first instance.')
199
+		continue
200
+
201
+	# Fields
202
+	if periph_name in same_regs_as:
203
+		print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name)
204
+	else:
205
+		print_fields(peripheral)
206
+
207
+print('    END\n')

+ 7 - 0
registers/gen/to_json.py View File

@@ -0,0 +1,7 @@
1
+import json
2
+from cmsis_svd.parser import SVDParser
3
+
4
+parser = SVDParser.for_packaged_svd('STMicro', 'STM32F042x.svd')
5
+svd_dict = parser.get_device().to_dict()
6
+print(json.dumps(svd_dict, sort_keys=True,
7
+                 indent=4, separators=(',', ': ')))

File diff suppressed because it is too large
+ 6335 - 0
registers/sfr_f031x.asm


File diff suppressed because it is too large
+ 7991 - 0
registers/sfr_f042x.asm


File diff suppressed because it is too large
+ 7016 - 0
registers/sfr_f100xx.asm


File diff suppressed because it is too large
+ 11031 - 0
registers/sfr_f303x.asm


File diff suppressed because it is too large
+ 11650 - 0
registers/sfr_f303xE.asm


File diff suppressed because it is too large
+ 11524 - 0
registers/sfr_f30x.asm


File diff suppressed because it is too large
+ 5823 - 0
registers/sfr_l100.asm


+ 50 - 0
registers/sfr_systick.asm View File

@@ -0,0 +1,50 @@
1
+;****************************************************************************
2
+;*
3
+;*                               REGISTERS
4
+;*
5
+;****************************************************************************
6
+
7
+SYSTICK_BASE       EQU 0xE000E010
8
+
9
+SYSTICK_CR         EQU (SYSTICK_BASE + 0x010)        ; (R/W) SysTick Control and Status Register
10
+SYSTICK_RELOAD     EQU (SYSTICK_BASE + 0x014)        ; (R/W) SysTick Reload Value Register
11
+SYSTICK_VAL        EQU (SYSTICK_BASE + 0x018)        ; (R/W) SysTick Current Value Register
12
+SYSTICK_CALIB      EQU (SYSTICK_BASE + 0x01C)        ; (R/ ) SysTick Calibration Value Register
13
+
14
+
15
+;****************************************************************************
16
+;*
17
+;*                       BIT MASKS AND DEFINITIONS
18
+;*
19
+;****************************************************************************
20
+
21
+
22
+;****************  Bit definition for SYSTICK_CR register  ****************
23
+
24
+SYSTICK_CR_ENABLE              EQU  0x00000001    ; Counter enable
25
+SYSTICK_CR_ENABLE_ofs          EQU  0
26
+SYSTICK_CR_ENABLE_len          EQU  1
27
+
28
+SYSTICK_CR_TICKINT             EQU  0x00000002    ; Enable interrupt when counter reaches zero
29
+SYSTICK_CR_TICKINT_ofs         EQU  1
30
+SYSTICK_CR_TICKINT_len         EQU  1
31
+
32
+SYSTICK_CR_CLKSOURCE           EQU  0x00000004    ; Clock source (0 - clock div 8, 1 - core clock)
33
+SYSTICK_CR_CLKSOURCE_ofs       EQU  2
34
+SYSTICK_CR_CLKSOURCE_len       EQU  1
35
+
36
+SYSTICK_CR_COUNTFLAG           EQU  0x00010000    ; Count Flag (only if interrupt is disabled)
37
+SYSTICK_CR_COUNTFLAG_ofs       EQU  16
38
+SYSTICK_CR_COUNTFLAG_len       EQU  1
39
+
40
+; masks
41
+SYSTICK_RELOAD_MASK            EQU  0x00FFFFFF    ; Reload value used when the counter reaches 0
42
+SYSTICK_VAL_MASK               EQU  0x00FFFFFF    ; Current value at the time the register is accessed
43
+
44
+
45
+; systick calib (according to datasheet)
46
+SYSTICK_CALIB_TENMS            EQU  0x00FFFFFF    ; Reload value to use for 10ms timing
47
+SYSTICK_CALIB_SKEW             EQU  0x40000000    ; Calibration value is not exactly 10 ms
48
+SYSTICK_CALIB_NOREF            EQU  0x80000000    ; The reference clock is not provided
49
+
50
+	END

+ 27 - 0
startup_scripts/README.md View File

@@ -0,0 +1,27 @@
1
+Startup scripts for STM32
2
+=========================
3
+
4
+All startup scripts are taken from Standard Peripheral Library, or the STM Cube.
5
+
6
+The scripts provided here are the "arm" variant, meant for ARM assembler or ARM-CC.
7
+
8
+License
9
+-------
10
+
11
+```none
12
+;*******************************************************************************
13
+; 
14
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15
+; You may not use this file except in compliance with the License.
16
+; You may obtain a copy of the License at:
17
+; 
18
+;        http://www.st.com/software_license_agreement_liberty_v2
19
+; 
20
+; Unless required by applicable law or agreed to in writing, software 
21
+; distributed under the License is distributed on an "AS IS" BASIS, 
22
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+; See the License for the specific language governing permissions and
24
+; limitations under the License.
25
+; 
26
+;*******************************************************************************
27
+```

+ 244 - 0
startup_scripts/f0xx/startup_stm32f030x6.s View File

@@ -0,0 +1,244 @@
1
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
2
+;* File Name          : startup_stm32f030x6.s
3
+;* Author             : MCD Application Team
4
+;* Version            : V2.2.2
5
+;* Date               : 26-June-2015
6
+;* Description        : STM32F030x4/STM32F030x6 devices vector table for MDK-ARM toolchain.
7
+;*                      This module performs:
8
+;*                      - Set the initial SP
9
+;*                      - Set the initial PC == Reset_Handler
10
+;*                      - Set the vector table entries with the exceptions ISR address
11
+;*                      - Branches to __main in the C library (which eventually
12
+;*                        calls main()).
13
+;*                      After Reset the CortexM0 processor is in Thread mode,
14
+;*                      priority is Privileged, and the Stack is set to Main.
15
+;* <<< Use Configuration Wizard in Context Menu >>>
16
+;*******************************************************************************
17
+;
18
+;* Redistribution and use in source and binary forms, with or without modification,
19
+;* are permitted provided that the following conditions are met:
20
+;*   1. Redistributions of source code must retain the above copyright notice,
21
+;*      this list of conditions and the following disclaimer.
22
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
23
+;*      this list of conditions and the following disclaimer in the documentation
24
+;*      and/or other materials provided with the distribution.
25
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
26
+;*      may be used to endorse or promote products derived from this software
27
+;*      without specific prior written permission.
28
+;*
29
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+;
40
+;*******************************************************************************
41
+
42
+; Amount of memory (in bytes) allocated for Stack
43
+; Tailor this value to your application needs
44
+; <h> Stack Configuration
45
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46
+; </h>
47
+
48
+Stack_Size      EQU     0x00000400
49
+
50
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
51
+Stack_Mem       SPACE   Stack_Size
52
+__initial_sp
53
+
54
+
55
+; <h> Heap Configuration
56
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57
+; </h>
58
+
59
+Heap_Size       EQU     0x00000200
60
+
61
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
62
+__heap_base
63
+Heap_Mem        SPACE   Heap_Size
64
+__heap_limit
65
+
66
+                PRESERVE8
67
+                THUMB
68
+
69
+
70
+; Vector Table Mapped to Address 0 at Reset
71
+                AREA    RESET, DATA, READONLY
72
+                EXPORT  __Vectors
73
+                EXPORT  __Vectors_End
74
+                EXPORT  __Vectors_Size
75
+
76
+__Vectors       DCD     __initial_sp                   ; Top of Stack
77
+                DCD     Reset_Handler                  ; Reset Handler
78
+                DCD     NMI_Handler                    ; NMI Handler
79
+                DCD     HardFault_Handler              ; Hard Fault Handler
80
+                DCD     0                              ; Reserved
81
+                DCD     0                              ; Reserved
82
+                DCD     0                              ; Reserved
83
+                DCD     0                              ; Reserved
84
+                DCD     0                              ; Reserved
85
+                DCD     0                              ; Reserved
86
+                DCD     0                              ; Reserved
87
+                DCD     SVC_Handler                    ; SVCall Handler
88
+                DCD     0                              ; Reserved
89
+                DCD     0                              ; Reserved
90
+                DCD     PendSV_Handler                 ; PendSV Handler
91
+                DCD     SysTick_Handler                ; SysTick Handler
92
+
93
+                ; External Interrupts
94
+                DCD     WWDG_IRQHandler                ; Window Watchdog
95
+                DCD     0                              ; Reserved
96
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
97
+                DCD     FLASH_IRQHandler               ; FLASH
98
+                DCD     RCC_IRQHandler                 ; RCC
99
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
100
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
101
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
102
+                DCD     0                              ; Reserved
103
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
104
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
105
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
106
+                DCD     ADC1_IRQHandler                ; ADC1 
107
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
108
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
109
+                DCD     0                              ; Reserved
110
+                DCD     TIM3_IRQHandler                ; TIM3
111
+                DCD     0                              ; Reserved
112
+                DCD     0                              ; Reserved
113
+                DCD     TIM14_IRQHandler               ; TIM14
114
+                DCD     0                              ; Reserved
115
+                DCD     TIM16_IRQHandler               ; TIM16
116
+                DCD     TIM17_IRQHandler               ; TIM17
117
+                DCD     I2C1_IRQHandler                ; I2C1
118
+                DCD     0                              ; Reserved
119
+                DCD     SPI1_IRQHandler                ; SPI1
120
+                DCD     0                              ; Reserved
121
+                DCD     USART1_IRQHandler              ; USART1
122
+
123
+
124
+__Vectors_End
125
+
126
+__Vectors_Size  EQU  __Vectors_End - __Vectors
127
+
128
+                AREA    |.text|, CODE, READONLY
129
+
130
+; Reset handler routine
131
+Reset_Handler    PROC
132
+                 EXPORT  Reset_Handler                 [WEAK]
133
+        IMPORT  __main
134
+        IMPORT  SystemInit  
135
+                 LDR     R0, =SystemInit
136
+                 BLX     R0
137
+                 LDR     R0, =__main
138
+                 BX      R0
139
+                 ENDP
140
+
141
+; Dummy Exception Handlers (infinite loops which can be modified)
142
+
143
+NMI_Handler     PROC
144
+                EXPORT  NMI_Handler                    [WEAK]
145
+                B       .
146
+                ENDP
147
+HardFault_Handler\
148
+                PROC
149
+                EXPORT  HardFault_Handler              [WEAK]
150
+                B       .
151
+                ENDP
152
+SVC_Handler     PROC
153
+                EXPORT  SVC_Handler                    [WEAK]
154
+                B       .
155
+                ENDP
156
+PendSV_Handler  PROC
157
+                EXPORT  PendSV_Handler                 [WEAK]
158
+                B       .
159
+                ENDP
160
+SysTick_Handler PROC
161
+                EXPORT  SysTick_Handler                [WEAK]
162
+                B       .
163
+                ENDP
164
+
165
+Default_Handler PROC
166
+
167
+                EXPORT  WWDG_IRQHandler                [WEAK]
168
+                EXPORT  RTC_IRQHandler                 [WEAK]
169
+                EXPORT  FLASH_IRQHandler               [WEAK]
170
+                EXPORT  RCC_IRQHandler                 [WEAK]
171
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
172
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
173
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
174
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
175
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
176
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
177
+                EXPORT  ADC1_IRQHandler                [WEAK]
178
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
179
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
180
+                EXPORT  TIM3_IRQHandler                [WEAK]
181
+                EXPORT  TIM14_IRQHandler               [WEAK]
182
+                EXPORT  TIM16_IRQHandler               [WEAK]
183
+                EXPORT  TIM17_IRQHandler               [WEAK]
184
+                EXPORT  I2C1_IRQHandler                [WEAK]
185
+                EXPORT  SPI1_IRQHandler                [WEAK]
186
+                EXPORT  USART1_IRQHandler              [WEAK]
187
+ 
188
+
189
+WWDG_IRQHandler
190
+RTC_IRQHandler
191
+FLASH_IRQHandler
192
+RCC_IRQHandler
193
+EXTI0_1_IRQHandler
194
+EXTI2_3_IRQHandler
195
+EXTI4_15_IRQHandler
196
+DMA1_Channel1_IRQHandler
197
+DMA1_Channel2_3_IRQHandler
198
+DMA1_Channel4_5_IRQHandler
199
+ADC1_IRQHandler 
200
+TIM1_BRK_UP_TRG_COM_IRQHandler
201
+TIM1_CC_IRQHandler
202
+TIM3_IRQHandler
203
+TIM14_IRQHandler
204
+TIM16_IRQHandler
205
+TIM17_IRQHandler
206
+I2C1_IRQHandler
207
+SPI1_IRQHandler
208
+USART1_IRQHandler
209
+
210
+                B       .
211
+
212
+                ENDP
213
+
214
+                ALIGN
215
+
216
+;*******************************************************************************
217
+; User Stack and Heap initialization
218
+;*******************************************************************************
219
+                 IF      :DEF:__MICROLIB
220
+
221
+                 EXPORT  __initial_sp
222
+                 EXPORT  __heap_base
223
+                 EXPORT  __heap_limit
224
+
225
+                 ELSE
226
+
227
+                 IMPORT  __use_two_region_memory
228
+                 EXPORT  __user_initial_stackheap
229
+
230
+__user_initial_stackheap
231
+
232
+                 LDR     R0, =  Heap_Mem
233
+                 LDR     R1, =(Stack_Mem + Stack_Size)
234
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
235
+                 LDR     R3, = Stack_Mem
236
+                 BX      LR
237
+
238
+                 ALIGN
239
+
240
+                 ENDIF
241
+
242
+                 END
243
+
244
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

+ 252 - 0
startup_scripts/f0xx/startup_stm32f030x8.s View File

@@ -0,0 +1,252 @@
1
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
2
+;* File Name          : startup_stm32f030x8.s
3
+;* Author             : MCD Application Team
4
+;* Version            : V2.2.2
5
+;* Date               : 26-June-2015
6
+;* Description        : STM32F030x8 devices vector table for MDK-ARM toolchain.
7
+;*                      This module performs:
8
+;*                      - Set the initial SP
9
+;*                      - Set the initial PC == Reset_Handler
10
+;*                      - Set the vector table entries with the exceptions ISR address
11
+;*                      - Branches to __main in the C library (which eventually
12
+;*                        calls main()).
13
+;*                      After Reset the CortexM0 processor is in Thread mode,
14
+;*                      priority is Privileged, and the Stack is set to Main.
15
+;* <<< Use Configuration Wizard in Context Menu >>>
16
+;*******************************************************************************
17
+;
18
+;* Redistribution and use in source and binary forms, with or without modification,
19
+;* are permitted provided that the following conditions are met:
20
+;*   1. Redistributions of source code must retain the above copyright notice,
21
+;*      this list of conditions and the following disclaimer.
22
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
23
+;*      this list of conditions and the following disclaimer in the documentation
24
+;*      and/or other materials provided with the distribution.
25
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
26
+;*      may be used to endorse or promote products derived from this software
27
+;*      without specific prior written permission.
28
+;*
29
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+;
40
+;*******************************************************************************
41
+
42
+; Amount of memory (in bytes) allocated for Stack
43
+; Tailor this value to your application needs
44
+; <h> Stack Configuration
45
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46
+; </h>
47
+
48
+Stack_Size      EQU     0x00000400
49
+
50
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
51
+Stack_Mem       SPACE   Stack_Size
52
+__initial_sp
53
+
54
+
55
+; <h> Heap Configuration
56
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57
+; </h>
58
+
59
+Heap_Size       EQU     0x00000200
60
+
61
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
62
+__heap_base
63
+Heap_Mem        SPACE   Heap_Size
64
+__heap_limit
65
+
66
+                PRESERVE8
67
+                THUMB
68
+
69
+
70
+; Vector Table Mapped to Address 0 at Reset
71
+                AREA    RESET, DATA, READONLY
72
+                EXPORT  __Vectors
73
+                EXPORT  __Vectors_End
74
+                EXPORT  __Vectors_Size
75
+
76
+__Vectors       DCD     __initial_sp                   ; Top of Stack
77
+                DCD     Reset_Handler                  ; Reset Handler
78
+                DCD     NMI_Handler                    ; NMI Handler
79
+                DCD     HardFault_Handler              ; Hard Fault Handler
80
+                DCD     0                              ; Reserved
81
+                DCD     0                              ; Reserved
82
+                DCD     0                              ; Reserved
83
+                DCD     0                              ; Reserved
84
+                DCD     0                              ; Reserved
85
+                DCD     0                              ; Reserved
86
+                DCD     0                              ; Reserved
87
+                DCD     SVC_Handler                    ; SVCall Handler
88
+                DCD     0                              ; Reserved
89
+                DCD     0                              ; Reserved
90
+                DCD     PendSV_Handler                 ; PendSV Handler
91
+                DCD     SysTick_Handler                ; SysTick Handler
92
+
93
+                ; External Interrupts
94
+                DCD     WWDG_IRQHandler                ; Window Watchdog
95
+                DCD     0                              ; Reserved
96
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
97
+                DCD     FLASH_IRQHandler               ; FLASH
98
+                DCD     RCC_IRQHandler                 ; RCC
99
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
100
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
101
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
102
+                DCD     0                              ; Reserved
103
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
104
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
105
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
106
+                DCD     ADC1_IRQHandler                ; ADC1 
107
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
108
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
109
+                DCD     0                              ; Reserved
110
+                DCD     TIM3_IRQHandler                ; TIM3
111
+                DCD     0                              ; Reserved
112
+                DCD     0                              ; Reserved
113
+                DCD     TIM14_IRQHandler               ; TIM14
114
+                DCD     TIM15_IRQHandler               ; TIM15
115
+                DCD     TIM16_IRQHandler               ; TIM16
116
+                DCD     TIM17_IRQHandler               ; TIM17
117
+                DCD     I2C1_IRQHandler                ; I2C1
118
+                DCD     I2C2_IRQHandler                ; I2C2
119
+                DCD     SPI1_IRQHandler                ; SPI1
120
+                DCD     SPI2_IRQHandler                ; SPI2
121
+                DCD     USART1_IRQHandler              ; USART1
122
+                DCD     USART2_IRQHandler              ; USART2
123
+
124
+__Vectors_End
125
+
126
+__Vectors_Size  EQU  __Vectors_End - __Vectors
127
+
128
+                AREA    |.text|, CODE, READONLY
129
+
130
+; Reset handler routine
131
+Reset_Handler    PROC
132
+                 EXPORT  Reset_Handler                 [WEAK]
133
+        IMPORT  __main
134
+        IMPORT  SystemInit  
135
+                 LDR     R0, =SystemInit
136
+                 BLX     R0
137
+                 LDR     R0, =__main
138
+                 BX      R0
139
+                 ENDP
140
+
141
+; Dummy Exception Handlers (infinite loops which can be modified)
142
+
143
+NMI_Handler     PROC
144
+                EXPORT  NMI_Handler                    [WEAK]
145
+                B       .
146
+                ENDP
147
+HardFault_Handler\
148
+                PROC
149
+                EXPORT  HardFault_Handler              [WEAK]
150
+                B       .
151
+                ENDP
152
+SVC_Handler     PROC
153
+                EXPORT  SVC_Handler                    [WEAK]
154
+                B       .
155
+                ENDP
156
+PendSV_Handler  PROC
157
+                EXPORT  PendSV_Handler                 [WEAK]
158
+                B       .
159
+                ENDP
160
+SysTick_Handler PROC
161
+                EXPORT  SysTick_Handler                [WEAK]
162
+                B       .
163
+                ENDP
164
+
165
+Default_Handler PROC
166
+
167
+                EXPORT  WWDG_IRQHandler                [WEAK]
168
+                EXPORT  RTC_IRQHandler                 [WEAK]
169
+                EXPORT  FLASH_IRQHandler               [WEAK]
170
+                EXPORT  RCC_IRQHandler                 [WEAK]
171
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
172
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
173
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
174
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
175
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
176
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
177
+                EXPORT  ADC1_IRQHandler                [WEAK]
178
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
179
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
180
+                EXPORT  TIM3_IRQHandler                [WEAK]
181
+                EXPORT  TIM14_IRQHandler               [WEAK]
182
+                EXPORT  TIM15_IRQHandler               [WEAK]
183
+                EXPORT  TIM16_IRQHandler               [WEAK]
184
+                EXPORT  TIM17_IRQHandler               [WEAK]
185
+                EXPORT  I2C1_IRQHandler                [WEAK]
186
+                EXPORT  I2C2_IRQHandler                [WEAK]
187
+                EXPORT  SPI1_IRQHandler                [WEAK]
188
+                EXPORT  SPI2_IRQHandler                [WEAK]
189
+                EXPORT  USART1_IRQHandler              [WEAK]
190
+                EXPORT  USART2_IRQHandler              [WEAK]
191
+
192
+
193
+WWDG_IRQHandler
194
+RTC_IRQHandler
195
+FLASH_IRQHandler
196
+RCC_IRQHandler
197
+EXTI0_1_IRQHandler
198
+EXTI2_3_IRQHandler
199
+EXTI4_15_IRQHandler
200
+DMA1_Channel1_IRQHandler
201
+DMA1_Channel2_3_IRQHandler
202
+DMA1_Channel4_5_IRQHandler
203
+ADC1_IRQHandler 
204
+TIM1_BRK_UP_TRG_COM_IRQHandler
205
+TIM1_CC_IRQHandler
206
+TIM3_IRQHandler
207
+TIM14_IRQHandler
208
+TIM15_IRQHandler
209
+TIM16_IRQHandler
210
+TIM17_IRQHandler
211
+I2C1_IRQHandler
212
+I2C2_IRQHandler
213
+SPI1_IRQHandler
214
+SPI2_IRQHandler
215
+USART1_IRQHandler
216
+USART2_IRQHandler
217
+
218
+                B       .
219
+
220
+                ENDP
221
+
222
+                ALIGN
223
+
224
+;*******************************************************************************
225
+; User Stack and Heap initialization
226
+;*******************************************************************************
227
+                 IF      :DEF:__MICROLIB
228
+
229
+                 EXPORT  __initial_sp
230
+                 EXPORT  __heap_base
231
+                 EXPORT  __heap_limit
232
+
233
+                 ELSE
234
+
235
+                 IMPORT  __use_two_region_memory
236
+                 EXPORT  __user_initial_stackheap
237
+
238
+__user_initial_stackheap
239
+
240
+                 LDR     R0, =  Heap_Mem
241
+                 LDR     R1, =(Stack_Mem + Stack_Size)
242
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
243
+                 LDR     R3, = Stack_Mem
244
+                 BX      LR
245
+
246
+                 ALIGN
247
+
248
+                 ENDIF
249
+
250
+                 END
251
+
252
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

+ 259 - 0
startup_scripts/f0xx/startup_stm32f030xc.s View File

@@ -0,0 +1,259 @@
1
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
2
+;* File Name          : startup_stm32f030xc.s
3
+;* Author             : MCD Application Team
4
+;* Version            : V2.2.2
5
+;* Date               : 26-June-2015
6
+;* Description        : STM32F030xc/STM32F030xb devices vector table for MDK-ARM toolchain.
7
+;*                      This module performs:
8
+;*                      - Set the initial SP
9
+;*                      - Set the initial PC == Reset_Handler
10
+;*                      - Set the vector table entries with the exceptions ISR address
11
+;*                      - Branches to __main in the C library (which eventually
12
+;*                        calls main()).
13
+;*                      After Reset the CortexM0 processor is in Thread mode,
14
+;*                      priority is Privileged, and the Stack is set to Main.
15
+;* <<< Use Configuration Wizard in Context Menu >>>
16
+;*******************************************************************************
17
+;
18
+;* Redistribution and use in source and binary forms, with or without modification,
19
+;* are permitted provided that the following conditions are met:
20
+;*   1. Redistributions of source code must retain the above copyright notice,
21
+;*      this list of conditions and the following disclaimer.
22
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
23
+;*      this list of conditions and the following disclaimer in the documentation
24
+;*      and/or other materials provided with the distribution.
25
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
26
+;*      may be used to endorse or promote products derived from this software
27
+;*      without specific prior written permission.
28
+;*
29
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+;
40
+;*******************************************************************************
41
+
42
+; Amount of memory (in bytes) allocated for Stack
43
+; Tailor this value to your application needs
44
+; <h> Stack Configuration
45
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46
+; </h>
47
+
48
+Stack_Size      EQU     0x00000400
49
+
50
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
51
+Stack_Mem       SPACE   Stack_Size
52
+__initial_sp
53
+
54
+
55
+; <h> Heap Configuration
56
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57
+; </h>
58
+
59
+Heap_Size       EQU     0x00000200
60
+
61
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
62
+__heap_base
63
+Heap_Mem        SPACE   Heap_Size
64
+__heap_limit
65
+
66
+                PRESERVE8
67
+                THUMB
68
+
69
+
70
+; Vector Table Mapped to Address 0 at Reset
71
+                AREA    RESET, DATA, READONLY
72
+                EXPORT  __Vectors
73
+                EXPORT  __Vectors_End
74
+                EXPORT  __Vectors_Size
75
+
76
+__Vectors       DCD     __initial_sp                   ; Top of Stack
77
+                DCD     Reset_Handler                  ; Reset Handler
78
+                DCD     NMI_Handler                    ; NMI Handler
79
+                DCD     HardFault_Handler              ; Hard Fault Handler
80
+                DCD     0                              ; Reserved
81
+                DCD     0                              ; Reserved
82
+                DCD     0                              ; Reserved
83
+                DCD     0                              ; Reserved
84
+                DCD     0                              ; Reserved
85
+                DCD     0                              ; Reserved
86
+                DCD     0                              ; Reserved
87
+                DCD     SVC_Handler                    ; SVCall Handler
88
+                DCD     0                              ; Reserved
89
+                DCD     0                              ; Reserved
90
+                DCD     PendSV_Handler                 ; PendSV Handler
91
+                DCD     SysTick_Handler                ; SysTick Handler
92
+
93
+                ; External Interrupts
94
+                DCD     WWDG_IRQHandler                ; Window Watchdog
95
+                DCD     0                              ; Reserved
96
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
97
+                DCD     FLASH_IRQHandler               ; FLASH
98
+                DCD     RCC_IRQHandler                 ; RCC
99
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
100
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
101
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
102
+                DCD     0                              ; Reserved
103
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
104
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
105
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
106
+                DCD     ADC1_IRQHandler                ; ADC1 
107
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
108
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
109
+                DCD     0                              ; Reserved
110
+                DCD     TIM3_IRQHandler                ; TIM3
111
+                DCD     TIM6_IRQHandler                ; TIM6
112
+                DCD     TIM7_IRQHandler                ; TIM7
113
+                DCD     TIM14_IRQHandler               ; TIM14
114
+                DCD     TIM15_IRQHandler               ; TIM15
115
+                DCD     TIM16_IRQHandler               ; TIM16
116
+                DCD     TIM17_IRQHandler               ; TIM17
117
+                DCD     I2C1_IRQHandler                ; I2C1
118
+                DCD     I2C2_IRQHandler                ; I2C2
119
+                DCD     SPI1_IRQHandler                ; SPI1
120
+                DCD     SPI2_IRQHandler                ; SPI2
121
+                DCD     USART1_IRQHandler              ; USART1
122
+                DCD     USART2_IRQHandler              ; USART2
123
+                DCD     USART3_6_IRQHandler            ; USART3, USART4, USART5, USART6
124
+                
125
+__Vectors_End
126
+
127
+__Vectors_Size  EQU  __Vectors_End - __Vectors
128
+
129
+                AREA    |.text|, CODE, READONLY
130
+
131
+; Reset handler routine
132
+Reset_Handler    PROC
133
+                 EXPORT  Reset_Handler                 [WEAK]
134
+        IMPORT  __main
135
+        IMPORT  SystemInit  
136
+                 LDR     R0, =SystemInit
137
+                 BLX     R0
138
+                 LDR     R0, =__main
139
+                 BX      R0
140
+                 ENDP
141
+
142
+; Dummy Exception Handlers (infinite loops which can be modified)
143
+
144
+NMI_Handler     PROC
145
+                EXPORT  NMI_Handler                    [WEAK]
146
+                B       .
147
+                ENDP
148
+HardFault_Handler\
149
+                PROC
150
+                EXPORT  HardFault_Handler              [WEAK]
151
+                B       .
152
+                ENDP
153
+SVC_Handler     PROC
154
+                EXPORT  SVC_Handler                    [WEAK]
155
+                B       .
156
+                ENDP
157
+PendSV_Handler  PROC
158
+                EXPORT  PendSV_Handler                 [WEAK]
159
+                B       .
160
+                ENDP
161
+SysTick_Handler PROC
162
+                EXPORT  SysTick_Handler                [WEAK]
163
+                B       .
164
+                ENDP
165
+
166
+Default_Handler PROC
167
+
168
+                EXPORT  WWDG_IRQHandler                [WEAK]
169
+                EXPORT  RTC_IRQHandler                 [WEAK]
170
+                EXPORT  FLASH_IRQHandler               [WEAK]
171
+                EXPORT  RCC_IRQHandler                 [WEAK]
172
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
173
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
174
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
175
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
176
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
177
+                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
178
+                EXPORT  ADC1_IRQHandler                [WEAK]
179
+                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
180
+                EXPORT  TIM1_CC_IRQHandler             [WEAK]
181
+                EXPORT  TIM3_IRQHandler                [WEAK]
182
+                EXPORT  TIM6_IRQHandler                [WEAK]
183
+                EXPORT  TIM7_IRQHandler                [WEAK]
184
+                EXPORT  TIM14_IRQHandler               [WEAK]
185
+                EXPORT  TIM15_IRQHandler               [WEAK]
186
+                EXPORT  TIM16_IRQHandler               [WEAK]
187
+                EXPORT  TIM17_IRQHandler               [WEAK]
188
+                EXPORT  I2C1_IRQHandler                [WEAK]
189
+                EXPORT  I2C2_IRQHandler                [WEAK]
190
+                EXPORT  SPI1_IRQHandler                [WEAK]
191
+                EXPORT  SPI2_IRQHandler                [WEAK]
192
+                EXPORT  USART1_IRQHandler              [WEAK]
193
+                EXPORT  USART2_IRQHandler              [WEAK]
194
+                EXPORT  USART3_6_IRQHandler            [WEAK]
195
+
196
+
197
+WWDG_IRQHandler
198
+RTC_IRQHandler
199
+FLASH_IRQHandler
200
+RCC_IRQHandler
201
+EXTI0_1_IRQHandler
202
+EXTI2_3_IRQHandler
203
+EXTI4_15_IRQHandler
204
+DMA1_Channel1_IRQHandler
205
+DMA1_Channel2_3_IRQHandler
206
+DMA1_Channel4_5_IRQHandler
207
+ADC1_IRQHandler 
208
+TIM1_BRK_UP_TRG_COM_IRQHandler
209
+TIM1_CC_IRQHandler
210
+TIM3_IRQHandler
211
+TIM6_IRQHandler
212
+TIM7_IRQHandler
213
+TIM14_IRQHandler
214
+TIM15_IRQHandler
215
+TIM16_IRQHandler
216
+TIM17_IRQHandler
217
+I2C1_IRQHandler
218
+I2C2_IRQHandler
219
+SPI1_IRQHandler
220
+SPI2_IRQHandler
221
+USART1_IRQHandler
222
+USART2_IRQHandler
223
+USART3_6_IRQHandler
224
+
225
+                B       .
226
+
227
+                ENDP
228
+
229
+                ALIGN
230
+
231
+;*******************************************************************************
232
+; User Stack and Heap initialization
233
+;*******************************************************************************
234
+                 IF      :DEF:__MICROLIB
235
+
236
+                 EXPORT  __initial_sp
237
+                 EXPORT  __heap_base
238
+                 EXPORT  __heap_limit
239
+
240
+                 ELSE
241
+
242
+                 IMPORT  __use_two_region_memory
243
+                 EXPORT  __user_initial_stackheap
244
+
245
+__user_initial_stackheap
246
+
247
+                 LDR     R0, =  Heap_Mem
248
+                 LDR     R1, =(Stack_Mem + Stack_Size)
249
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
250
+                 LDR     R3, = Stack_Mem
251
+                 BX      LR
252
+
253
+                 ALIGN
254
+
255
+                 ENDIF
256
+
257
+                 END
258
+
259
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

+ 248 - 0
startup_scripts/f0xx/startup_stm32f031x6.s View File

@@ -0,0 +1,248 @@
1
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
2
+;* File Name          : startup_stm32f031x6.s
3
+;* Author             : MCD Application Team
4
+;* Version            : V2.2.2
5
+;* Date               : 26-June-2015
6
+;* Description        : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
7
+;*                      This module performs:
8
+;*                      - Set the initial SP
9
+;*                      - Set the initial PC == Reset_Handler
10
+;*                      - Set the vector table entries with the exceptions ISR address
11
+;*                      - Branches to __main in the C library (which eventually
12
+;*                        calls main()).
13
+;*                      After Reset the CortexM0 processor is in Thread mode,
14
+;*                      priority is Privileged, and the Stack is set to Main.
15
+;* <<< Use Configuration Wizard in Context Menu >>>
16
+;*******************************************************************************
17
+;
18
+;* Redistribution and use in source and binary forms, with or without modification,
19
+;* are permitted provided that the following conditions are met:
20
+;*   1. Redistributions of source code must retain the above copyright notice,
21
+;*      this list of conditions and the following disclaimer.
22
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
23
+;*      this list of conditions and the following disclaimer in the documentation
24
+;*      and/or other materials provided with the distribution.
25
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
26
+;*      may be used to endorse or promote products derived from this software
27
+;*      without specific prior written permission.
28
+;*
29
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+;
40
+;*******************************************************************************
41
+
42
+; Amount of memory (in bytes) allocated for Stack
43
+; Tailor this value to your application needs
44
+; <h> Stack Configuration
45
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46
+; </h>
47
+
48
+Stack_Size      EQU     0x00000400
49
+
50
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
51
+Stack_Mem       SPACE   Stack_Size
52
+__initial_sp
53
+
54
+
55
+; <h> Heap Configuration
56
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
57
+; </h>
58
+
59
+Heap_Size       EQU     0x00000200
60
+
61
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
62
+__heap_base
63
+Heap_Mem        SPACE   Heap_Size
64
+__heap_limit
65
+
66
+                PRESERVE8
67
+                THUMB
68
+
69
+
70
+; Vector Table Mapped to Address 0 at Reset
71
+                AREA    RESET, DATA, READONLY
72
+                EXPORT  __Vectors
73
+                EXPORT  __Vectors_End
74
+                EXPORT  __Vectors_Size
75
+
76
+__Vectors       DCD     __initial_sp                   ; Top of Stack
77
+                DCD     Reset_Handler                  ; Reset Handler
78
+                DCD     NMI_Handler                    ; NMI Handler
79
+                DCD     HardFault_Handler              ; Hard Fault Handler
80
+                DCD     0                              ; Reserved
81
+                DCD     0                              ; Reserved
82
+                DCD     0                              ; Reserved
83
+                DCD     0                              ; Reserved
84
+                DCD     0                              ; Reserved
85
+                DCD     0                              ; Reserved
86
+                DCD     0                              ; Reserved
87
+                DCD     SVC_Handler                    ; SVCall Handler
88
+                DCD     0                              ; Reserved
89
+                DCD     0                              ; Reserved
90
+                DCD     PendSV_Handler                 ; PendSV Handler
91
+                DCD     SysTick_Handler                ; SysTick Handler
92
+
93
+                ; External Interrupts
94
+                DCD     WWDG_IRQHandler                ; Window Watchdog
95
+                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
96
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
97
+                DCD     FLASH_IRQHandler               ; FLASH
98
+                DCD     RCC_IRQHandler                 ; RCC
99
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
100
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
101
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
102
+                DCD     0                              ; Reserved
103
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
104
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
105
+                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
106
+                DCD     ADC1_IRQHandler                ; ADC1 
107
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
108
+                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
109
+                DCD     TIM2_IRQHandler                ; TIM2
110
+                DCD     TIM3_IRQHandler                ; TIM3
111
+                DCD     0                              ; Reserved
112
+                DCD     0                              ; Reserved
113
+                DCD     TIM14_IRQHandler               ; TIM14
114
+                DCD     0                              ; Reserved
115
+                DCD     TIM16_IRQHandler               ; TIM16
116
+                DCD     TIM17_IRQHandler               ; TIM17
117
+                DCD     I2C1_IRQHandler                ; I2C1
118
+                DCD     0                              ; Reserved
119
+                DCD     SPI1_IRQHandler                ; SPI1
120
+                DCD     0                              ; Reserved
121
+                DCD     USART1_IRQHandler              ; USART1
122
+
123
+
124
+__Vectors_End
125
+
126
+__Vectors_Size  EQU  __Vectors_End - __Vectors
127
+
128
+                AREA    |.text|, CODE, READONLY
129
+
130
+; Reset handler routine
131
+Reset_Handler    PROC
132
+                 EXPORT  Reset_Handler                 [WEAK]
133
+        IMPORT  __main
134
+        IMPORT  SystemInit  
135
+                 LDR     R0, =SystemInit
136
+                 BLX     R0
137
+                 LDR     R0, =__main
138
+                 BX      R0
139
+                 ENDP
140
+
141
+; Dummy Exception Handlers (infinite loops which can be modified)
142
+
143
+NMI_Handler     PROC
144
+                EXPORT  NMI_Handler                    [WEAK]
145
+                B       .
146
+                ENDP
147
+HardFault_Handler\
148
+                PROC
149
+                EXPORT  HardFault_Handler              [WEAK]
150
+                B       .
151
+                ENDP
152
+SVC_Handler     PROC
153
+                EXPORT  SVC_Handler                    [WEAK]
154
+                B       .
155
+                ENDP
156
+PendSV_Handler  PROC
157
+                EXPORT  PendSV_Handler                 [WEAK]
158
+                B       .
159
+                ENDP
160
+SysTick_Handler PROC
161
+                EXPORT  SysTick_Handler                [WEAK]
162
+                B       .
163
+                ENDP
164
+
165
+Default_Handler PROC
166
+
167
+                EXPORT  WWDG_IRQHandler                [WEAK]
168
+                EXPORT  PVD_IRQHandler                 [WEAK]
169
+                EXPORT  RTC_IRQHandler                 [WEAK]
170
+                EXPORT  FLASH_IRQHandler               [WEAK]
171
+                EXPORT  RCC_IRQHandler                 [WEAK]
172
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
173
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
174
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
175
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]