commit
fe17c2029f
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STM32 assembler examples |
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======================== |
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|
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This project provides examples for programming the STM32 microcontrollers in ARM assembler. |
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|
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Please visit the project folders for additional information (they contain separate READMEs). |
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|
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License |
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------- |
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|
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Unless otherwise specified (as is the case with the startup scripts), all files in this repository |
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are subject to the MIT license. |
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|
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For details, refer to the LICENSE file. |
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Register definitions |
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==================== |
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|
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Those files provide definitions of register addresses and bit field mapping. |
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|
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Include the appropriate file using the ` GET 'filename.asm'` directive in your |
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main file. |
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|
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Example |
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------- |
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|
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```asm |
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; GPIOA base address: |
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GPIOA_BASE EQU 0x48000000 |
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|
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; GPIOA registers: |
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|
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GPIOA_MODER EQU (GPIOA_BASE + 0x0) ; GPIO port mode register |
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GPIOA_OTYPER EQU (GPIOA_BASE + 0x4) ; GPIO port output type register |
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; ... |
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|
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; GPIO_MODER fields: |
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|
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GPIO_MODER_MODER15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15) |
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GPIO_MODER_MODER15_ofs EQU 30 |
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GPIO_MODER_MODER15_len EQU 2 |
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GPIO_MODER_MODER14 EQU 0x30000000 ; Port x configuration bits (y = 0..15) |
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GPIO_MODER_MODER14_ofs EQU 28 |
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GPIO_MODER_MODER14_len EQU 2 |
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; ... |
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``` |
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Registers for a peripheral are named `<peripheral>_<register>`. |
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|
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Bit fields are named `<peripheral>_<register>_<field>`, and the field length and offset |
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are available in the `_len` and `_ofs` constants. |
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|
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Notice how the peripheral is called `GPIOA`, but firlds are named `GPIO_...`. That is because |
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all GPIOs have the same register structure, so they also share the same field definitions. |
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|
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Generating |
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---------- |
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|
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The definition files are in a large part generated from the CMSIS SVD files, with just a few manual modifications. |
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|
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See the `gen/` folder for more info on how this conversion works. |
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The register or bit field naming may differ from the datasheet, which is ST's fault. Feel free to correct those mistakes and **submit a pull request**. |
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@ -0,0 +1,13 @@ |
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Scripts for converting .svd to assembler definitions (EQU). |
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Before use, you have to install the `cmsis-svd` python module. |
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https://github.com/posborne/cmsis-svd |
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--- |
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|
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At the top of the script is some configuration that has to be |
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adjusted for your particular SVD. |
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|
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The produced file may also need some manual tweaking. |
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@ -0,0 +1,207 @@ |
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from cmsis_svd.parser import SVDParser |
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import json |
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import re |
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# ------------------------------------ |
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svd_name = 'STM32F031x.svd' |
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want_ofs = True |
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want_len = True |
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|
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# Do not print poripheral field definitions (same as first instance) |
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no_print_fields = [ |
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'GPIOB', |
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'GPIOC', |
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'GPIOD', |
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'GPIOE', |
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'GPIOA', |
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'GPIOG', |
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'USART2', |
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'USART3', |
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'ADC2', |
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'ADC3', |
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'ADC4', |
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'ADC34', |
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'I2C2', |
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'I2C3', |
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'SPI2', |
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'SPI3', |
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] |
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|
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# Same registers as... (points to first instance) |
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same_regs_as = { |
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'GPIOB': 'GPIOF', |
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'GPIOC': 'GPIOF', |
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'GPIOD': 'GPIOF', |
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'GPIOE': 'GPIOF', |
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'GPIOA': 'GPIOF', |
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'GPIOG': 'GPIOF', |
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'GPIOH': 'GPIOF', |
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'USART2': 'USART1', |
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'USART3': 'USART1', |
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'TIM4': 'TIM3', |
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'DAC2': 'DAC1', |
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'ADC2': 'ADC1', |
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'ADC3': 'ADC1', |
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'ADC4': 'ADC1', |
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'ADC34': 'ADC12', |
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'I2C2': 'I2C1', |
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'I2C3': 'I2C1', |
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'SPI2': 'SPI1', |
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'SPI3': 'SPI1', |
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} |
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|
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# Rename peripheral when building field definitions |
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# Used for multiple instances (build fields only for the first) |
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periph_rename_for_field = { |
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'GPIOF': 'GPIO', |
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'USART1': 'USART', |
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'DAC1': 'DAC', |
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'ADC12': 'ADCC', |
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'I2C1': 'I2C', |
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'SPI1': 'SPI' |
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} |
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|
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# Rename peripheral when generating (bad name in SVD) |
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periph_rename = { |
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'ADC1_2': 'ADC12', |
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'ADC3_4': 'ADC34', |
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'Flash': 'FLASH' |
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} |
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# ------------------------------------ |
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base_line = "{0:<30} EQU {1:#x}" |
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reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
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field_line = "{0:<30} EQU {1:#010x}" |
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field_ofs_line = "{0:<30} EQU {1:#d}" |
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field_len_line = field_ofs_line |
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|
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def comment_str(x): |
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if x is None: |
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return '' |
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return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
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|
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def comment(x): |
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print(comment_str(x)) |
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def banner(x): |
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comment('==== {:=<55}'.format("%s " % x)) |
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def caption(x): |
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print() |
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comment('---- {:-<55}'.format("%s " % x)) |
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def comment(x): |
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print(comment_str(x)) |
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# ------------------------------------ |
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parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
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device = parser.get_device() |
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print() |
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banner('%s PERIPHERALS' % device.name) |
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comment('') |
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comment('CTU Prague, FEL, Department of Measurement') |
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comment('') |
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comment('-' * 60) |
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comment('') |
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comment('Generated from "%s"' % svd_name) |
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comment('') |
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comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
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comment(' https://github.com/posborne/cmsis-svd') |
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comment('ASM building script (c) Ondrej Hruska, 2016') |
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comment('') |
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comment('=' * 60) |
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print() |
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# periph registers |
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def print_registers(peripheral, pname=None): |
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if pname is None: |
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pname = periph_rename.get(peripheral.name, peripheral.name) |
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for register in peripheral.registers: |
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print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
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comment(register.description) |
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# periph fields |
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def print_fields(peripheral, pname=None): |
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if pname is None: |
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pname = periph_rename.get(peripheral.name, peripheral.name) |
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for register in peripheral.registers: |
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print() |
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comment('%s_%s fields:' % (pname, register.name)) |
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print() |
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for field in register.fields: |
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mask = ((1 << field.bit_width) - 1) << field.bit_offset |
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f_pname = periph_rename_for_field.get(pname, pname) |
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print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
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comment(field.description) |
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if want_ofs: |
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print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
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if want_len: |
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print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
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print() |
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# Print the list |
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periph_dict = {} |
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for peripheral in device.peripherals: |
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periph_name = periph_rename.get(peripheral.name, peripheral.name) |
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# add to a dict for referencing by name |
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periph_dict[periph_name] = peripheral |
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# ----- |
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caption(periph_name) |
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comment('Desc: %s' % peripheral.description) |
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print() |
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comment('%s base address:' % periph_name) |
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print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
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print() |
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comment('%s registers:' % periph_name) |
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print() |
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# Registers |
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if periph_name in same_regs_as: |
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print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
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else: |
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print_registers(peripheral) |
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if periph_name in no_print_fields: |
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comment('Fields the same as in the first instance.') |
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continue |
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# Fields |
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if periph_name in same_regs_as: |
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print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
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else: |
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print_fields(peripheral) |
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print(' END\n') |
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@ -0,0 +1,207 @@ |
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from cmsis_svd.parser import SVDParser |
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import json |
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import re |
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# ------------------------------------ |
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svd_name = 'STM32F042x.svd' |
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want_ofs = True |
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want_len = True |
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# Do not print poripheral field definitions (same as first instance) |
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no_print_fields = [ |
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'GPIOB', |
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'GPIOC', |
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'GPIOD', |
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'GPIOE', |
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'GPIOA', |
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'GPIOG', |
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'USART2', |
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'USART3', |
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'ADC2', |
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'ADC3', |
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'ADC4', |
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'ADC34', |
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'I2C2', |
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'I2C3', |
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'SPI2', |
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'SPI3', |
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] |
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|
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# Same registers as... (points to first instance) |
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same_regs_as = { |
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'GPIOB': 'GPIOF', |
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'GPIOC': 'GPIOF', |
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'GPIOD': 'GPIOF', |
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'GPIOE': 'GPIOF', |
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'GPIOA': 'GPIOF', |
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'GPIOG': 'GPIOF', |
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'GPIOH': 'GPIOF', |
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'USART2': 'USART1', |
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'USART3': 'USART1', |
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'TIM4': 'TIM3', |
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'DAC2': 'DAC1', |
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'ADC2': 'ADC1', |
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'ADC3': 'ADC1', |
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'ADC4': 'ADC1', |
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'ADC34': 'ADC12', |
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'I2C2': 'I2C1', |
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'I2C3': 'I2C1', |
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'SPI2': 'SPI1', |
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'SPI3': 'SPI1', |
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} |
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|
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# Rename peripheral when building field definitions |
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# Used for multiple instances (build fields only for the first) |
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periph_rename_for_field = { |
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'GPIOF': 'GPIO', |
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'USART1': 'USART', |
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'DAC1': 'DAC', |
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'ADC12': 'ADCC', |
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'I2C1': 'I2C', |
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'SPI1': 'SPI' |
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} |
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|
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# Rename peripheral when generating (bad name in SVD) |
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periph_rename = { |
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'ADC1_2': 'ADC12', |
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'ADC3_4': 'ADC34', |
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'Flash': 'FLASH' |
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} |
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|
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|
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|
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|
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# ------------------------------------ |
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base_line = "{0:<30} EQU {1:#x}" |
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reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
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field_line = "{0:<30} EQU {1:#010x}" |
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field_ofs_line = "{0:<30} EQU {1:#d}" |
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field_len_line = field_ofs_line |
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|
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def comment_str(x): |
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if x is None: |
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return '' |
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|
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return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
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|
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def comment(x): |
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print(comment_str(x)) |
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|
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def banner(x): |
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comment('==== {:=<55}'.format("%s " % x)) |
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|
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def caption(x): |
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print() |
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comment('---- {:-<55}'.format("%s " % x)) |
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|
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def comment(x): |
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print(comment_str(x)) |
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|
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# ------------------------------------ |
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parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
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device = parser.get_device() |
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print() |
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banner('%s PERIPHERALS' % device.name) |
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comment('') |
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comment('CTU Prague, FEL, Department of Measurement') |
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comment('') |
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comment('-' * 60) |
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comment('') |
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comment('Generated from "%s"' % svd_name) |
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comment('') |
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comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
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comment(' https://github.com/posborne/cmsis-svd') |
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comment('ASM building script (c) Ondrej Hruska, 2016') |
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comment('') |
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comment('=' * 60) |
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print() |
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|
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|
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|
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# periph registers |
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def print_registers(peripheral, pname=None): |
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if pname is None: |
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pname = periph_rename.get(peripheral.name, peripheral.name) |
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|
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for register in peripheral.registers: |
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print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
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comment(register.description) |
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|
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|
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# periph fields |
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def print_fields(peripheral, pname=None): |
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if pname is None: |
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pname = periph_rename.get(peripheral.name, peripheral.name) |
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|
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for register in peripheral.registers: |
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|
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print() |
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comment('%s_%s fields:' % (pname, register.name)) |
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print() |
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|
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for field in register.fields: |
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mask = ((1 << field.bit_width) - 1) << field.bit_offset |
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|
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f_pname = periph_rename_for_field.get(pname, pname) |
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|
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print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
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comment(field.description) |
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|
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if want_ofs: |
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print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
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|
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if want_len: |
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print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
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|
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print() |
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|
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|
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# Print the list |
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|
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periph_dict = {} |
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|
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for peripheral in device.peripherals: |
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|
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periph_name = periph_rename.get(peripheral.name, peripheral.name) |
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|
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# add to a dict for referencing by name |
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periph_dict[periph_name] = peripheral |
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|
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# ----- |
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caption(periph_name) |
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comment('Desc: %s' % peripheral.description) |
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|
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print() |
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comment('%s base address:' % periph_name) |
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print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
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|
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|
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print() |
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comment('%s registers:' % periph_name) |
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print() |
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|
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# Registers |
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if periph_name in same_regs_as: |
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print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
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else: |
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print_registers(peripheral) |
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|
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|
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if periph_name in no_print_fields: |
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comment('Fields the same as in the first instance.') |
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continue |
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|
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# Fields |
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if periph_name in same_regs_as: |
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print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
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else: |
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print_fields(peripheral) |
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|
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print(' END\n') |
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@ -0,0 +1,230 @@ |
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|
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from cmsis_svd.parser import SVDParser |
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import json |
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import re |
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|
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# ------------------------------------ |
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|
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# ~ $ ls /usr/lib/python3.5/site-packages/cmsis_svd/data/STMicro/ |
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# Contents.txt STM32F091x.svd STM32F105xx.svd STM32F303xE.svd STM32F401x.svd STM32F437x.svd STM32L053x.svd STM32L15xxxA.svd |
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# License.html STM32F0xx.svd STM32F107xx.svd STM32F303x.svd STM32F40x.svd STM32F439x.svd STM32L062x.svd STM32L1xx.svd |
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# STM32F030.svd STM32F100xx.svd STM32F20x.svd STM32F30x.svd STM32F411xx.svd STM32F446x.svd STM32L063x.svd STM32L4x6.svd |
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# STM32F031x.svd STM32F101xx.svd STM32F21x.svd STM32F334x.svd STM32F41x.svd STM32F46_79x.svd STM32L100.svd STM32W108.svd |
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# STM32F042x.svd STM32F102xx.svd STM32F301x.svd STM32F37x.svd STM32F427x.svd STM32L051x.svd STM32L15xC.svd |
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# STM32F072x.svd STM32F103xx.svd STM32F302x.svd STM32F401xE.svd STM32F429x.svd STM32L052x.svd STM32L15xxE.svd |
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|
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|
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svd_name = 'STM32F100xx.svd' |
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|
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want_ofs = True |
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want_len = True |
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|
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# Do not print poripheral field definitions (same as first instance) |
||||
no_print_fields = [ |
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'GPIOB', |
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'GPIOC', |
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'GPIOD', |
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'GPIOE', |
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'GPIOF', |
||||
'GPIOG', |
||||
'GPIOH', |
||||
'USART2', |
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'USART3', |
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'USART4', |
||||
'USART5', |
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'SPI2', |
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'SPI3', |
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'TIM3', |
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'DAC2', |
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'SPI2', |
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'SPI3', |
||||
'ADC2', |
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'ADC3', |
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'ADC4', |
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'ADC34', |
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'I2C2', |
||||
'I2C3', |
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] |
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|
||||
# Rename peripheral when building field definitions |
||||
# Used for multiple instances (build fields only for the first) |
||||
periph_rename_for_field = { |
||||
'GPIOA': 'GPIO', |
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'USART1': 'USART', |
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'DAC1': 'DAC', |
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'SPI1': 'SPI', |
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'ADC1': 'ADC', |
||||
'ADC12': 'ADCC', |
||||
'I2C1': 'I2C' |
||||
} |
||||
|
||||
# Same registers as... (points to first instance) |
||||
same_regs_as = { |
||||
'GPIOB': 'GPIOA', |
||||
'GPIOC': 'GPIOA', |
||||
'GPIOD': 'GPIOA', |
||||
'GPIOE': 'GPIOA', |
||||
'GPIOF': 'GPIOA', |
||||
'GPIOG': 'GPIOA', |
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'GPIOH': 'GPIOA', |
||||
'USART2': 'USART1', |
||||
'USART3': 'USART1', |
||||
'USART4': 'USART1', |
||||
'USART5': 'USART1', |
||||
'DAC2': 'DAC1', |
||||
'SPI2': 'SPI1', |
||||
'SPI3': 'SPI1', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'I2C2': 'I2C1', |
||||
'I2C3': 'I2C1', |
||||
'ADC34': 'ADC12', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'TIM3': 'TIM2', |
||||
'TIM4': 'TIM2', |
||||
} |
||||
|
||||
# Rename peripheral when generating (bad name in SVD) |
||||
periph_rename = { |
||||
'ADC1_2': 'ADC12', |
||||
'ADC3_4': 'ADC34', |
||||
'Flash': 'FLASH' |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
base_line = "{0:<30} EQU {1:#x}" |
||||
reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
||||
field_line = "{0:<30} EQU {1:#010x}" |
||||
field_ofs_line = "{0:<30} EQU {1:#d}" |
||||
field_len_line = field_ofs_line |
||||
|
||||
def comment_str(x): |
||||
if x is None: |
||||
return '' |
||||
|
||||
return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
def banner(x): |
||||
comment('==== {:=<55}'.format("%s " % x)) |
||||
|
||||
def caption(x): |
||||
print() |
||||
comment('---- {:-<55}'.format("%s " % x)) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
||||
device = parser.get_device() |
||||
|
||||
print() |
||||
banner('%s PERIPHERALS' % device.name) |
||||
comment('') |
||||
comment('CTU Prague, FEL, Department of Measurement') |
||||
comment('') |
||||
comment('-' * 60) |
||||
comment('') |
||||
comment('Generated from "%s"' % svd_name) |
||||
comment('') |
||||
comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
||||
comment(' https://github.com/posborne/cmsis-svd') |
||||
comment('ASM building script (c) Ondrej Hruska, 2016') |
||||
comment('') |
||||
comment('=' * 60) |
||||
print() |
||||
|
||||
|
||||
|
||||
# periph registers |
||||
def print_registers(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
||||
comment(register.description) |
||||
|
||||
|
||||
# periph fields |
||||
def print_fields(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
|
||||
print() |
||||
comment('%s_%s fields:' % (pname, register.name)) |
||||
print() |
||||
|
||||
for field in register.fields: |
||||
mask = ((1 << field.bit_width) - 1) << field.bit_offset |
||||
|
||||
f_pname = periph_rename_for_field.get(pname, pname) |
||||
|
||||
print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
||||
comment(field.description) |
||||
|
||||
if want_ofs: |
||||
print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
||||
|
||||
if want_len: |
||||
print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
||||
|
||||
print() |
||||
|
||||
|
||||
# Print the list |
||||
|
||||
periph_dict = {} |
||||
|
||||
for peripheral in device.peripherals: |
||||
|
||||
periph_name = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
# add to a dict for referencing by name |
||||
periph_dict[periph_name] = peripheral |
||||
|
||||
# ----- |
||||
caption(periph_name) |
||||
comment('Desc: %s' % peripheral.description) |
||||
|
||||
print() |
||||
comment('%s base address:' % periph_name) |
||||
print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
||||
|
||||
|
||||
print() |
||||
comment('%s registers:' % periph_name) |
||||
print() |
||||
|
||||
# Registers |
||||
if periph_name in same_regs_as: |
||||
print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_registers(peripheral) |
||||
|
||||
|
||||
if periph_name in no_print_fields: |
||||
comment('Fields the same as in the first instance.') |
||||
continue |
||||
|
||||
# Fields |
||||
if periph_name in same_regs_as: |
||||
print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_fields(peripheral) |
||||
|
||||
print(' END\n') |
||||
@ -0,0 +1,189 @@ |
||||
|
||||
from cmsis_svd.parser import SVDParser |
||||
import json |
||||
import re |
||||
|
||||
# ------------------------------------ |
||||
|
||||
svd_name = 'STM32F303x.svd' |
||||
|
||||
want_ofs = True |
||||
want_len = True |
||||
|
||||
# Do not print poripheral field definitions (same as first instance) |
||||
no_print_fields = [ |
||||
'GPIOB', |
||||
'GPIOC', |
||||
'GPIOD', |
||||
'GPIOG', |
||||
'GPIOF', |
||||
'USART2', |
||||
'USART3', |
||||
'ADC2' |
||||
] |
||||
|
||||
# Same registers as... (points to first instance) |
||||
same_regs_as = { |
||||
'GPIOB': 'GPIOA', |
||||
'GPIOC': 'GPIOA', |
||||
'GPIOD': 'GPIOA', |
||||
'GPIOE': 'GPIOA', |
||||
'GPIOF': 'GPIOA', |
||||
'GPIOG': 'GPIOG', |
||||
'USART2': 'USART1', |
||||
'USART3': 'USART1', |
||||
'TIM3': 'TIM2', |
||||
'DAC2': 'DAC1', |
||||
'ADC2': 'ADC1' |
||||
} |
||||
|
||||
# Rename peripheral when building field definitions |
||||
# Used for multiple instances (build fields only for the first) |
||||
periph_rename_for_field = { |
||||
'GPIOA': 'GPIO', |
||||
'USART1': 'USART', |
||||
'DAC1': 'DAC', |
||||
'ADC12': 'ADCC', |
||||
'I2C1': 'I2C' |
||||
} |
||||
|
||||
# Rename peripheral when generating (bad name in SVD) |
||||
periph_rename = { |
||||
'ADC1_2': 'ADC12', |
||||
'Flash': 'FLASH' |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
base_line = "{0:<30} EQU {1:#x}" |
||||
reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
||||
field_line = "{0:<30} EQU {1:#010x}" |
||||
field_ofs_line = "{0:<30} EQU {1:#d}" |
||||
field_len_line = field_ofs_line |
||||
|
||||
def comment_str(x): |
||||
if x is None: |
||||
return '' |
||||
|
||||
return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
def banner(x): |
||||
comment('==== {:=<55}'.format("%s " % x)) |
||||
|
||||
def caption(x): |
||||
print() |
||||
comment('---- {:-<55}'.format("%s " % x)) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
||||
device = parser.get_device() |
||||
|
||||
print() |
||||
banner('%s PERIPHERALS' % device.name) |
||||
comment('') |
||||
comment('CTU Prague, FEL, Department of Measurement') |
||||
comment('') |
||||
comment('-' * 60) |
||||
comment('') |
||||
comment('Generated from "%s"' % svd_name) |
||||
comment('') |
||||
comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
||||
comment(' https://github.com/posborne/cmsis-svd') |
||||
comment('ASM building script (c) Ondrej Hruska, 2016') |
||||
comment('') |
||||
comment('=' * 60) |
||||
print() |
||||
|
||||
|
||||
|
||||
# periph registers |
||||
def print_registers(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
||||
comment(register.description) |
||||
|
||||
|
||||
# periph fields |
||||
def print_fields(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
|
||||
print() |
||||
comment('%s_%s fields:' % (pname, register.name)) |
||||
print() |
||||
|
||||
for field in register.fields: |
||||
mask = ((1 << field.bit_width) - 1) << field.bit_offset |
||||
|
||||
f_pname = periph_rename_for_field.get(pname, pname) |
||||
|
||||
print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
||||
comment(field.description) |
||||
|
||||
if want_ofs: |
||||
print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
||||
|
||||
if want_len: |
||||
print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
||||
|
||||
print() |
||||
|
||||
|
||||
# Print the list |
||||
|
||||
periph_dict = {} |
||||
|
||||
for peripheral in device.peripherals: |
||||
|
||||
periph_name = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
# add to a dict for referencing by name |
||||
periph_dict[periph_name] = peripheral |
||||
|
||||
# ----- |
||||
caption(periph_name) |
||||
comment('Desc: %s' % peripheral.description) |
||||
|
||||
print() |
||||
comment('%s base address:' % periph_name) |
||||
print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
||||
|
||||
|
||||
print() |
||||
comment('%s registers:' % periph_name) |
||||
print() |
||||
|
||||
# Registers |
||||
if periph_name in same_regs_as: |
||||
print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_registers(peripheral) |
||||
|
||||
|
||||
if periph_name in no_print_fields: |
||||
comment('Fields the same as in the first instance.') |
||||
continue |
||||
|
||||
# Fields |
||||
if periph_name in same_regs_as: |
||||
print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_fields(peripheral) |
||||
|
||||
print(' END\n') |
||||
@ -0,0 +1,230 @@ |
||||
|
||||
from cmsis_svd.parser import SVDParser |
||||
import json |
||||
import re |
||||
|
||||
# ------------------------------------ |
||||
|
||||
# ~ $ ls /usr/lib/python3.5/site-packages/cmsis_svd/data/STMicro/ |
||||
# Contents.txt STM32F091x.svd STM32F105xx.svd STM32F303xE.svd STM32F401x.svd STM32F437x.svd STM32L053x.svd STM32L15xxxA.svd |
||||
# License.html STM32F0xx.svd STM32F107xx.svd STM32F303x.svd STM32F40x.svd STM32F439x.svd STM32L062x.svd STM32L1xx.svd |
||||
# STM32F030.svd STM32F100xx.svd STM32F20x.svd STM32F30x.svd STM32F411xx.svd STM32F446x.svd STM32L063x.svd STM32L4x6.svd |
||||
# STM32F031x.svd STM32F101xx.svd STM32F21x.svd STM32F334x.svd STM32F41x.svd STM32F46_79x.svd STM32L100.svd STM32W108.svd |
||||
# STM32F042x.svd STM32F102xx.svd STM32F301x.svd STM32F37x.svd STM32F427x.svd STM32L051x.svd STM32L15xC.svd |
||||
# STM32F072x.svd STM32F103xx.svd STM32F302x.svd STM32F401xE.svd STM32F429x.svd STM32L052x.svd STM32L15xxE.svd |
||||
|
||||
|
||||
svd_name = 'STM32F303xE.svd' |
||||
|
||||
want_ofs = True |
||||
want_len = True |
||||
|
||||
# Do not print poripheral field definitions (same as first instance) |
||||
no_print_fields = [ |
||||
'GPIOB', |
||||
'GPIOC', |
||||
'GPIOD', |
||||
'GPIOE', |
||||
'GPIOF', |
||||
'GPIOG', |
||||
'GPIOH', |
||||
'USART2', |
||||
'USART3', |
||||
'USART4', |
||||
'USART5', |
||||
'SPI2', |
||||
'SPI3', |
||||
'TIM3', |
||||
'DAC2', |
||||
'SPI2', |
||||
'SPI3', |
||||
'ADC2', |
||||
'ADC3', |
||||
'ADC4', |
||||
'ADC34', |
||||
'I2C2', |
||||
'I2C3', |
||||
] |
||||
|
||||
# Rename peripheral when building field definitions |
||||
# Used for multiple instances (build fields only for the first) |
||||
periph_rename_for_field = { |
||||
'GPIOA': 'GPIO', |
||||
'USART1': 'USART', |
||||
'DAC1': 'DAC', |
||||
'SPI1': 'SPI', |
||||
'ADC1': 'ADC', |
||||
'ADC12': 'ADCC', |
||||
'I2C1': 'I2C' |
||||
} |
||||
|
||||
# Same registers as... (points to first instance) |
||||
same_regs_as = { |
||||
'GPIOB': 'GPIOA', |
||||
'GPIOC': 'GPIOA', |
||||
'GPIOD': 'GPIOA', |
||||
'GPIOE': 'GPIOA', |
||||
'GPIOF': 'GPIOA', |
||||
'GPIOG': 'GPIOA', |
||||
'GPIOH': 'GPIOA', |
||||
'USART2': 'USART1', |
||||
'USART3': 'USART1', |
||||
'USART4': 'USART1', |
||||
'USART5': 'USART1', |
||||
'DAC2': 'DAC1', |
||||
'SPI2': 'SPI1', |
||||
'SPI3': 'SPI1', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'I2C2': 'I2C1', |
||||
'I2C3': 'I2C1', |
||||
'ADC34': 'ADC12', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'TIM3': 'TIM2', |
||||
'TIM4': 'TIM2', |
||||
} |
||||
|
||||
# Rename peripheral when generating (bad name in SVD) |
||||
periph_rename = { |
||||
'ADC1_2': 'ADC12', |
||||
'ADC3_4': 'ADC34', |
||||
'Flash': 'FLASH' |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
base_line = "{0:<30} EQU {1:#x}" |
||||
reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
||||
field_line = "{0:<30} EQU {1:#010x}" |
||||
field_ofs_line = "{0:<30} EQU {1:#d}" |
||||
field_len_line = field_ofs_line |
||||
|
||||
def comment_str(x): |
||||
if x is None: |
||||
return '' |
||||
|
||||
return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
def banner(x): |
||||
comment('==== {:=<55}'.format("%s " % x)) |
||||
|
||||
def caption(x): |
||||
print() |
||||
comment('---- {:-<55}'.format("%s " % x)) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
||||
device = parser.get_device() |
||||
|
||||
print() |
||||
banner('%s PERIPHERALS' % device.name) |
||||
comment('') |
||||
comment('CTU Prague, FEL, Department of Measurement') |
||||
comment('') |
||||
comment('-' * 60) |
||||
comment('') |
||||
comment('Generated from "%s"' % svd_name) |
||||
comment('') |
||||
comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
||||
comment(' https://github.com/posborne/cmsis-svd') |
||||
comment('ASM building script (c) Ondrej Hruska, 2016') |
||||
comment('') |
||||
comment('=' * 60) |
||||
print() |
||||
|
||||
|
||||
|
||||
# periph registers |
||||
def print_registers(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
||||
comment(register.description) |
||||
|
||||
|
||||
# periph fields |
||||
def print_fields(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
|
||||
print() |
||||
comment('%s_%s fields:' % (pname, register.name)) |
||||
print() |
||||
|
||||
for field in register.fields: |
||||
mask = ((1 << field.bit_width) - 1) << field.bit_offset |
||||
|
||||
f_pname = periph_rename_for_field.get(pname, pname) |
||||
|
||||
print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
||||
comment(field.description) |
||||
|
||||
if want_ofs: |
||||
print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
||||
|
||||
if want_len: |
||||
print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
||||
|
||||
print() |
||||
|
||||
|
||||
# Print the list |
||||
|
||||
periph_dict = {} |
||||
|
||||
for peripheral in device.peripherals: |
||||
|
||||
periph_name = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
# add to a dict for referencing by name |
||||
periph_dict[periph_name] = peripheral |
||||
|
||||
# ----- |
||||
caption(periph_name) |
||||
comment('Desc: %s' % peripheral.description) |
||||
|
||||
print() |
||||
comment('%s base address:' % periph_name) |
||||
print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
||||
|
||||
|
||||
print() |
||||
comment('%s registers:' % periph_name) |
||||
print() |
||||
|
||||
# Registers |
||||
if periph_name in same_regs_as: |
||||
print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_registers(peripheral) |
||||
|
||||
|
||||
if periph_name in no_print_fields: |
||||
comment('Fields the same as in the first instance.') |
||||
continue |
||||
|
||||
# Fields |
||||
if periph_name in same_regs_as: |
||||
print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_fields(peripheral) |
||||
|
||||
print(' END\n') |
||||
@ -0,0 +1,206 @@ |
||||
|
||||
from cmsis_svd.parser import SVDParser |
||||
import json |
||||
import re |
||||
|
||||
# ------------------------------------ |
||||
|
||||
svd_name = 'STM32F30x.svd' |
||||
|
||||
want_ofs = True |
||||
want_len = True |
||||
|
||||
# Do not print poripheral field definitions (same as first instance) |
||||
no_print_fields = [ |
||||
'GPIOB', |
||||
'GPIOC', |
||||
'GPIOD', |
||||
'GPIOE', |
||||
'GPIOF', |
||||
'GPIOG', |
||||
'USART2', |
||||
'USART3', |
||||
'ADC2', |
||||
'ADC3', |
||||
'ADC4', |
||||
'ADC34', |
||||
'I2C2', |
||||
'I2C3', |
||||
'SPI2', |
||||
'SPI3', |
||||
] |
||||
|
||||
# Same registers as... (points to first instance) |
||||
same_regs_as = { |
||||
'GPIOB': 'GPIOA', |
||||
'GPIOC': 'GPIOA', |
||||
'GPIOD': 'GPIOA', |
||||
'GPIOE': 'GPIOA', |
||||
'GPIOF': 'GPIOA', |
||||
'GPIOG': 'GPIOG', |
||||
'GPIOH': 'GPIOH', |
||||
'USART2': 'USART1', |
||||
'USART3': 'USART1', |
||||
'TIM4': 'TIM3', |
||||
'DAC2': 'DAC1', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'ADC34': 'ADC12', |
||||
'I2C2': 'I2C1', |
||||
'I2C3': 'I2C1', |
||||
'SPI2': 'SPI1', |
||||
'SPI3': 'SPI1', |
||||
} |
||||
|
||||
# Rename peripheral when building field definitions |
||||
# Used for multiple instances (build fields only for the first) |
||||
periph_rename_for_field = { |
||||
'GPIOA': 'GPIO', |
||||
'USART1': 'USART', |
||||
'DAC1': 'DAC', |
||||
'ADC12': 'ADCC', |
||||
'I2C1': 'I2C' |
||||
} |
||||
|
||||
# Rename peripheral when generating (bad name in SVD) |
||||
periph_rename = { |
||||
'ADC1_2': 'ADC12', |
||||
'ADC3_4': 'ADC34', |
||||
'Flash': 'FLASH' |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
base_line = "{0:<30} EQU {1:#x}" |
||||
reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
||||
field_line = "{0:<30} EQU {1:#010x}" |
||||
field_ofs_line = "{0:<30} EQU {1:#d}" |
||||
field_len_line = field_ofs_line |
||||
|
||||
def comment_str(x): |
||||
if x is None: |
||||
return '' |
||||
|
||||
return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
def banner(x): |
||||
comment('==== {:=<55}'.format("%s " % x)) |
||||
|
||||
def caption(x): |
||||
print() |
||||
comment('---- {:-<55}'.format("%s " % x)) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
||||
device = parser.get_device() |
||||
|
||||
print() |
||||
banner('%s PERIPHERALS' % device.name) |
||||
comment('') |
||||
comment('CTU Prague, FEL, Department of Measurement') |
||||
comment('') |
||||
comment('-' * 60) |
||||
comment('') |
||||
comment('Generated from "%s"' % svd_name) |
||||
comment('') |
||||
comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
||||
comment(' https://github.com/posborne/cmsis-svd') |
||||
comment('ASM building script (c) Ondrej Hruska, 2016') |
||||
comment('') |
||||
comment('=' * 60) |
||||
print() |
||||
|
||||
|
||||
|
||||
# periph registers |
||||
def print_registers(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
||||
comment(register.description) |
||||
|
||||
|
||||
# periph fields |
||||
def print_fields(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
|
||||
print() |
||||
comment('%s_%s fields:' % (pname, register.name)) |
||||
print() |
||||
|
||||
for field in register.fields: |
||||
mask = ((1 << field.bit_width) - 1) << field.bit_offset |
||||
|
||||
f_pname = periph_rename_for_field.get(pname, pname) |
||||
|
||||
print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
||||
comment(field.description) |
||||
|
||||
if want_ofs: |
||||
print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
||||
|
||||
if want_len: |
||||
print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
||||
|
||||
print() |
||||
|
||||
|
||||
# Print the list |
||||
|
||||
periph_dict = {} |
||||
|
||||
for peripheral in device.peripherals: |
||||
|
||||
periph_name = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
# add to a dict for referencing by name |
||||
periph_dict[periph_name] = peripheral |
||||
|
||||
# ----- |
||||
caption(periph_name) |
||||
comment('Desc: %s' % peripheral.description) |
||||
|
||||
print() |
||||
comment('%s base address:' % periph_name) |
||||
print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
||||
|
||||
|
||||
print() |
||||
comment('%s registers:' % periph_name) |
||||
print() |
||||
|
||||
# Registers |
||||
if periph_name in same_regs_as: |
||||
print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_registers(peripheral) |
||||
|
||||
|
||||
if periph_name in no_print_fields: |
||||
comment('Fields the same as in the first instance.') |
||||
continue |
||||
|
||||
# Fields |
||||
if periph_name in same_regs_as: |
||||
print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_fields(peripheral) |
||||
|
||||
print(' END\n') |
||||
@ -0,0 +1,207 @@ |
||||
|
||||
from cmsis_svd.parser import SVDParser |
||||
import json |
||||
import re |
||||
|
||||
# ------------------------------------ |
||||
|
||||
svd_name = 'STM32L100.svd' |
||||
|
||||
want_ofs = True |
||||
want_len = True |
||||
|
||||
# Do not print poripheral field definitions (same as first instance) |
||||
no_print_fields = [ |
||||
'GPIOB', |
||||
'GPIOC', |
||||
'GPIOD', |
||||
'GPIOE', |
||||
'GPIOF', |
||||
'GPIOG', |
||||
'USART2', |
||||
'USART3', |
||||
'ADC2', |
||||
'ADC3', |
||||
'ADC4', |
||||
'ADC34', |
||||
'I2C2', |
||||
'I2C3', |
||||
'SPI2', |
||||
'SPI3', |
||||
] |
||||
|
||||
# Same registers as... (points to first instance) |
||||
same_regs_as = { |
||||
'GPIOB': 'GPIOA', |
||||
'GPIOC': 'GPIOA', |
||||
'GPIOD': 'GPIOA', |
||||
'GPIOE': 'GPIOA', |
||||
'GPIOF': 'GPIOA', |
||||
'GPIOG': 'GPIOG', |
||||
'GPIOH': 'GPIOH', |
||||
'USART2': 'USART1', |
||||
'USART3': 'USART1', |
||||
'TIM4': 'TIM3', |
||||
'DAC2': 'DAC1', |
||||
'ADC2': 'ADC1', |
||||
'ADC3': 'ADC1', |
||||
'ADC4': 'ADC1', |
||||
'ADC34': 'ADC12', |
||||
'I2C2': 'I2C1', |
||||
'I2C3': 'I2C1', |
||||
'SPI2': 'SPI1', |
||||
'SPI3': 'SPI1', |
||||
} |
||||
|
||||
# Rename peripheral when building field definitions |
||||
# Used for multiple instances (build fields only for the first) |
||||
periph_rename_for_field = { |
||||
'GPIOA': 'GPIO', |
||||
'USART1': 'USART', |
||||
'DAC1': 'DAC', |
||||
'ADC12': 'ADCC', |
||||
'I2C1': 'I2C', |
||||
'SPI1': 'SPI', |
||||
} |
||||
|
||||
# Rename peripheral when generating (bad name in SVD) |
||||
periph_rename = { |
||||
'ADC1_2': 'ADC12', |
||||
'ADC3_4': 'ADC34', |
||||
'Flash': 'FLASH' |
||||
} |
||||
|
||||
|
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
base_line = "{0:<30} EQU {1:#x}" |
||||
reg_line = "{0:<30} EQU ({1}_BASE + {2:#x})" |
||||
field_line = "{0:<30} EQU {1:#010x}" |
||||
field_ofs_line = "{0:<30} EQU {1:#d}" |
||||
field_len_line = field_ofs_line |
||||
|
||||
def comment_str(x): |
||||
if x is None: |
||||
return '' |
||||
|
||||
return '; %s' % re.sub(r"[\s\n]+", ' ', x.replace('\n',' ')) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
def banner(x): |
||||
comment('==== {:=<55}'.format("%s " % x)) |
||||
|
||||
def caption(x): |
||||
print() |
||||
comment('---- {:-<55}'.format("%s " % x)) |
||||
|
||||
def comment(x): |
||||
print(comment_str(x)) |
||||
|
||||
|
||||
# ------------------------------------ |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', svd_name) |
||||
device = parser.get_device() |
||||
|
||||
print() |
||||
banner('%s PERIPHERALS' % device.name) |
||||
comment('') |
||||
comment('CTU Prague, FEL, Department of Measurement') |
||||
comment('') |
||||
comment('-' * 60) |
||||
comment('') |
||||
comment('Generated from "%s"' % svd_name) |
||||
comment('') |
||||
comment('SVD parsing library (c) Paul Osborne, 2015-2016') |
||||
comment(' https://github.com/posborne/cmsis-svd') |
||||
comment('ASM building script (c) Ondrej Hruska, 2016') |
||||
comment('') |
||||
comment('=' * 60) |
||||
print() |
||||
|
||||
|
||||
|
||||
# periph registers |
||||
def print_registers(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
print(reg_line.format("%s_%s" % (pname, register.name), pname, register.address_offset), end=' ') |
||||
comment(register.description) |
||||
|
||||
|
||||
# periph fields |
||||
def print_fields(peripheral, pname=None): |
||||
if pname is None: |
||||
pname = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
for register in peripheral.registers: |
||||
|
||||
print() |
||||
comment('%s_%s fields:' % (pname, register.name)) |
||||
print() |
||||
|
||||
for field in register.fields: |
||||
mask = ((1 << field.bit_width) - 1) << field.bit_offset |
||||
|
||||
f_pname = periph_rename_for_field.get(pname, pname) |
||||
|
||||
print(field_line.format("%s_%s_%s" % (f_pname, register.name, field.name), mask), end=' ') |
||||
comment(field.description) |
||||
|
||||
if want_ofs: |
||||
print(field_ofs_line.format("%s_%s_%s_ofs" % (f_pname, register.name, field.name), field.bit_offset)) |
||||
|
||||
if want_len: |
||||
print(field_len_line.format("%s_%s_%s_len" % (f_pname, register.name, field.name), field.bit_width)) |
||||
|
||||
print() |
||||
|
||||
|
||||
# Print the list |
||||
|
||||
periph_dict = {} |
||||
|
||||
for peripheral in device.peripherals: |
||||
|
||||
periph_name = periph_rename.get(peripheral.name, peripheral.name) |
||||
|
||||
# add to a dict for referencing by name |
||||
periph_dict[periph_name] = peripheral |
||||
|
||||
# ----- |
||||
caption(periph_name) |
||||
comment('Desc: %s' % peripheral.description) |
||||
|
||||
print() |
||||
comment('%s base address:' % periph_name) |
||||
print(base_line.format("%s_BASE" % periph_name, peripheral.base_address)) |
||||
|
||||
|
||||
print() |
||||
comment('%s registers:' % periph_name) |
||||
print() |
||||
|
||||
# Registers |
||||
if periph_name in same_regs_as: |
||||
print_registers(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_registers(peripheral) |
||||
|
||||
|
||||
if periph_name in no_print_fields: |
||||
comment('Fields the same as in the first instance.') |
||||
continue |
||||
|
||||
# Fields |
||||
if periph_name in same_regs_as: |
||||
print_fields(periph_dict[same_regs_as[periph_name]], pname=periph_name) |
||||
else: |
||||
print_fields(peripheral) |
||||
|
||||
print(' END\n') |
||||
@ -0,0 +1,7 @@ |
||||
import json |
||||
from cmsis_svd.parser import SVDParser |
||||
|
||||
parser = SVDParser.for_packaged_svd('STMicro', 'STM32F042x.svd') |
||||
svd_dict = parser.get_device().to_dict() |
||||
print(json.dumps(svd_dict, sort_keys=True, |
||||
indent=4, separators=(',', ': '))) |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,50 @@ |
||||
;**************************************************************************** |
||||
;* |
||||
;* REGISTERS |
||||
;* |
||||
;**************************************************************************** |
||||
|
||||
SYSTICK_BASE EQU 0xE000E010 |
||||
|
||||
SYSTICK_CR EQU (SYSTICK_BASE + 0x010) ; (R/W) SysTick Control and Status Register |
||||
SYSTICK_RELOAD EQU (SYSTICK_BASE + 0x014) ; (R/W) SysTick Reload Value Register |
||||
SYSTICK_VAL EQU (SYSTICK_BASE + 0x018) ; (R/W) SysTick Current Value Register |
||||
SYSTICK_CALIB EQU (SYSTICK_BASE + 0x01C) ; (R/ ) SysTick Calibration Value Register |
||||
|
||||
|
||||
;**************************************************************************** |
||||
;* |
||||
;* BIT MASKS AND DEFINITIONS |
||||
;* |
||||
;**************************************************************************** |
||||
|
||||
|
||||
;**************** Bit definition for SYSTICK_CR register **************** |
||||
|
||||
SYSTICK_CR_ENABLE EQU 0x00000001 ; Counter enable |
||||
SYSTICK_CR_ENABLE_ofs EQU 0 |
||||
SYSTICK_CR_ENABLE_len EQU 1 |
||||
|
||||
SYSTICK_CR_TICKINT EQU 0x00000002 ; Enable interrupt when counter reaches zero |
||||
SYSTICK_CR_TICKINT_ofs EQU 1 |
||||
SYSTICK_CR_TICKINT_len EQU 1 |
||||
|
||||
SYSTICK_CR_CLKSOURCE EQU 0x00000004 ; Clock source (0 - clock div 8, 1 - core clock) |
||||
SYSTICK_CR_CLKSOURCE_ofs EQU 2 |
||||
SYSTICK_CR_CLKSOURCE_len EQU 1 |
||||
|
||||
SYSTICK_CR_COUNTFLAG EQU 0x00010000 ; Count Flag (only if interrupt is disabled) |
||||
SYSTICK_CR_COUNTFLAG_ofs EQU 16 |
||||
SYSTICK_CR_COUNTFLAG_len EQU 1 |
||||
|
||||
; masks |
||||
SYSTICK_RELOAD_MASK EQU 0x00FFFFFF ; Reload value used when the counter reaches 0 |
||||
SYSTICK_VAL_MASK EQU 0x00FFFFFF ; Current value at the time the register is accessed |
||||
|
||||
|
||||
; systick calib (according to datasheet) |
||||
SYSTICK_CALIB_TENMS EQU 0x00FFFFFF ; Reload value to use for 10ms timing |
||||
SYSTICK_CALIB_SKEW EQU 0x40000000 ; Calibration value is not exactly 10 ms |
||||
SYSTICK_CALIB_NOREF EQU 0x80000000 ; The reference clock is not provided |
||||
|
||||
END |
||||
@ -0,0 +1,27 @@ |
||||
Startup scripts for STM32 |
||||
========================= |
||||
|
||||
All startup scripts are taken from Standard Peripheral Library, or the STM Cube. |
||||
|
||||
The scripts provided here are the "arm" variant, meant for ARM assembler or ARM-CC. |
||||
|
||||
License |
||||
------- |
||||
|
||||
```none |
||||
;******************************************************************************* |
||||
; |
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
||||
; You may not use this file except in compliance with the License. |
||||
; You may obtain a copy of the License at: |
||||
; |
||||
; http://www.st.com/software_license_agreement_liberty_v2 |
||||
; |
||||
; Unless required by applicable law or agreed to in writing, software |
||||
; distributed under the License is distributed on an "AS IS" BASIS, |
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
; See the License for the specific language governing permissions and |
||||
; limitations under the License. |
||||
; |
||||
;******************************************************************************* |
||||
``` |
||||
@ -0,0 +1,244 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f030x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F030x4/STM32F030x6 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler
|
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,252 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f030x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F030x8 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler
|
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,259 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f030xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F030xc/STM32F030xb devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_6_IRQHandler ; USART3, USART4, USART5, USART6
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_6_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler
|
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_6_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,248 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f031x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,246 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f038xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F038xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,289 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f042x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
|
||||
|
||||
|
||||
LDR R0, =__initial_sp ; set stack pointer
|
||||
MSR MSP, R0
|
||||
|
||||
;;Check if boot space corresponds to test memory
|
||||
|
||||
LDR R0,=0x00000004 |
||||
LDR R1, [R0] |
||||
LSRS R1, R1, #24 |
||||
LDR R2,=0x1F |
||||
CMP R1, R2 |
||||
|
||||
BNE ApplicationStart
|
||||
|
||||
;; SYSCFG clock enable
|
||||
|
||||
LDR R0,=0x40021018
|
||||
LDR R1,=0x00000001 |
||||
STR R1, [R0] |
||||
|
||||
;; Set CFGR1 register with flash memory remap at address 0
|
||||
|
||||
LDR R0,=0x40010000
|
||||
LDR R1,=0x00000000 |
||||
STR R1, [R0] |
||||
ApplicationStart |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,261 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f048xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F048xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD VDDIO2_IRQHandler ; VDDIO2 Monitor through EXTI Line 31
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,264 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f051x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
CEC_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,262 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f058xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F058xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
CEC_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,279 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f070x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F070x4/STM32F070x6 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
|
||||
|
||||
|
||||
LDR R0, =__initial_sp ; set stack pointer
|
||||
MSR MSP, R0
|
||||
|
||||
;;Check if boot space corresponds to test memory
|
||||
|
||||
LDR R0,=0x00000004 |
||||
LDR R1, [R0] |
||||
LSRS R1, R1, #24 |
||||
LDR R2,=0x1F |
||||
CMP R1, R2 |
||||
|
||||
BNE ApplicationStart
|
||||
|
||||
;; SYSCFG clock enable
|
||||
|
||||
LDR R0,=0x40021018
|
||||
LDR R1,=0x00000001 |
||||
STR R1, [R0] |
||||
|
||||
;; Set CFGR1 register with flash memory remap at address 0
|
||||
|
||||
LDR R0,=0x40010000
|
||||
LDR R1,=0x00000000 |
||||
STR R1, [R0] |
||||
ApplicationStart |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,263 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f070xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F070x8/STM32F070xB devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_4_IRQHandler ; USART3 & USART4
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_4_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_IRQHandler |
||||
ADC1_IRQHandler
|
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_4_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,268 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f071xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F071x8/STM32F071xB devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_4_IRQHandler ; USART3 & USART4
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_4_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_6_7_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_4_IRQHandler |
||||
CEC_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,271 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f072xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F072x8/STM32F072xB devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_4_IRQHandler ; USART3 & USART4
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_4_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_6_7_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_4_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,271 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f078xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F078xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD VDDIO2_IRQHandler ; VDDIO2 Monitor through EXTI Line 31
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
|
||||
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_4_IRQHandler ; USART3 & USART4
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
DCD USB_IRQHandler ; USB
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_4_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
EXPORT USB_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_3_IRQHandler |
||||
DMA1_Channel4_5_6_7_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_4_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
USB_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,268 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f091xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
|
||||
DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_8_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Ch1_IRQHandler |
||||
DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
||||
DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_8_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,268 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f098xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.2
|
||||
;* Date : 26-June-2015
|
||||
;* Description : STM32F098xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM0 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD VDDIO2_IRQHandler ; VDDIO2 Monitor through EXTI Line 31
|
||||
DCD RTC_IRQHandler ; RTC through EXTI Line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_CRS_IRQHandler ; RCC and CRS
|
||||
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
|
||||
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
|
||||
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
|
||||
DCD TSC_IRQHandler ; TS
|
||||
DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
|
||||
DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
|
||||
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
|
||||
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD I2C1_IRQHandler ; I2C1
|
||||
DCD I2C2_IRQHandler ; I2C2
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
|
||||
DCD CEC_CAN_IRQHandler ; CEC and CAN
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT VDDIO2_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_CRS_IRQHandler [WEAK] |
||||
EXPORT EXTI0_1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_15_IRQHandler [WEAK] |
||||
EXPORT TSC_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK] |
||||
EXPORT ADC1_COMP_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT I2C1_IRQHandler [WEAK] |
||||
EXPORT I2C2_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_8_IRQHandler [WEAK] |
||||
EXPORT CEC_CAN_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
VDDIO2_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_CRS_IRQHandler |
||||
EXTI0_1_IRQHandler |
||||
EXTI2_3_IRQHandler |
||||
EXTI4_15_IRQHandler |
||||
TSC_IRQHandler |
||||
DMA1_Ch1_IRQHandler |
||||
DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
||||
DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler |
||||
ADC1_COMP_IRQHandler |
||||
TIM1_BRK_UP_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
I2C1_IRQHandler |
||||
I2C2_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_8_IRQHandler |
||||
CEC_CAN_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,332 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f100xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F100xB Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD CEC_IRQHandler ; HDMI-CEC
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
CEC_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,363 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f100xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F100xE Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system and also configure the external
|
||||
;* SRAM mounted on STM32100E-EVAL board to be used as data
|
||||
;* memory (optional, to be enabled by user)
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD CEC_IRQHandler ; HDMI CEC
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
EXPORT TIM12_IRQHandler [WEAK] |
||||
EXPORT TIM13_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
CEC_IRQHandler |
||||
TIM12_IRQHandler |
||||
TIM13_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_5_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,295 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f101x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F101x6 Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,305 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f101xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F101xB Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,343 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f101xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F101xE Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT FSMC_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
FSMC_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_5_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,355 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f101xg.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F101xG Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM12_IRQHandler [WEAK] |
||||
EXPORT TIM13_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT FSMC_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
TIM12_IRQHandler |
||||
TIM13_IRQHandler |
||||
TIM14_IRQHandler |
||||
FSMC_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_5_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,302 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f102x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F102x6 Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,312 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f102xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F102xB Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,314 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f103x6.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F103x6 Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN1_TX_IRQHandler |
||||
USB_LP_CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_IRQHandler |
||||
TIM1_UP_IRQHandler |
||||
TIM1_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,324 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f103xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN1_TX_IRQHandler |
||||
USB_LP_CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_IRQHandler |
||||
TIM1_UP_IRQHandler |
||||
TIM1_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,373 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f103xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT TIM8_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM8_UP_IRQHandler [WEAK] |
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK] |
||||
EXPORT FSMC_IRQHandler [WEAK] |
||||
EXPORT SDIO_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN1_TX_IRQHandler |
||||
USB_LP_CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_IRQHandler |
||||
TIM1_UP_IRQHandler |
||||
TIM1_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
TIM8_BRK_IRQHandler |
||||
TIM8_UP_IRQHandler |
||||
TIM8_TRG_COM_IRQHandler |
||||
TIM8_CC_IRQHandler |
||||
ADC3_IRQHandler |
||||
FSMC_IRQHandler |
||||
SDIO_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_5_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,373 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f103xg.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F103xG Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD FSMC_IRQHandler ; FSMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit |
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] |
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] |
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK] |
||||
EXPORT FSMC_IRQHandler [WEAK] |
||||
EXPORT SDIO_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN1_TX_IRQHandler |
||||
USB_LP_CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM9_IRQHandler |
||||
TIM1_UP_TIM10_IRQHandler |
||||
TIM1_TRG_COM_TIM11_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
TIM8_BRK_TIM12_IRQHandler |
||||
TIM8_UP_TIM13_IRQHandler |
||||
TIM8_TRG_COM_TIM14_IRQHandler |
||||
TIM8_CC_IRQHandler |
||||
ADC3_IRQHandler |
||||
FSMC_IRQHandler |
||||
SDIO_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_5_IRQHandler |
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,381 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f105xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F105xC Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C1 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT CAN2_TX_IRQHandler [WEAK] |
||||
EXPORT CAN2_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN2_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN2_SCE_IRQHandler [WEAK] |
||||
EXPORT OTG_FS_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN1_TX_IRQHandler |
||||
CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_IRQHandler |
||||
TIM1_UP_IRQHandler |
||||
TIM1_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
OTG_FS_WKUP_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
CAN2_TX_IRQHandler |
||||
CAN2_RX0_IRQHandler |
||||
CAN2_RX1_IRQHandler |
||||
CAN2_SCE_IRQHandler |
||||
OTG_FS_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,385 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f107xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V4.0.1
|
||||
;* Date : 31-July-2015
|
||||
;* Description : STM32F107xC Devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Configure the clock system
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C1 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_IRQHandler [WEAK] |
||||
EXPORT RTC_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ETH_IRQHandler [WEAK] |
||||
EXPORT ETH_WKUP_IRQHandler [WEAK] |
||||
EXPORT CAN2_TX_IRQHandler [WEAK] |
||||
EXPORT CAN2_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN2_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN2_SCE_IRQHandler [WEAK] |
||||
EXPORT OTG_FS_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_IRQHandler |
||||
RTC_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN1_TX_IRQHandler |
||||
CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_IRQHandler |
||||
TIM1_UP_IRQHandler |
||||
TIM1_TRG_COM_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
OTG_FS_WKUP_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
ETH_IRQHandler |
||||
ETH_WKUP_IRQHandler |
||||
CAN2_TX_IRQHandler |
||||
CAN2_RX0_IRQHandler |
||||
CAN2_RX1_IRQHandler |
||||
CAN2_SCE_IRQHandler |
||||
OTG_FS_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,361 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f301x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F301x6/x8 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT COMP2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT I2C3_EV_IRQHandler [WEAK] |
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
SPI3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
COMP2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
I2C3_EV_IRQHandler |
||||
I2C3_ER_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,367 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f302x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.2.2
|
||||
;* Date : 27-February-2015
|
||||
;* Description : STM32F302x8 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_TS_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT COMP2_IRQHandler [WEAK]
|
||||
EXPORT COMP4_6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_TS_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_CAN1_TX_IRQHandler
|
||||
USB_LP_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBWakeUp_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
COMP2_IRQHandler
|
||||
COMP4_6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
USBWakeUp_RMP_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,393 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f302xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F302xB/xC devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
|
||||
DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_IRQHandler ; COMP1 and COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN_TX_IRQHandler |
||||
USB_LP_CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP1_2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
USBWakeUp_RMP_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,412 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f302xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F302xE devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
|
||||
DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_IRQHandler ; COMP1 and COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD TIM20_BRK_IRQHandler ; TIM20 Break
|
||||
DCD TIM20_UP_IRQHandler ; TIM20 Update
|
||||
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
|
||||
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT FMC_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT I2C3_EV_IRQHandler [WEAK] |
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK] |
||||
EXPORT TIM20_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM20_UP_IRQHandler [WEAK] |
||||
EXPORT TIM20_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM20_CC_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
EXPORT SPI4_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN_TX_IRQHandler |
||||
USB_LP_CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
FMC_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP1_2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
I2C3_EV_IRQHandler |
||||
I2C3_ER_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
USBWakeUp_RMP_IRQHandler |
||||
TIM20_BRK_IRQHandler |
||||
TIM20_UP_IRQHandler |
||||
TIM20_TRG_COM_IRQHandler |
||||
TIM20_CC_IRQHandler |
||||
FPU_IRQHandler |
||||
SPI4_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,363 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f303x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
|
||||
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
|
||||
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
|
||||
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK] |
||||
EXPORT TIM7_DAC2_IRQHandler [WEAK] |
||||
EXPORT COMP2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
TIM6_DAC1_IRQHandler |
||||
TIM7_DAC2_IRQHandler |
||||
COMP2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,399 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f303xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.2.2
|
||||
;* Date : 27-February-2015
|
||||
;* Description : STM32F303xC devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD ADC4_IRQHandler ; ADC4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
|
||||
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_TS_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ADC4_IRQHandler [WEAK]
|
||||
EXPORT COMP1_2_3_IRQHandler [WEAK]
|
||||
EXPORT COMP4_5_6_IRQHandler [WEAK]
|
||||
EXPORT COMP7_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_TS_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USB_HP_CAN1_TX_IRQHandler
|
||||
USB_LP_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBWakeUp_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler |
||||
ADC4_IRQHandler |
||||
COMP1_2_3_IRQHandler
|
||||
COMP4_5_6_IRQHandler
|
||||
COMP7_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
USBWakeUp_RMP_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,418 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f303xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.2.2
|
||||
;* Date : 27-February-2015
|
||||
;* Description : STM32F303xE devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD ADC4_IRQHandler ; ADC4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
|
||||
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD TIM20_BRK_IRQHandler ; TIM20 Break
|
||||
DCD TIM20_UP_IRQHandler ; TIM20 Update
|
||||
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
|
||||
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TS_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN1_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT TIM8_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM8_UP_IRQHandler [WEAK] |
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK] |
||||
EXPORT FMC_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ADC4_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_3_IRQHandler [WEAK] |
||||
EXPORT COMP4_5_6_IRQHandler [WEAK] |
||||
EXPORT COMP7_IRQHandler [WEAK] |
||||
EXPORT I2C3_EV_IRQHandler [WEAK] |
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK] |
||||
EXPORT TIM20_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM20_UP_IRQHandler [WEAK] |
||||
EXPORT TIM20_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM20_CC_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TS_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
USB_HP_CAN1_TX_IRQHandler |
||||
USB_LP_CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler |
||||
CAN1_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
TIM8_BRK_IRQHandler |
||||
TIM8_UP_IRQHandler |
||||
TIM8_TRG_COM_IRQHandler |
||||
TIM8_CC_IRQHandler |
||||
ADC3_IRQHandler |
||||
FMC_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
ADC4_IRQHandler |
||||
COMP1_2_3_IRQHandler |
||||
COMP4_5_6_IRQHandler |
||||
COMP7_IRQHandler |
||||
I2C3_EV_IRQHandler |
||||
I2C3_ER_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
USBWakeUp_RMP_IRQHandler |
||||
TIM20_BRK_IRQHandler |
||||
TIM20_UP_IRQHandler |
||||
TIM20_TRG_COM_IRQHandler |
||||
TIM20_CC_IRQHandler |
||||
FPU_IRQHandler |
||||
SPI4_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,399 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f30x.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.2.2
|
||||
;* Date : 27-February-2015
|
||||
;* Description : STM32F30x devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD ADC4_IRQHandler ; ADC4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
|
||||
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_HP_IRQHandler ; USB High Priority remap
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority remap
|
||||
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_TS_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ADC4_IRQHandler [WEAK]
|
||||
EXPORT COMP1_2_3_IRQHandler [WEAK]
|
||||
EXPORT COMP4_5_6_IRQHandler [WEAK]
|
||||
EXPORT COMP7_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_TS_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USB_HP_CAN1_TX_IRQHandler
|
||||
USB_LP_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBWakeUp_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler |
||||
ADC4_IRQHandler |
||||
COMP1_2_3_IRQHandler
|
||||
COMP4_5_6_IRQHandler
|
||||
COMP7_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
USBWakeUp_RMP_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,359 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f318xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F318xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT COMP2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT I2C3_EV_IRQHandler [WEAK] |
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
SPI3_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
COMP2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
I2C3_EV_IRQHandler |
||||
I2C3_ER_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,361 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f328xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F328xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
|
||||
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
|
||||
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
|
||||
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK] |
||||
EXPORT TIM7_DAC2_IRQHandler [WEAK] |
||||
EXPORT COMP2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
TIM6_DAC1_IRQHandler |
||||
TIM7_DAC2_IRQHandler |
||||
COMP2_IRQHandler |
||||
COMP4_6_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,368 @@ |
||||
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f334x8.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V1.2.2
|
||||
;* Date : 27-February-2015
|
||||
;* Description : STM32F334 devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
; You may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at:
|
||||
;
|
||||
; http://www.st.com/software_license_agreement_liberty_v2
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
|
||||
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
|
||||
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
|
||||
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP2_IRQHandler ; COMP2
|
||||
DCD COMP4_6_IRQHandler ; COMP4, COMP6
|
||||
DCD 0 ; Reserved
|
||||
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
|
||||
DCD HRTIM1_TIMA_IRQHandler ; Reserved
|
||||
DCD HRTIM1_TIMB_IRQHandler ; Reserved
|
||||
DCD HRTIM1_TIMC_IRQHandler ; Reserved
|
||||
DCD HRTIM1_TIMD_IRQHandler ; Reserved
|
||||
DCD HRTIM1_TIME_IRQHandler ; Reserved
|
||||
DCD HRTIM1_FLT_IRQHandler ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_TS_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK] |
||||
EXPORT TIM7_DAC2_IRQHandler [WEAK] |
||||
EXPORT COMP2_IRQHandler [WEAK] |
||||
EXPORT COMP4_6_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_Master_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_TIMA_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
|
||||
EXPORT HRTIM1_TIMC_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_TIMD_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_TIME_IRQHandler [WEAK] |
||||
EXPORT HRTIM1_FLT_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_TS_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
CAN1_TX_IRQHandler |
||||
CAN1_RX0_IRQHandler |
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM15_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler |
||||
TIM6_DAC1_IRQHandler |
||||
TIM7_DAC2_IRQHandler |
||||
COMP2_IRQHandler |
||||
COMP4_6_IRQHandler
|
||||
HRTIM1_Master_IRQHandler |
||||
HRTIM1_TIMA_IRQHandler |
||||
HRTIM1_TIMB_IRQHandler |
||||
HRTIM1_TIMC_IRQHandler |
||||
HRTIM1_TIMD_IRQHandler |
||||
HRTIM1_TIME_IRQHandler |
||||
HRTIM1_FLT_IRQHandler |
||||
FPU_IRQHandler
|
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,400 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f358xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F358xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD ADC4_IRQHandler ; ADC4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
|
||||
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM8_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM8_UP_IRQHandler [WEAK] |
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ADC4_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_3_IRQHandler [WEAK] |
||||
EXPORT COMP4_5_6_IRQHandler [WEAK] |
||||
EXPORT COMP7_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
TIM8_BRK_IRQHandler |
||||
TIM8_UP_IRQHandler |
||||
TIM8_TRG_COM_IRQHandler |
||||
TIM8_CC_IRQHandler |
||||
ADC3_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
ADC4_IRQHandler |
||||
COMP1_2_3_IRQHandler |
||||
COMP4_5_6_IRQHandler |
||||
COMP7_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,405 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f373xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F373xB/xC devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD SDADC1_IRQHandler ; SDADC1
|
||||
DCD SDADC2_IRQHandler ; SDADC2
|
||||
DCD SDADC3_IRQHandler ; SDADC3
|
||||
DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM19_IRQHandler ; TIM19
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM18_DAC2_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
EXPORT TIM12_IRQHandler [WEAK] |
||||
EXPORT TIM13_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT SDADC1_IRQHandler [WEAK] |
||||
EXPORT SDADC2_IRQHandler [WEAK] |
||||
EXPORT SDADC3_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT USBWakeUp_IRQHandler [WEAK] |
||||
EXPORT TIM19_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
TIM18_DAC2_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
CEC_IRQHandler |
||||
TIM12_IRQHandler |
||||
TIM13_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
TIM6_DAC1_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
SDADC1_IRQHandler |
||||
SDADC2_IRQHandler |
||||
SDADC3_IRQHandler |
||||
COMP1_2_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
USBWakeUp_IRQHandler |
||||
TIM19_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,397 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f378xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F378xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM15_IRQHandler ; TIM15
|
||||
DCD TIM16_IRQHandler ; TIM16
|
||||
DCD TIM17_IRQHandler ; TIM17
|
||||
DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
DCD TIM12_IRQHandler ; TIM12
|
||||
DCD TIM13_IRQHandler ; TIM13
|
||||
DCD TIM14_IRQHandler ; TIM14
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD SDADC1_IRQHandler ; SDADC1
|
||||
DCD SDADC2_IRQHandler ; SDADC2
|
||||
DCD SDADC3_IRQHandler ; SDADC3
|
||||
DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM19_IRQHandler ; TIM19
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM18_DAC2_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT CEC_IRQHandler [WEAK] |
||||
EXPORT TIM12_IRQHandler [WEAK] |
||||
EXPORT TIM13_IRQHandler [WEAK] |
||||
EXPORT TIM14_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC1_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT SDADC1_IRQHandler [WEAK] |
||||
EXPORT SDADC2_IRQHandler [WEAK] |
||||
EXPORT SDADC3_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_IRQHandler [WEAK] |
||||
EXPORT TIM19_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
|
||||
|
||||
WWDG_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM15_IRQHandler |
||||
TIM16_IRQHandler |
||||
TIM17_IRQHandler |
||||
TIM18_DAC2_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
CEC_IRQHandler |
||||
TIM12_IRQHandler |
||||
TIM13_IRQHandler |
||||
TIM14_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
TIM6_DAC1_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
SDADC1_IRQHandler |
||||
SDADC2_IRQHandler |
||||
SDADC3_IRQHandler |
||||
COMP1_2_IRQHandler |
||||
TIM19_IRQHandler |
||||
FPU_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,419 @@ |
||||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f398xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : $VERSION$
|
||||
;* Date : 12-Sept-2014
|
||||
;* Description : STM32F398xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD 0 ; Reserved
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
|
||||
DCD CAN_TX_IRQHandler ; CAN TX
|
||||
DCD CAN_RX0_IRQHandler ; CAN RX0
|
||||
DCD CAN_RX1_IRQHandler ; CAN RX1
|
||||
DCD CAN_SCE_IRQHandler ; CAN SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD ADC4_IRQHandler ; ADC4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
|
||||
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM20_BRK_IRQHandler ; TIM20 Break
|
||||
DCD TIM20_UP_IRQHandler ; TIM20 Update
|
||||
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
|
||||
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT SystemInit |
||||
IMPORT __main |
||||
|
||||
LDR R0, =SystemInit |
||||
BLX R0 |
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_TSC_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_2_IRQHandler [WEAK] |
||||
EXPORT CAN_TX_IRQHandler [WEAK] |
||||
EXPORT CAN_RX0_IRQHandler [WEAK] |
||||
EXPORT CAN_RX1_IRQHandler [WEAK] |
||||
EXPORT CAN_SCE_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
||||
EXPORT TIM1_CC_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT TIM8_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM8_UP_IRQHandler [WEAK] |
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM8_CC_IRQHandler [WEAK] |
||||
EXPORT ADC3_IRQHandler [WEAK] |
||||
EXPORT FMC_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT TIM6_DAC_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT ADC4_IRQHandler [WEAK] |
||||
EXPORT COMP1_2_3_IRQHandler [WEAK] |
||||
EXPORT COMP4_5_6_IRQHandler [WEAK] |
||||
EXPORT COMP7_IRQHandler [WEAK] |
||||
EXPORT I2C3_EV_IRQHandler [WEAK] |
||||
EXPORT I2C3_ER_IRQHandler [WEAK] |
||||
EXPORT TIM20_BRK_IRQHandler [WEAK] |
||||
EXPORT TIM20_UP_IRQHandler [WEAK] |
||||
EXPORT TIM20_TRG_COM_IRQHandler [WEAK] |
||||
EXPORT TIM20_CC_IRQHandler [WEAK] |
||||
EXPORT FPU_IRQHandler [WEAK] |
||||
EXPORT SPI4_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
TAMP_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_TSC_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_2_IRQHandler |
||||
CAN_TX_IRQHandler |
||||
CAN_RX0_IRQHandler |
||||
CAN_RX1_IRQHandler |
||||
CAN_SCE_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM1_BRK_TIM15_IRQHandler |
||||
TIM1_UP_TIM16_IRQHandler |
||||
TIM1_TRG_COM_TIM17_IRQHandler |
||||
TIM1_CC_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
TIM8_BRK_IRQHandler |
||||
TIM8_UP_IRQHandler |
||||
TIM8_TRG_COM_IRQHandler |
||||
TIM8_CC_IRQHandler |
||||
ADC3_IRQHandler |
||||
FMC_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
TIM6_DAC_IRQHandler |
||||
TIM7_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
ADC4_IRQHandler |
||||
COMP1_2_3_IRQHandler |
||||
COMP4_5_6_IRQHandler |
||||
COMP7_IRQHandler |
||||
I2C3_EV_IRQHandler |
||||
I2C3_ER_IRQHandler |
||||
TIM20_BRK_IRQHandler |
||||
TIM20_UP_IRQHandler |
||||
TIM20_TRG_COM_IRQHandler |
||||
TIM20_CC_IRQHandler |
||||
FPU_IRQHandler |
||||
SPI4_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB |
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,332 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l100xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L100XB Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,332 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l100xba.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L100XBA Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,358 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l100xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L100XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,330 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XB Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,330 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xba.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XBA Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,358 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,358 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xca.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,364 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xd.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XD Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT SDIO_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
SDIO_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,362 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xdx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XD-X Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,362 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L151XE Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,332 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xb.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XB Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,332 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xba.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XBA Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,359 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,360 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xca.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XCA Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,366 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xd.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XD Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT SDIO_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
SDIO_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,364 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xdx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XD-X Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,364 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L152XE Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD 0 ; Reserved
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,362 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l162xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L162XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD AES_IRQHandler ; AES
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT AES_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
AES_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,362 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l162xca.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L162XCA Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD AES_IRQHandler ; AES
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT AES_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
AES_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,368 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l162xd.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L162XD Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD AES_IRQHandler ; AES
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT SDIO_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK] |
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT AES_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
SDIO_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
AES_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,366 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l162xdx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L162XD-X Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD AES_IRQHandler ; AES
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT AES_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
AES_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@ -0,0 +1,366 @@ |
||||
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l162xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.2
|
||||
;* Date : 09-October-2015
|
||||
;* Description : STM32L162XE Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Configure the system clock
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2015 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400 |
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3 |
||||
Stack_Mem SPACE Stack_Size |
||||
__initial_sp |
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200 |
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
||||
__heap_base |
||||
Heap_Mem SPACE Heap_Size |
||||
__heap_limit |
||||
|
||||
PRESERVE8 |
||||
THUMB |
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY |
||||
EXPORT __Vectors |
||||
EXPORT __Vectors_End |
||||
EXPORT __Vectors_Size |
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_IRQHandler ; ADC1
|
||||
DCD USB_HP_IRQHandler ; USB High Priority
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority
|
||||
DCD DAC_IRQHandler ; DAC
|
||||
DCD COMP_IRQHandler ; COMP through EXTI Line
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD LCD_IRQHandler ; LCD
|
||||
DCD TIM9_IRQHandler ; TIM9
|
||||
DCD TIM10_IRQHandler ; TIM10
|
||||
DCD TIM11_IRQHandler ; TIM11
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD 0 ; Reserved
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
|
||||
DCD AES_IRQHandler ; AES
|
||||
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
|
||||
|
||||
__Vectors_End |
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors |
||||
|
||||
AREA |.text|, CODE, READONLY |
||||
|
||||
; Reset handler routine
|
||||
Reset_Handler PROC |
||||
EXPORT Reset_Handler [WEAK] |
||||
IMPORT __main |
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit |
||||
BLX R0
|
||||
LDR R0, =__main |
||||
BX R0 |
||||
ENDP |
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC |
||||
EXPORT NMI_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
HardFault_Handler\ |
||||
PROC |
||||
EXPORT HardFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
MemManage_Handler\ |
||||
PROC |
||||
EXPORT MemManage_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
BusFault_Handler\ |
||||
PROC |
||||
EXPORT BusFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
UsageFault_Handler\ |
||||
PROC |
||||
EXPORT UsageFault_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SVC_Handler PROC |
||||
EXPORT SVC_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
DebugMon_Handler\ |
||||
PROC |
||||
EXPORT DebugMon_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
PendSV_Handler PROC |
||||
EXPORT PendSV_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
SysTick_Handler PROC |
||||
EXPORT SysTick_Handler [WEAK] |
||||
B . |
||||
ENDP |
||||
|
||||
Default_Handler PROC |
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK] |
||||
EXPORT PVD_IRQHandler [WEAK] |
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK] |
||||
EXPORT RTC_WKUP_IRQHandler [WEAK] |
||||
EXPORT FLASH_IRQHandler [WEAK] |
||||
EXPORT RCC_IRQHandler [WEAK] |
||||
EXPORT EXTI0_IRQHandler [WEAK] |
||||
EXPORT EXTI1_IRQHandler [WEAK] |
||||
EXPORT EXTI2_IRQHandler [WEAK] |
||||
EXPORT EXTI3_IRQHandler [WEAK] |
||||
EXPORT EXTI4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK] |
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK] |
||||
EXPORT ADC1_IRQHandler [WEAK] |
||||
EXPORT USB_HP_IRQHandler [WEAK] |
||||
EXPORT USB_LP_IRQHandler [WEAK] |
||||
EXPORT DAC_IRQHandler [WEAK] |
||||
EXPORT COMP_IRQHandler [WEAK] |
||||
EXPORT EXTI9_5_IRQHandler [WEAK] |
||||
EXPORT LCD_IRQHandler [WEAK] |
||||
EXPORT TIM9_IRQHandler [WEAK] |
||||
EXPORT TIM10_IRQHandler [WEAK] |
||||
EXPORT TIM11_IRQHandler [WEAK] |
||||
EXPORT TIM2_IRQHandler [WEAK] |
||||
EXPORT TIM3_IRQHandler [WEAK] |
||||
EXPORT TIM4_IRQHandler [WEAK] |
||||
EXPORT I2C1_EV_IRQHandler [WEAK] |
||||
EXPORT I2C1_ER_IRQHandler [WEAK] |
||||
EXPORT I2C2_EV_IRQHandler [WEAK] |
||||
EXPORT I2C2_ER_IRQHandler [WEAK] |
||||
EXPORT SPI1_IRQHandler [WEAK] |
||||
EXPORT SPI2_IRQHandler [WEAK] |
||||
EXPORT USART1_IRQHandler [WEAK] |
||||
EXPORT USART2_IRQHandler [WEAK] |
||||
EXPORT USART3_IRQHandler [WEAK] |
||||
EXPORT EXTI15_10_IRQHandler [WEAK] |
||||
EXPORT RTC_Alarm_IRQHandler [WEAK] |
||||
EXPORT USB_FS_WKUP_IRQHandler [WEAK] |
||||
EXPORT TIM6_IRQHandler [WEAK] |
||||
EXPORT TIM7_IRQHandler [WEAK] |
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK] |
||||
EXPORT UART4_IRQHandler [WEAK] |
||||
EXPORT UART5_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK] |
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK] |
||||
EXPORT AES_IRQHandler [WEAK] |
||||
EXPORT COMP_ACQ_IRQHandler [WEAK] |
||||
|
||||
WWDG_IRQHandler |
||||
PVD_IRQHandler |
||||
TAMPER_STAMP_IRQHandler |
||||
RTC_WKUP_IRQHandler |
||||
FLASH_IRQHandler |
||||
RCC_IRQHandler |
||||
EXTI0_IRQHandler |
||||
EXTI1_IRQHandler |
||||
EXTI2_IRQHandler |
||||
EXTI3_IRQHandler |
||||
EXTI4_IRQHandler |
||||
DMA1_Channel1_IRQHandler |
||||
DMA1_Channel2_IRQHandler |
||||
DMA1_Channel3_IRQHandler |
||||
DMA1_Channel4_IRQHandler |
||||
DMA1_Channel5_IRQHandler |
||||
DMA1_Channel6_IRQHandler |
||||
DMA1_Channel7_IRQHandler |
||||
ADC1_IRQHandler |
||||
USB_HP_IRQHandler |
||||
USB_LP_IRQHandler |
||||
DAC_IRQHandler |
||||
COMP_IRQHandler |
||||
EXTI9_5_IRQHandler |
||||
LCD_IRQHandler |
||||
TIM9_IRQHandler |
||||
TIM10_IRQHandler |
||||
TIM11_IRQHandler |
||||
TIM2_IRQHandler |
||||
TIM3_IRQHandler |
||||
TIM4_IRQHandler |
||||
I2C1_EV_IRQHandler |
||||
I2C1_ER_IRQHandler |
||||
I2C2_EV_IRQHandler |
||||
I2C2_ER_IRQHandler |
||||
SPI1_IRQHandler |
||||
SPI2_IRQHandler |
||||
USART1_IRQHandler |
||||
USART2_IRQHandler |
||||
USART3_IRQHandler |
||||
EXTI15_10_IRQHandler |
||||
RTC_Alarm_IRQHandler |
||||
USB_FS_WKUP_IRQHandler |
||||
TIM6_IRQHandler |
||||
TIM7_IRQHandler |
||||
TIM5_IRQHandler |
||||
SPI3_IRQHandler |
||||
UART4_IRQHandler |
||||
UART5_IRQHandler |
||||
DMA2_Channel1_IRQHandler |
||||
DMA2_Channel2_IRQHandler |
||||
DMA2_Channel3_IRQHandler |
||||
DMA2_Channel4_IRQHandler |
||||
DMA2_Channel5_IRQHandler |
||||
AES_IRQHandler |
||||
COMP_ACQ_IRQHandler |
||||
|
||||
B . |
||||
|
||||
ENDP |
||||
|
||||
ALIGN |
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp |
||||
EXPORT __heap_base |
||||
EXPORT __heap_limit |
||||
|
||||
ELSE |
||||
|
||||
IMPORT __use_two_region_memory |
||||
EXPORT __user_initial_stackheap |
||||
|
||||
__user_initial_stackheap |
||||
|
||||
LDR R0, = Heap_Mem |
||||
LDR R1, =(Stack_Mem + Stack_Size) |
||||
LDR R2, = (Heap_Mem + Heap_Size) |
||||
LDR R3, = Stack_Mem |
||||
BX LR |
||||
|
||||
ALIGN |
||||
|
||||
ENDIF |
||||
|
||||
END |
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
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Reference in new issue