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spd-lorabees/build/stm32l0xx_hal_cortex.lst

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ARM GAS /tmp/ccd4VzkJ.s page 1
1 .cpu cortex-m0plus
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 0
10 .eabi_attribute 18, 4
11 .file "stm32l0xx_hal_cortex.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
16 .align 1
17 .global HAL_NVIC_SetPriority
18 .syntax unified
19 .code 16
20 .thumb_func
21 .fpu softvfp
23 HAL_NVIC_SetPriority:
24 .LFB39:
25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c"
1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ******************************************************************************
3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @file stm32l0xx_hal_cortex.c
4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @author MCD Application Team
5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief CORTEX HAL module driver.
6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This file provides firmware functions to manage the following
7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * functionalities of the CORTEX:
8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + Initialization and de-initialization functions
9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * + Peripheral Control functions
10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim
12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### How to use this driver #####
14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver ***
18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ===========================================================
19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This section provide functions allowing to configure the NVIC interrupts (IRQ).
21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** The Cortex-M0+ exceptions are managed by CMSIS functions.
22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Enable and Configure the priority of the selected IRQ Channels.
23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** The priority can be 0..3.
24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** -@- Lower priority values gives higher priority.
26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** -@- Priority Order:
27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#@) Lowest priority.
28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#@) Lowest hardware priority (IRQn position).
29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
ARM GAS /tmp/ccd4VzkJ.s page 2
34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver ***
36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ========================================================
37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Setup SysTick Timer for time base
39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** is a CMSIS function that:
42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter.
43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x03).
44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Resets the SysTick Counter register.
45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Enables the SysTick Interrupt.
47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Starts the SysTick Counter.
48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined
52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** inside the stm32l0xx_hal_cortex.c file.
53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the
55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct
57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula:
59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF
63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim
65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ******************************************************************************
66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @attention
67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * Redistribution and use in source and binary forms, with or without modification,
71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * are permitted provided that the following conditions are met:
72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 1. Redistributions of source code must retain the above copyright notice,
73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * this list of conditions and the following disclaimer.
74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 2. Redistributions in binary form must reproduce the above copyright notice,
75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * this list of conditions and the following disclaimer in the documentation
76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * and/or other materials provided with the distribution.
77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors
78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * may be used to endorse or promote products derived from this software
79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * without specific prior written permission.
80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ARM GAS /tmp/ccd4VzkJ.s page 3
91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ******************************************************************************
93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/
96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #include "stm32l0xx_hal.h"
97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup STM32L0xx_HAL_Driver
99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{
100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED
103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX
105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief CORTEX HAL module driver
106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{
107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/
110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/
111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/
112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/
113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/
114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/
115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions
117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{
118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initialization and Configuration functions
123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim
125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### Initialization and de-initialization functions #####
127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts
130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** Systick functionalities
131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim
133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{
134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Sets the priority of an interrupt.
138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number .
139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param PreemptPriority: The pre-emption priority for the IRQn channel.
142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be a value between 0 and 3.
143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * A lower priority value indicates a higher priority
144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param SubPriority: The subpriority level for the IRQ channel.
145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * no subpriority supported in Cortex M0+ based products.
147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
ARM GAS /tmp/ccd4VzkJ.s page 4
148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
26 .loc 1 150 0
27 .cfi_startproc
28 @ args = 0, pretend = 0, frame = 0
29 @ frame_needed = 0, uses_anonymous_args = 0
30 .LVL0:
31 0000 70B5 push {r4, r5, r6, lr}
32 .LCFI0:
33 .cfi_def_cfa_offset 16
34 .cfi_offset 4, -16
35 .cfi_offset 5, -12
36 .cfi_offset 6, -8
37 .cfi_offset 14, -4
38 .LVL1:
39 .LBB26:
40 .LBB27:
41 .file 2 "Drivers/CMSIS/Include/core_cm0plus.h"
1:Drivers/CMSIS/Include/core_cm0plus.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/core_cm0plus.h **** * @file core_cm0plus.h
3:Drivers/CMSIS/Include/core_cm0plus.h **** * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4:Drivers/CMSIS/Include/core_cm0plus.h **** * @version V4.30
5:Drivers/CMSIS/Include/core_cm0plus.h **** * @date 20. October 2015
6:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/core_cm0plus.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
8:Drivers/CMSIS/Include/core_cm0plus.h ****
9:Drivers/CMSIS/Include/core_cm0plus.h **** All rights reserved.
10:Drivers/CMSIS/Include/core_cm0plus.h **** Redistribution and use in source and binary forms, with or without
11:Drivers/CMSIS/Include/core_cm0plus.h **** modification, are permitted provided that the following conditions are met:
12:Drivers/CMSIS/Include/core_cm0plus.h **** - Redistributions of source code must retain the above copyright
13:Drivers/CMSIS/Include/core_cm0plus.h **** notice, this list of conditions and the following disclaimer.
14:Drivers/CMSIS/Include/core_cm0plus.h **** - Redistributions in binary form must reproduce the above copyright
15:Drivers/CMSIS/Include/core_cm0plus.h **** notice, this list of conditions and the following disclaimer in the
16:Drivers/CMSIS/Include/core_cm0plus.h **** documentation and/or other materials provided with the distribution.
17:Drivers/CMSIS/Include/core_cm0plus.h **** - Neither the name of ARM nor the names of its contributors may be used
18:Drivers/CMSIS/Include/core_cm0plus.h **** to endorse or promote products derived from this software without
19:Drivers/CMSIS/Include/core_cm0plus.h **** specific prior written permission.
20:Drivers/CMSIS/Include/core_cm0plus.h **** *
21:Drivers/CMSIS/Include/core_cm0plus.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22:Drivers/CMSIS/Include/core_cm0plus.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23:Drivers/CMSIS/Include/core_cm0plus.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24:Drivers/CMSIS/Include/core_cm0plus.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25:Drivers/CMSIS/Include/core_cm0plus.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26:Drivers/CMSIS/Include/core_cm0plus.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27:Drivers/CMSIS/Include/core_cm0plus.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28:Drivers/CMSIS/Include/core_cm0plus.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29:Drivers/CMSIS/Include/core_cm0plus.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30:Drivers/CMSIS/Include/core_cm0plus.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31:Drivers/CMSIS/Include/core_cm0plus.h **** POSSIBILITY OF SUCH DAMAGE.
32:Drivers/CMSIS/Include/core_cm0plus.h **** ---------------------------------------------------------------------------*/
33:Drivers/CMSIS/Include/core_cm0plus.h ****
34:Drivers/CMSIS/Include/core_cm0plus.h ****
35:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __ICCARM__ )
36:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma system_include /* treat file as system include file for MISRA check */
37:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma clang system_header /* treat file as system include file */
ARM GAS /tmp/ccd4VzkJ.s page 5
39:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
40:Drivers/CMSIS/Include/core_cm0plus.h ****
41:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_GENERIC
42:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_GENERIC
43:Drivers/CMSIS/Include/core_cm0plus.h ****
44:Drivers/CMSIS/Include/core_cm0plus.h **** #include <stdint.h>
45:Drivers/CMSIS/Include/core_cm0plus.h ****
46:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
47:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" {
48:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
49:Drivers/CMSIS/Include/core_cm0plus.h ****
50:Drivers/CMSIS/Include/core_cm0plus.h **** /**
51:Drivers/CMSIS/Include/core_cm0plus.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52:Drivers/CMSIS/Include/core_cm0plus.h **** CMSIS violates the following MISRA-C:2004 rules:
53:Drivers/CMSIS/Include/core_cm0plus.h ****
54:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 8.5, object/function definition in header file.<br>
55:Drivers/CMSIS/Include/core_cm0plus.h **** Function definitions in header files are used to allow 'inlining'.
56:Drivers/CMSIS/Include/core_cm0plus.h ****
57:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58:Drivers/CMSIS/Include/core_cm0plus.h **** Unions are used for effective representation of core registers.
59:Drivers/CMSIS/Include/core_cm0plus.h ****
60:Drivers/CMSIS/Include/core_cm0plus.h **** \li Advisory Rule 19.7, Function-like macro defined.<br>
61:Drivers/CMSIS/Include/core_cm0plus.h **** Function-like macros are used to allow more efficient code.
62:Drivers/CMSIS/Include/core_cm0plus.h **** */
63:Drivers/CMSIS/Include/core_cm0plus.h ****
64:Drivers/CMSIS/Include/core_cm0plus.h ****
65:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
66:Drivers/CMSIS/Include/core_cm0plus.h **** * CMSIS definitions
67:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/
68:Drivers/CMSIS/Include/core_cm0plus.h **** /**
69:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup Cortex-M0+
70:Drivers/CMSIS/Include/core_cm0plus.h **** @{
71:Drivers/CMSIS/Include/core_cm0plus.h **** */
72:Drivers/CMSIS/Include/core_cm0plus.h ****
73:Drivers/CMSIS/Include/core_cm0plus.h **** /* CMSIS CM0+ definitions */
74:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS H
75:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS H
76:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
77:Drivers/CMSIS/Include/core_cm0plus.h **** __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL versi
78:Drivers/CMSIS/Include/core_cm0plus.h ****
79:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORTEX_M (0x00U) /*!< Cortex-M Core *
80:Drivers/CMSIS/Include/core_cm0plus.h ****
81:Drivers/CMSIS/Include/core_cm0plus.h ****
82:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM )
83:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for ARM Comp
84:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE __inline /*!< inline keyword for ARM C
85:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static __inline
86:Drivers/CMSIS/Include/core_cm0plus.h ****
87:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for ARM Comp
89:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE __inline /*!< inline keyword for ARM C
90:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static __inline
91:Drivers/CMSIS/Include/core_cm0plus.h ****
92:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ )
93:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for GNU Comp
94:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for GNU C
95:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline
ARM GAS /tmp/ccd4VzkJ.s page 6
96:Drivers/CMSIS/Include/core_cm0plus.h ****
97:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ )
98:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for IAR Comp
99:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for IAR C
100:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline
101:Drivers/CMSIS/Include/core_cm0plus.h ****
102:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TMS470__ )
103:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for TI CCS C
104:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline
105:Drivers/CMSIS/Include/core_cm0plus.h ****
106:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ )
107:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM __asm /*!< asm keyword for TASKING
108:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for TASKI
109:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline
110:Drivers/CMSIS/Include/core_cm0plus.h ****
111:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ )
112:Drivers/CMSIS/Include/core_cm0plus.h **** #define __packed
113:Drivers/CMSIS/Include/core_cm0plus.h **** #define __ASM _asm /*!< asm keyword for COSMIC Co
114:Drivers/CMSIS/Include/core_cm0plus.h **** #define __INLINE inline /*!< inline keyword for COSMIC
115:Drivers/CMSIS/Include/core_cm0plus.h **** #define __STATIC_INLINE static inline
116:Drivers/CMSIS/Include/core_cm0plus.h ****
117:Drivers/CMSIS/Include/core_cm0plus.h **** #else
118:Drivers/CMSIS/Include/core_cm0plus.h **** #error Unknown compiler
119:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
120:Drivers/CMSIS/Include/core_cm0plus.h ****
121:Drivers/CMSIS/Include/core_cm0plus.h **** /** __FPU_USED indicates whether an FPU is used or not.
122:Drivers/CMSIS/Include/core_cm0plus.h **** This core does not support an FPU at all
123:Drivers/CMSIS/Include/core_cm0plus.h **** */
124:Drivers/CMSIS/Include/core_cm0plus.h **** #define __FPU_USED 0U
125:Drivers/CMSIS/Include/core_cm0plus.h ****
126:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM )
127:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TARGET_FPU_VFP
128:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
130:Drivers/CMSIS/Include/core_cm0plus.h ****
131:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARM_PCS_VFP
133:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
135:Drivers/CMSIS/Include/core_cm0plus.h ****
136:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ )
137:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
140:Drivers/CMSIS/Include/core_cm0plus.h ****
141:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ )
142:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARMVFP__
143:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
145:Drivers/CMSIS/Include/core_cm0plus.h ****
146:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TMS470__ )
147:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TI_VFP_SUPPORT__
148:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
150:Drivers/CMSIS/Include/core_cm0plus.h ****
151:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ )
152:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __FPU_VFP__
ARM GAS /tmp/ccd4VzkJ.s page 7
153:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
155:Drivers/CMSIS/Include/core_cm0plus.h ****
156:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ )
157:Drivers/CMSIS/Include/core_cm0plus.h **** #if ( __CSMC__ & 0x400U)
158:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
160:Drivers/CMSIS/Include/core_cm0plus.h ****
161:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
162:Drivers/CMSIS/Include/core_cm0plus.h ****
163:Drivers/CMSIS/Include/core_cm0plus.h **** #include "core_cmInstr.h" /* Core Instruction Access */
164:Drivers/CMSIS/Include/core_cm0plus.h **** #include "core_cmFunc.h" /* Core Function Access */
165:Drivers/CMSIS/Include/core_cm0plus.h ****
166:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
167:Drivers/CMSIS/Include/core_cm0plus.h **** }
168:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
169:Drivers/CMSIS/Include/core_cm0plus.h ****
170:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* __CORE_CM0PLUS_H_GENERIC */
171:Drivers/CMSIS/Include/core_cm0plus.h ****
172:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CMSIS_GENERIC
173:Drivers/CMSIS/Include/core_cm0plus.h ****
174:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_DEPENDANT
175:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_DEPENDANT
176:Drivers/CMSIS/Include/core_cm0plus.h ****
177:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
178:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" {
179:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
180:Drivers/CMSIS/Include/core_cm0plus.h ****
181:Drivers/CMSIS/Include/core_cm0plus.h **** /* check device defines and use defaults */
182:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __CHECK_DEVICE_DEFINES
183:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CM0PLUS_REV
184:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_REV 0x0000U
185:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__CM0PLUS_REV not defined in device header file; using default!"
186:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
187:Drivers/CMSIS/Include/core_cm0plus.h ****
188:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __MPU_PRESENT
189:Drivers/CMSIS/Include/core_cm0plus.h **** #define __MPU_PRESENT 0U
190:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__MPU_PRESENT not defined in device header file; using default!"
191:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
192:Drivers/CMSIS/Include/core_cm0plus.h ****
193:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __VTOR_PRESENT
194:Drivers/CMSIS/Include/core_cm0plus.h **** #define __VTOR_PRESENT 0U
195:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__VTOR_PRESENT not defined in device header file; using default!"
196:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
197:Drivers/CMSIS/Include/core_cm0plus.h ****
198:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __NVIC_PRIO_BITS
199:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_PRIO_BITS 2U
200:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
201:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
202:Drivers/CMSIS/Include/core_cm0plus.h ****
203:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __Vendor_SysTickConfig
204:Drivers/CMSIS/Include/core_cm0plus.h **** #define __Vendor_SysTickConfig 0U
205:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
206:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
207:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
208:Drivers/CMSIS/Include/core_cm0plus.h ****
209:Drivers/CMSIS/Include/core_cm0plus.h **** /* IO definitions (access restrictions to peripheral registers) */
ARM GAS /tmp/ccd4VzkJ.s page 8
210:Drivers/CMSIS/Include/core_cm0plus.h **** /**
211:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines
212:Drivers/CMSIS/Include/core_cm0plus.h ****
213:Drivers/CMSIS/Include/core_cm0plus.h **** <strong>IO Type Qualifiers</strong> are used
214:Drivers/CMSIS/Include/core_cm0plus.h **** \li to specify the access to peripheral variables.
215:Drivers/CMSIS/Include/core_cm0plus.h **** \li for automatic generation of peripheral register debug information.
216:Drivers/CMSIS/Include/core_cm0plus.h **** */
217:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus
218:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile /*!< Defines 'read only' permissions */
219:Drivers/CMSIS/Include/core_cm0plus.h **** #else
220:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile const /*!< Defines 'read only' permissions */
221:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
222:Drivers/CMSIS/Include/core_cm0plus.h **** #define __O volatile /*!< Defines 'write only' permissions */
223:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IO volatile /*!< Defines 'read / write' permissions */
224:Drivers/CMSIS/Include/core_cm0plus.h ****
225:Drivers/CMSIS/Include/core_cm0plus.h **** /* following defines should be used for structure members */
226:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */
227:Drivers/CMSIS/Include/core_cm0plus.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */
228:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */
229:Drivers/CMSIS/Include/core_cm0plus.h ****
230:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group Cortex-M0+ */
231:Drivers/CMSIS/Include/core_cm0plus.h ****
232:Drivers/CMSIS/Include/core_cm0plus.h ****
233:Drivers/CMSIS/Include/core_cm0plus.h ****
234:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
235:Drivers/CMSIS/Include/core_cm0plus.h **** * Register Abstraction
236:Drivers/CMSIS/Include/core_cm0plus.h **** Core Register contain:
237:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register
238:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Register
239:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SCB Register
240:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Register
241:Drivers/CMSIS/Include/core_cm0plus.h **** - Core MPU Register
242:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/
243:Drivers/CMSIS/Include/core_cm0plus.h **** /**
244:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_register Defines and Type Definitions
245:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions and defines for Cortex-M processor based devices.
246:Drivers/CMSIS/Include/core_cm0plus.h **** */
247:Drivers/CMSIS/Include/core_cm0plus.h ****
248:Drivers/CMSIS/Include/core_cm0plus.h **** /**
249:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
250:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CORE Status and Control Registers
251:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Core Register type definitions.
252:Drivers/CMSIS/Include/core_cm0plus.h **** @{
253:Drivers/CMSIS/Include/core_cm0plus.h **** */
254:Drivers/CMSIS/Include/core_cm0plus.h ****
255:Drivers/CMSIS/Include/core_cm0plus.h **** /**
256:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Application Program Status Register (APSR).
257:Drivers/CMSIS/Include/core_cm0plus.h **** */
258:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
259:Drivers/CMSIS/Include/core_cm0plus.h **** {
260:Drivers/CMSIS/Include/core_cm0plus.h **** struct
261:Drivers/CMSIS/Include/core_cm0plus.h **** {
262:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
263:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
264:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
265:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
266:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
ARM GAS /tmp/ccd4VzkJ.s page 9
267:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */
268:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */
269:Drivers/CMSIS/Include/core_cm0plus.h **** } APSR_Type;
270:Drivers/CMSIS/Include/core_cm0plus.h ****
271:Drivers/CMSIS/Include/core_cm0plus.h **** /* APSR Register Definitions */
272:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Pos 31U /*!< APSR
273:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR
274:Drivers/CMSIS/Include/core_cm0plus.h ****
275:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Pos 30U /*!< APSR
276:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR
277:Drivers/CMSIS/Include/core_cm0plus.h ****
278:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Pos 29U /*!< APSR
279:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR
280:Drivers/CMSIS/Include/core_cm0plus.h ****
281:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Pos 28U /*!< APSR
282:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR
283:Drivers/CMSIS/Include/core_cm0plus.h ****
284:Drivers/CMSIS/Include/core_cm0plus.h ****
285:Drivers/CMSIS/Include/core_cm0plus.h **** /**
286:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Interrupt Program Status Register (IPSR).
287:Drivers/CMSIS/Include/core_cm0plus.h **** */
288:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
289:Drivers/CMSIS/Include/core_cm0plus.h **** {
290:Drivers/CMSIS/Include/core_cm0plus.h **** struct
291:Drivers/CMSIS/Include/core_cm0plus.h **** {
292:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
294:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */
295:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */
296:Drivers/CMSIS/Include/core_cm0plus.h **** } IPSR_Type;
297:Drivers/CMSIS/Include/core_cm0plus.h ****
298:Drivers/CMSIS/Include/core_cm0plus.h **** /* IPSR Register Definitions */
299:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Pos 0U /*!< IPSR
300:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR
301:Drivers/CMSIS/Include/core_cm0plus.h ****
302:Drivers/CMSIS/Include/core_cm0plus.h ****
303:Drivers/CMSIS/Include/core_cm0plus.h **** /**
304:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
305:Drivers/CMSIS/Include/core_cm0plus.h **** */
306:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
307:Drivers/CMSIS/Include/core_cm0plus.h **** {
308:Drivers/CMSIS/Include/core_cm0plus.h **** struct
309:Drivers/CMSIS/Include/core_cm0plus.h **** {
310:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
311:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
312:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
313:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
314:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
315:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
316:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
317:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
318:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */
319:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */
320:Drivers/CMSIS/Include/core_cm0plus.h **** } xPSR_Type;
321:Drivers/CMSIS/Include/core_cm0plus.h ****
322:Drivers/CMSIS/Include/core_cm0plus.h **** /* xPSR Register Definitions */
323:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Pos 31U /*!< xPSR
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324:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR
325:Drivers/CMSIS/Include/core_cm0plus.h ****
326:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Pos 30U /*!< xPSR
327:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR
328:Drivers/CMSIS/Include/core_cm0plus.h ****
329:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Pos 29U /*!< xPSR
330:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR
331:Drivers/CMSIS/Include/core_cm0plus.h ****
332:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Pos 28U /*!< xPSR
333:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR
334:Drivers/CMSIS/Include/core_cm0plus.h ****
335:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Pos 24U /*!< xPSR
336:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
337:Drivers/CMSIS/Include/core_cm0plus.h ****
338:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Pos 0U /*!< xPSR
339:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR
340:Drivers/CMSIS/Include/core_cm0plus.h ****
341:Drivers/CMSIS/Include/core_cm0plus.h ****
342:Drivers/CMSIS/Include/core_cm0plus.h **** /**
343:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Control Registers (CONTROL).
344:Drivers/CMSIS/Include/core_cm0plus.h **** */
345:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union
346:Drivers/CMSIS/Include/core_cm0plus.h **** {
347:Drivers/CMSIS/Include/core_cm0plus.h **** struct
348:Drivers/CMSIS/Include/core_cm0plus.h **** {
349:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
350:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
351:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
352:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */
353:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */
354:Drivers/CMSIS/Include/core_cm0plus.h **** } CONTROL_Type;
355:Drivers/CMSIS/Include/core_cm0plus.h ****
356:Drivers/CMSIS/Include/core_cm0plus.h **** /* CONTROL Register Definitions */
357:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT
358:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT
359:Drivers/CMSIS/Include/core_cm0plus.h ****
360:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT
361:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT
362:Drivers/CMSIS/Include/core_cm0plus.h ****
363:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CORE */
364:Drivers/CMSIS/Include/core_cm0plus.h ****
365:Drivers/CMSIS/Include/core_cm0plus.h ****
366:Drivers/CMSIS/Include/core_cm0plus.h **** /**
367:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
368:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
369:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the NVIC Registers
370:Drivers/CMSIS/Include/core_cm0plus.h **** @{
371:Drivers/CMSIS/Include/core_cm0plus.h **** */
372:Drivers/CMSIS/Include/core_cm0plus.h ****
373:Drivers/CMSIS/Include/core_cm0plus.h **** /**
374:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
375:Drivers/CMSIS/Include/core_cm0plus.h **** */
376:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
377:Drivers/CMSIS/Include/core_cm0plus.h **** {
378:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
379:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0[31U];
380:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register
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381:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RSERVED1[31U];
382:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
383:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED2[31U];
384:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
385:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED3[31U];
386:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED4[64U];
387:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
388:Drivers/CMSIS/Include/core_cm0plus.h **** } NVIC_Type;
389:Drivers/CMSIS/Include/core_cm0plus.h ****
390:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_NVIC */
391:Drivers/CMSIS/Include/core_cm0plus.h ****
392:Drivers/CMSIS/Include/core_cm0plus.h ****
393:Drivers/CMSIS/Include/core_cm0plus.h **** /**
394:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
395:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SCB System Control Block (SCB)
396:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Control Block Registers
397:Drivers/CMSIS/Include/core_cm0plus.h **** @{
398:Drivers/CMSIS/Include/core_cm0plus.h **** */
399:Drivers/CMSIS/Include/core_cm0plus.h ****
400:Drivers/CMSIS/Include/core_cm0plus.h **** /**
401:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Control Block (SCB).
402:Drivers/CMSIS/Include/core_cm0plus.h **** */
403:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
404:Drivers/CMSIS/Include/core_cm0plus.h **** {
405:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
406:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi
407:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__VTOR_PRESENT == 1U)
408:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
409:Drivers/CMSIS/Include/core_cm0plus.h **** #else
410:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0;
411:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
412:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset
413:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
414:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register *
415:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED1;
416:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registe
417:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State
418:Drivers/CMSIS/Include/core_cm0plus.h **** } SCB_Type;
419:Drivers/CMSIS/Include/core_cm0plus.h ****
420:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB CPUID Register Definitions */
421:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB
422:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB
423:Drivers/CMSIS/Include/core_cm0plus.h ****
424:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB
425:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB
426:Drivers/CMSIS/Include/core_cm0plus.h ****
427:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB
428:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB
429:Drivers/CMSIS/Include/core_cm0plus.h ****
430:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB
431:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB
432:Drivers/CMSIS/Include/core_cm0plus.h ****
433:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB
434:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB
435:Drivers/CMSIS/Include/core_cm0plus.h ****
436:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */
437:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB
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438:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
439:Drivers/CMSIS/Include/core_cm0plus.h ****
440:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
441:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
442:Drivers/CMSIS/Include/core_cm0plus.h ****
443:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB
444:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB
445:Drivers/CMSIS/Include/core_cm0plus.h ****
446:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB
447:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB
448:Drivers/CMSIS/Include/core_cm0plus.h ****
449:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB
450:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB
451:Drivers/CMSIS/Include/core_cm0plus.h ****
452:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
453:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
454:Drivers/CMSIS/Include/core_cm0plus.h ****
455:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
456:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB
457:Drivers/CMSIS/Include/core_cm0plus.h ****
458:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB
459:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB
460:Drivers/CMSIS/Include/core_cm0plus.h ****
461:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB
462:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
463:Drivers/CMSIS/Include/core_cm0plus.h ****
464:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__VTOR_PRESENT == 1U)
465:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */
466:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB
467:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
468:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
469:Drivers/CMSIS/Include/core_cm0plus.h ****
470:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
471:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB
472:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB
473:Drivers/CMSIS/Include/core_cm0plus.h ****
474:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB
475:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB
476:Drivers/CMSIS/Include/core_cm0plus.h ****
477:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB
478:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB
479:Drivers/CMSIS/Include/core_cm0plus.h ****
480:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB
481:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB
482:Drivers/CMSIS/Include/core_cm0plus.h ****
483:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB
484:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB
485:Drivers/CMSIS/Include/core_cm0plus.h ****
486:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Control Register Definitions */
487:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB
488:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
489:Drivers/CMSIS/Include/core_cm0plus.h ****
490:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
491:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
492:Drivers/CMSIS/Include/core_cm0plus.h ****
493:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB
494:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB
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495:Drivers/CMSIS/Include/core_cm0plus.h ****
496:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Configuration Control Register Definitions */
497:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB
498:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB
499:Drivers/CMSIS/Include/core_cm0plus.h ****
500:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
501:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
502:Drivers/CMSIS/Include/core_cm0plus.h ****
503:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Handler Control and State Register Definitions */
504:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB
505:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
506:Drivers/CMSIS/Include/core_cm0plus.h ****
507:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SCB */
508:Drivers/CMSIS/Include/core_cm0plus.h ****
509:Drivers/CMSIS/Include/core_cm0plus.h ****
510:Drivers/CMSIS/Include/core_cm0plus.h **** /**
511:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
512:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
513:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Timer Registers.
514:Drivers/CMSIS/Include/core_cm0plus.h **** @{
515:Drivers/CMSIS/Include/core_cm0plus.h **** */
516:Drivers/CMSIS/Include/core_cm0plus.h ****
517:Drivers/CMSIS/Include/core_cm0plus.h **** /**
518:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Timer (SysTick).
519:Drivers/CMSIS/Include/core_cm0plus.h **** */
520:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
521:Drivers/CMSIS/Include/core_cm0plus.h **** {
522:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis
523:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
524:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register *
525:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
526:Drivers/CMSIS/Include/core_cm0plus.h **** } SysTick_Type;
527:Drivers/CMSIS/Include/core_cm0plus.h ****
528:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Control / Status Register Definitions */
529:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
530:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
531:Drivers/CMSIS/Include/core_cm0plus.h ****
532:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
533:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT
534:Drivers/CMSIS/Include/core_cm0plus.h ****
535:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT
536:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT
537:Drivers/CMSIS/Include/core_cm0plus.h ****
538:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT
539:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT
540:Drivers/CMSIS/Include/core_cm0plus.h ****
541:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Reload Register Definitions */
542:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT
543:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT
544:Drivers/CMSIS/Include/core_cm0plus.h ****
545:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Current Register Definitions */
546:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT
547:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT
548:Drivers/CMSIS/Include/core_cm0plus.h ****
549:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Calibration Register Definitions */
550:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT
551:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT
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552:Drivers/CMSIS/Include/core_cm0plus.h ****
553:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT
554:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT
555:Drivers/CMSIS/Include/core_cm0plus.h ****
556:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
557:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
558:Drivers/CMSIS/Include/core_cm0plus.h ****
559:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SysTick */
560:Drivers/CMSIS/Include/core_cm0plus.h ****
561:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__MPU_PRESENT == 1U)
562:Drivers/CMSIS/Include/core_cm0plus.h **** /**
563:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
564:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU)
565:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the Memory Protection Unit (MPU)
566:Drivers/CMSIS/Include/core_cm0plus.h **** @{
567:Drivers/CMSIS/Include/core_cm0plus.h **** */
568:Drivers/CMSIS/Include/core_cm0plus.h ****
569:Drivers/CMSIS/Include/core_cm0plus.h **** /**
570:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Memory Protection Unit (MPU).
571:Drivers/CMSIS/Include/core_cm0plus.h **** */
572:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct
573:Drivers/CMSIS/Include/core_cm0plus.h **** {
574:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
575:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
576:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
577:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register
578:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re
579:Drivers/CMSIS/Include/core_cm0plus.h **** } MPU_Type;
580:Drivers/CMSIS/Include/core_cm0plus.h ****
581:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Type Register Definitions */
582:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
583:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
584:Drivers/CMSIS/Include/core_cm0plus.h ****
585:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU
586:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU
587:Drivers/CMSIS/Include/core_cm0plus.h ****
588:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU
589:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
590:Drivers/CMSIS/Include/core_cm0plus.h ****
591:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Control Register Definitions */
592:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
593:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU
594:Drivers/CMSIS/Include/core_cm0plus.h ****
595:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU
596:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU
597:Drivers/CMSIS/Include/core_cm0plus.h ****
598:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU
599:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU
600:Drivers/CMSIS/Include/core_cm0plus.h ****
601:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Number Register Definitions */
602:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
603:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
604:Drivers/CMSIS/Include/core_cm0plus.h ****
605:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Base Address Register Definitions */
606:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Pos 8U /*!< MPU
607:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU
608:Drivers/CMSIS/Include/core_cm0plus.h ****
ARM GAS /tmp/ccd4VzkJ.s page 15
609:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU
610:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU
611:Drivers/CMSIS/Include/core_cm0plus.h ****
612:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU
613:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU
614:Drivers/CMSIS/Include/core_cm0plus.h ****
615:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Attribute and Size Register Definitions */
616:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU
617:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
618:Drivers/CMSIS/Include/core_cm0plus.h ****
619:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU
620:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
621:Drivers/CMSIS/Include/core_cm0plus.h ****
622:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
623:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
624:Drivers/CMSIS/Include/core_cm0plus.h ****
625:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
626:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
627:Drivers/CMSIS/Include/core_cm0plus.h ****
628:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Pos 18U /*!< MPU
629:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU
630:Drivers/CMSIS/Include/core_cm0plus.h ****
631:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Pos 17U /*!< MPU
632:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU
633:Drivers/CMSIS/Include/core_cm0plus.h ****
634:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Pos 16U /*!< MPU
635:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU
636:Drivers/CMSIS/Include/core_cm0plus.h ****
637:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
638:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
639:Drivers/CMSIS/Include/core_cm0plus.h ****
640:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
641:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU
642:Drivers/CMSIS/Include/core_cm0plus.h ****
643:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU
644:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU
645:Drivers/CMSIS/Include/core_cm0plus.h ****
646:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_MPU */
647:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
648:Drivers/CMSIS/Include/core_cm0plus.h ****
649:Drivers/CMSIS/Include/core_cm0plus.h ****
650:Drivers/CMSIS/Include/core_cm0plus.h **** /**
651:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
652:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
653:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ov
654:Drivers/CMSIS/Include/core_cm0plus.h **** Therefore they are not covered by the Cortex-M0+ header file.
655:Drivers/CMSIS/Include/core_cm0plus.h **** @{
656:Drivers/CMSIS/Include/core_cm0plus.h **** */
657:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CoreDebug */
658:Drivers/CMSIS/Include/core_cm0plus.h ****
659:Drivers/CMSIS/Include/core_cm0plus.h ****
660:Drivers/CMSIS/Include/core_cm0plus.h **** /**
661:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
662:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_bitfield Core register bit field macros
663:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
664:Drivers/CMSIS/Include/core_cm0plus.h **** @{
665:Drivers/CMSIS/Include/core_cm0plus.h **** */
ARM GAS /tmp/ccd4VzkJ.s page 16
666:Drivers/CMSIS/Include/core_cm0plus.h ****
667:Drivers/CMSIS/Include/core_cm0plus.h **** /**
668:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a bit field value for use in a register bit range.
669:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field.
670:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of the bit field.
671:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted value.
672:Drivers/CMSIS/Include/core_cm0plus.h **** */
673:Drivers/CMSIS/Include/core_cm0plus.h **** #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
674:Drivers/CMSIS/Include/core_cm0plus.h ****
675:Drivers/CMSIS/Include/core_cm0plus.h **** /**
676:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a register value to extract a bit filed value.
677:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field.
678:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of register.
679:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted bit field value.
680:Drivers/CMSIS/Include/core_cm0plus.h **** */
681:Drivers/CMSIS/Include/core_cm0plus.h **** #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
682:Drivers/CMSIS/Include/core_cm0plus.h ****
683:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_core_bitfield */
684:Drivers/CMSIS/Include/core_cm0plus.h ****
685:Drivers/CMSIS/Include/core_cm0plus.h ****
686:Drivers/CMSIS/Include/core_cm0plus.h **** /**
687:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register
688:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_base Core Definitions
689:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Definitions for base addresses, unions, and structures.
690:Drivers/CMSIS/Include/core_cm0plus.h **** @{
691:Drivers/CMSIS/Include/core_cm0plus.h **** */
692:Drivers/CMSIS/Include/core_cm0plus.h ****
693:Drivers/CMSIS/Include/core_cm0plus.h **** /* Memory mapping of Cortex-M0+ Hardware */
694:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas
695:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
696:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
697:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas
698:Drivers/CMSIS/Include/core_cm0plus.h ****
699:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct
700:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st
701:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
702:Drivers/CMSIS/Include/core_cm0plus.h ****
703:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__MPU_PRESENT == 1U)
704:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit *
705:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit *
706:Drivers/CMSIS/Include/core_cm0plus.h **** #endif
707:Drivers/CMSIS/Include/core_cm0plus.h ****
708:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} */
709:Drivers/CMSIS/Include/core_cm0plus.h ****
710:Drivers/CMSIS/Include/core_cm0plus.h ****
711:Drivers/CMSIS/Include/core_cm0plus.h ****
712:Drivers/CMSIS/Include/core_cm0plus.h **** /*******************************************************************************
713:Drivers/CMSIS/Include/core_cm0plus.h **** * Hardware Abstraction Layer
714:Drivers/CMSIS/Include/core_cm0plus.h **** Core Function Interface contains:
715:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Functions
716:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Functions
717:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register Access Functions
718:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/
719:Drivers/CMSIS/Include/core_cm0plus.h **** /**
720:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
721:Drivers/CMSIS/Include/core_cm0plus.h **** */
722:Drivers/CMSIS/Include/core_cm0plus.h ****
ARM GAS /tmp/ccd4VzkJ.s page 17
723:Drivers/CMSIS/Include/core_cm0plus.h ****
724:Drivers/CMSIS/Include/core_cm0plus.h ****
725:Drivers/CMSIS/Include/core_cm0plus.h **** /* ########################## NVIC functions #################################### */
726:Drivers/CMSIS/Include/core_cm0plus.h **** /**
727:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface
728:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
729:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
730:Drivers/CMSIS/Include/core_cm0plus.h **** @{
731:Drivers/CMSIS/Include/core_cm0plus.h **** */
732:Drivers/CMSIS/Include/core_cm0plus.h ****
733:Drivers/CMSIS/Include/core_cm0plus.h **** /* Interrupt Priorities are WORD accessible only under ARMv6M */
734:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following MACROS handle generation of the register offset and byte masks */
735:Drivers/CMSIS/Include/core_cm0plus.h **** #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
736:Drivers/CMSIS/Include/core_cm0plus.h **** #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
737:Drivers/CMSIS/Include/core_cm0plus.h **** #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
738:Drivers/CMSIS/Include/core_cm0plus.h ****
739:Drivers/CMSIS/Include/core_cm0plus.h ****
740:Drivers/CMSIS/Include/core_cm0plus.h **** /**
741:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Enable External Interrupt
742:Drivers/CMSIS/Include/core_cm0plus.h **** \details Enables a device-specific interrupt in the NVIC interrupt controller.
743:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
744:Drivers/CMSIS/Include/core_cm0plus.h **** */
745:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
746:Drivers/CMSIS/Include/core_cm0plus.h **** {
747:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
748:Drivers/CMSIS/Include/core_cm0plus.h **** }
749:Drivers/CMSIS/Include/core_cm0plus.h ****
750:Drivers/CMSIS/Include/core_cm0plus.h ****
751:Drivers/CMSIS/Include/core_cm0plus.h **** /**
752:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Disable External Interrupt
753:Drivers/CMSIS/Include/core_cm0plus.h **** \details Disables a device-specific interrupt in the NVIC interrupt controller.
754:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
755:Drivers/CMSIS/Include/core_cm0plus.h **** */
756:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
757:Drivers/CMSIS/Include/core_cm0plus.h **** {
758:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
759:Drivers/CMSIS/Include/core_cm0plus.h **** }
760:Drivers/CMSIS/Include/core_cm0plus.h ****
761:Drivers/CMSIS/Include/core_cm0plus.h ****
762:Drivers/CMSIS/Include/core_cm0plus.h **** /**
763:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Pending Interrupt
764:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the pending register in the NVIC and returns the pending bit for the specified int
765:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number.
766:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Interrupt status is not pending.
767:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Interrupt status is pending.
768:Drivers/CMSIS/Include/core_cm0plus.h **** */
769:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
770:Drivers/CMSIS/Include/core_cm0plus.h **** {
771:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
772:Drivers/CMSIS/Include/core_cm0plus.h **** }
773:Drivers/CMSIS/Include/core_cm0plus.h ****
774:Drivers/CMSIS/Include/core_cm0plus.h ****
775:Drivers/CMSIS/Include/core_cm0plus.h **** /**
776:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Pending Interrupt
777:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the pending bit of an external interrupt.
778:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. Value cannot be negative.
779:Drivers/CMSIS/Include/core_cm0plus.h **** */
ARM GAS /tmp/ccd4VzkJ.s page 18
780:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
781:Drivers/CMSIS/Include/core_cm0plus.h **** {
782:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
783:Drivers/CMSIS/Include/core_cm0plus.h **** }
784:Drivers/CMSIS/Include/core_cm0plus.h ****
785:Drivers/CMSIS/Include/core_cm0plus.h ****
786:Drivers/CMSIS/Include/core_cm0plus.h **** /**
787:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Clear Pending Interrupt
788:Drivers/CMSIS/Include/core_cm0plus.h **** \details Clears the pending bit of an external interrupt.
789:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
790:Drivers/CMSIS/Include/core_cm0plus.h **** */
791:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
792:Drivers/CMSIS/Include/core_cm0plus.h **** {
793:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
794:Drivers/CMSIS/Include/core_cm0plus.h **** }
795:Drivers/CMSIS/Include/core_cm0plus.h ****
796:Drivers/CMSIS/Include/core_cm0plus.h ****
797:Drivers/CMSIS/Include/core_cm0plus.h **** /**
798:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Interrupt Priority
799:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the priority of an interrupt.
800:Drivers/CMSIS/Include/core_cm0plus.h **** \note The priority cannot be set for every core interrupt.
801:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number.
802:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] priority Priority to set.
803:Drivers/CMSIS/Include/core_cm0plus.h **** */
804:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
805:Drivers/CMSIS/Include/core_cm0plus.h **** {
806:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) < 0)
42 .loc 2 806 0
43 0002 0028 cmp r0, #0
44 0004 11DB blt .L4
807:Drivers/CMSIS/Include/core_cm0plus.h **** {
808:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
809:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
810:Drivers/CMSIS/Include/core_cm0plus.h **** }
811:Drivers/CMSIS/Include/core_cm0plus.h **** else
812:Drivers/CMSIS/Include/core_cm0plus.h **** {
813:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
45 .loc 2 813 0
46 0006 8408 lsrs r4, r0, #2
47 0008 134D ldr r5, .L5
48 000a C034 adds r4, r4, #192
49 000c A400 lsls r4, r4, #2
50 000e 6259 ldr r2, [r4, r5]
51 .LVL2:
52 0010 0323 movs r3, #3
53 0012 1840 ands r0, r3
54 .LVL3:
55 0014 C000 lsls r0, r0, #3
56 0016 FC33 adds r3, r3, #252
57 0018 1E00 movs r6, r3
58 001a 8640 lsls r6, r6, r0
59 001c B243 bics r2, r6
814:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
60 .loc 2 814 0
61 001e 8901 lsls r1, r1, #6
62 .LVL4:
63 0020 0B40 ands r3, r1
ARM GAS /tmp/ccd4VzkJ.s page 19
64 0022 8340 lsls r3, r3, r0
813:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
65 .loc 2 813 0
66 0024 1343 orrs r3, r2
67 0026 6351 str r3, [r4, r5]
68 .LVL5:
69 .L1:
70 .LBE27:
71 .LBE26:
151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SetPriority(IRQn,PreemptPriority);
154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
72 .loc 1 154 0
73 @ sp needed
74 0028 70BD pop {r4, r5, r6, pc}
75 .LVL6:
76 .L4:
77 .LBB29:
78 .LBB28:
808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
79 .loc 2 808 0
80 002a C0B2 uxtb r0, r0
81 002c 0F22 movs r2, #15
82 .LVL7:
83 002e 0240 ands r2, r0
84 0030 083A subs r2, r2, #8
85 0032 9208 lsrs r2, r2, #2
86 0034 0632 adds r2, r2, #6
87 0036 9200 lsls r2, r2, #2
88 0038 084B ldr r3, .L5+4
89 003a D318 adds r3, r2, r3
90 003c 5D68 ldr r5, [r3, #4]
91 003e 0324 movs r4, #3
92 0040 2040 ands r0, r4
93 .LVL8:
94 0042 C000 lsls r0, r0, #3
95 0044 FF22 movs r2, #255
96 0046 1400 movs r4, r2
97 0048 8440 lsls r4, r4, r0
98 004a A543 bics r5, r4
809:Drivers/CMSIS/Include/core_cm0plus.h **** }
99 .loc 2 809 0
100 004c 8901 lsls r1, r1, #6
101 .LVL9:
102 004e 0A40 ands r2, r1
103 0050 8240 lsls r2, r2, r0
808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
104 .loc 2 808 0
105 0052 2A43 orrs r2, r5
106 0054 5A60 str r2, [r3, #4]
107 0056 E7E7 b .L1
108 .L6:
109 .align 2
110 .L5:
111 0058 00E100E0 .word -536813312
112 005c 00ED00E0 .word -536810240
ARM GAS /tmp/ccd4VzkJ.s page 20
113 .LBE28:
114 .LBE29:
115 .cfi_endproc
116 .LFE39:
118 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits
119 .align 1
120 .global HAL_NVIC_EnableIRQ
121 .syntax unified
122 .code 16
123 .thumb_func
124 .fpu softvfp
126 HAL_NVIC_EnableIRQ:
127 .LFB40:
155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller.
158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * function should be called before.
160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn External interrupt number .
161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
128 .loc 1 166 0
129 .cfi_startproc
130 @ args = 0, pretend = 0, frame = 0
131 @ frame_needed = 0, uses_anonymous_args = 0
132 @ link register save eliminated.
133 .LVL10:
134 .LBB30:
135 .LBB31:
747:Drivers/CMSIS/Include/core_cm0plus.h **** }
136 .loc 2 747 0
137 0000 1F23 movs r3, #31
138 0002 1840 ands r0, r3
139 .LVL11:
140 0004 1E3B subs r3, r3, #30
141 0006 8340 lsls r3, r3, r0
142 0008 014A ldr r2, .L8
143 000a 1360 str r3, [r2]
144 .LVL12:
145 .LBE31:
146 .LBE30:
167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Enable interrupt */
171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn);
172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
147 .loc 1 172 0
148 @ sp needed
149 000c 7047 bx lr
150 .L9:
151 000e C046 .align 2
152 .L8:
ARM GAS /tmp/ccd4VzkJ.s page 21
153 0010 00E100E0 .word -536813312
154 .cfi_endproc
155 .LFE40:
157 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits
158 .align 1
159 .global HAL_NVIC_DisableIRQ
160 .syntax unified
161 .code 16
162 .thumb_func
163 .fpu softvfp
165 HAL_NVIC_DisableIRQ:
166 .LFB41:
173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller.
176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn External interrupt number .
177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
167 .loc 1 182 0
168 .cfi_startproc
169 @ args = 0, pretend = 0, frame = 0
170 @ frame_needed = 0, uses_anonymous_args = 0
171 @ link register save eliminated.
172 .LVL13:
173 .LBB32:
174 .LBB33:
758:Drivers/CMSIS/Include/core_cm0plus.h **** }
175 .loc 2 758 0
176 0000 1F23 movs r3, #31
177 0002 1840 ands r0, r3
178 .LVL14:
179 0004 1E3B subs r3, r3, #30
180 0006 8340 lsls r3, r3, r0
181 0008 0149 ldr r1, .L11
182 000a 8022 movs r2, #128
183 000c 8B50 str r3, [r1, r2]
184 .LVL15:
185 .LBE33:
186 .LBE32:
183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Disable interrupt */
187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn);
188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
187 .loc 1 188 0
188 @ sp needed
189 000e 7047 bx lr
190 .L12:
191 .align 2
192 .L11:
193 0010 00E100E0 .word -536813312
194 .cfi_endproc
ARM GAS /tmp/ccd4VzkJ.s page 22
195 .LFE41:
197 .section .text.HAL_NVIC_SystemReset,"ax",%progbits
198 .align 1
199 .global HAL_NVIC_SystemReset
200 .syntax unified
201 .code 16
202 .thumb_func
203 .fpu softvfp
205 HAL_NVIC_SystemReset:
206 .LFB42:
189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU.
192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void)
195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
207 .loc 1 195 0
208 .cfi_startproc
209 @ Volatile: function does not return.
210 @ args = 0, pretend = 0, frame = 0
211 @ frame_needed = 0, uses_anonymous_args = 0
212 @ link register save eliminated.
213 .LBB42:
214 .LBB43:
215 .LBB44:
216 .LBB45:
217 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
8:Drivers/CMSIS/Include/cmsis_gcc.h ****
9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved.
10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without
11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met:
12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright
13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright
15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the
16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution.
17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used
18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without
19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission.
20:Drivers/CMSIS/Include/cmsis_gcc.h **** *
21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARM GAS /tmp/ccd4VzkJ.s page 23
30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE.
32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h ****
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
37:Drivers/CMSIS/Include/cmsis_gcc.h ****
38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ )
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
45:Drivers/CMSIS/Include/cmsis_gcc.h ****
46:Drivers/CMSIS/Include/cmsis_gcc.h ****
47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
51:Drivers/CMSIS/Include/cmsis_gcc.h **** */
52:Drivers/CMSIS/Include/cmsis_gcc.h ****
53:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
57:Drivers/CMSIS/Include/cmsis_gcc.h **** */
58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
59:Drivers/CMSIS/Include/cmsis_gcc.h **** {
60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
61:Drivers/CMSIS/Include/cmsis_gcc.h **** }
62:Drivers/CMSIS/Include/cmsis_gcc.h ****
63:Drivers/CMSIS/Include/cmsis_gcc.h ****
64:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
68:Drivers/CMSIS/Include/cmsis_gcc.h **** */
69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
70:Drivers/CMSIS/Include/cmsis_gcc.h **** {
71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
72:Drivers/CMSIS/Include/cmsis_gcc.h **** }
73:Drivers/CMSIS/Include/cmsis_gcc.h ****
74:Drivers/CMSIS/Include/cmsis_gcc.h ****
75:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
79:Drivers/CMSIS/Include/cmsis_gcc.h **** */
80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
81:Drivers/CMSIS/Include/cmsis_gcc.h **** {
82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
83:Drivers/CMSIS/Include/cmsis_gcc.h ****
84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
86:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS /tmp/ccd4VzkJ.s page 24
87:Drivers/CMSIS/Include/cmsis_gcc.h ****
88:Drivers/CMSIS/Include/cmsis_gcc.h ****
89:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
93:Drivers/CMSIS/Include/cmsis_gcc.h **** */
94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
95:Drivers/CMSIS/Include/cmsis_gcc.h **** {
96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
97:Drivers/CMSIS/Include/cmsis_gcc.h **** }
98:Drivers/CMSIS/Include/cmsis_gcc.h ****
99:Drivers/CMSIS/Include/cmsis_gcc.h ****
100:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
104:Drivers/CMSIS/Include/cmsis_gcc.h **** */
105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
106:Drivers/CMSIS/Include/cmsis_gcc.h **** {
107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
108:Drivers/CMSIS/Include/cmsis_gcc.h ****
109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
111:Drivers/CMSIS/Include/cmsis_gcc.h **** }
112:Drivers/CMSIS/Include/cmsis_gcc.h ****
113:Drivers/CMSIS/Include/cmsis_gcc.h ****
114:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
118:Drivers/CMSIS/Include/cmsis_gcc.h **** */
119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
120:Drivers/CMSIS/Include/cmsis_gcc.h **** {
121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
122:Drivers/CMSIS/Include/cmsis_gcc.h ****
123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
125:Drivers/CMSIS/Include/cmsis_gcc.h **** }
126:Drivers/CMSIS/Include/cmsis_gcc.h ****
127:Drivers/CMSIS/Include/cmsis_gcc.h ****
128:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
131:Drivers/CMSIS/Include/cmsis_gcc.h ****
132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
133:Drivers/CMSIS/Include/cmsis_gcc.h **** */
134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
135:Drivers/CMSIS/Include/cmsis_gcc.h **** {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
137:Drivers/CMSIS/Include/cmsis_gcc.h ****
138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
140:Drivers/CMSIS/Include/cmsis_gcc.h **** }
141:Drivers/CMSIS/Include/cmsis_gcc.h ****
142:Drivers/CMSIS/Include/cmsis_gcc.h ****
143:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS /tmp/ccd4VzkJ.s page 25
144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
147:Drivers/CMSIS/Include/cmsis_gcc.h **** */
148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
149:Drivers/CMSIS/Include/cmsis_gcc.h **** {
150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result;
151:Drivers/CMSIS/Include/cmsis_gcc.h ****
152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h ****
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
161:Drivers/CMSIS/Include/cmsis_gcc.h **** */
162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
163:Drivers/CMSIS/Include/cmsis_gcc.h **** {
164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
165:Drivers/CMSIS/Include/cmsis_gcc.h **** }
166:Drivers/CMSIS/Include/cmsis_gcc.h ****
167:Drivers/CMSIS/Include/cmsis_gcc.h ****
168:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
172:Drivers/CMSIS/Include/cmsis_gcc.h **** */
173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
174:Drivers/CMSIS/Include/cmsis_gcc.h **** {
175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result;
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
179:Drivers/CMSIS/Include/cmsis_gcc.h **** }
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h ****
182:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
187:Drivers/CMSIS/Include/cmsis_gcc.h **** */
188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
189:Drivers/CMSIS/Include/cmsis_gcc.h **** {
190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
191:Drivers/CMSIS/Include/cmsis_gcc.h **** }
192:Drivers/CMSIS/Include/cmsis_gcc.h ****
193:Drivers/CMSIS/Include/cmsis_gcc.h ****
194:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
198:Drivers/CMSIS/Include/cmsis_gcc.h **** */
199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
200:Drivers/CMSIS/Include/cmsis_gcc.h **** {
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201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
202:Drivers/CMSIS/Include/cmsis_gcc.h ****
203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) );
204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
205:Drivers/CMSIS/Include/cmsis_gcc.h **** }
206:Drivers/CMSIS/Include/cmsis_gcc.h ****
207:Drivers/CMSIS/Include/cmsis_gcc.h ****
208:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
212:Drivers/CMSIS/Include/cmsis_gcc.h **** */
213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
214:Drivers/CMSIS/Include/cmsis_gcc.h **** {
215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
216:Drivers/CMSIS/Include/cmsis_gcc.h **** }
217:Drivers/CMSIS/Include/cmsis_gcc.h ****
218:Drivers/CMSIS/Include/cmsis_gcc.h ****
219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U)
220:Drivers/CMSIS/Include/cmsis_gcc.h ****
221:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
225:Drivers/CMSIS/Include/cmsis_gcc.h **** */
226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
227:Drivers/CMSIS/Include/cmsis_gcc.h **** {
228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
229:Drivers/CMSIS/Include/cmsis_gcc.h **** }
230:Drivers/CMSIS/Include/cmsis_gcc.h ****
231:Drivers/CMSIS/Include/cmsis_gcc.h ****
232:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
236:Drivers/CMSIS/Include/cmsis_gcc.h **** */
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
238:Drivers/CMSIS/Include/cmsis_gcc.h **** {
239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
240:Drivers/CMSIS/Include/cmsis_gcc.h **** }
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
242:Drivers/CMSIS/Include/cmsis_gcc.h ****
243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
247:Drivers/CMSIS/Include/cmsis_gcc.h **** */
248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
251:Drivers/CMSIS/Include/cmsis_gcc.h ****
252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
254:Drivers/CMSIS/Include/cmsis_gcc.h **** }
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
256:Drivers/CMSIS/Include/cmsis_gcc.h ****
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
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258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
265:Drivers/CMSIS/Include/cmsis_gcc.h **** }
266:Drivers/CMSIS/Include/cmsis_gcc.h ****
267:Drivers/CMSIS/Include/cmsis_gcc.h ****
268:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
273:Drivers/CMSIS/Include/cmsis_gcc.h **** */
274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
275:Drivers/CMSIS/Include/cmsis_gcc.h **** {
276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
277:Drivers/CMSIS/Include/cmsis_gcc.h **** }
278:Drivers/CMSIS/Include/cmsis_gcc.h ****
279:Drivers/CMSIS/Include/cmsis_gcc.h ****
280:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
284:Drivers/CMSIS/Include/cmsis_gcc.h **** */
285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
286:Drivers/CMSIS/Include/cmsis_gcc.h **** {
287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
288:Drivers/CMSIS/Include/cmsis_gcc.h ****
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
291:Drivers/CMSIS/Include/cmsis_gcc.h **** }
292:Drivers/CMSIS/Include/cmsis_gcc.h ****
293:Drivers/CMSIS/Include/cmsis_gcc.h ****
294:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
298:Drivers/CMSIS/Include/cmsis_gcc.h **** */
299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
300:Drivers/CMSIS/Include/cmsis_gcc.h **** {
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
302:Drivers/CMSIS/Include/cmsis_gcc.h **** }
303:Drivers/CMSIS/Include/cmsis_gcc.h ****
304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */
305:Drivers/CMSIS/Include/cmsis_gcc.h ****
306:Drivers/CMSIS/Include/cmsis_gcc.h ****
307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
313:Drivers/CMSIS/Include/cmsis_gcc.h **** */
314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
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315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
318:Drivers/CMSIS/Include/cmsis_gcc.h ****
319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0);
326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
327:Drivers/CMSIS/Include/cmsis_gcc.h **** }
328:Drivers/CMSIS/Include/cmsis_gcc.h ****
329:Drivers/CMSIS/Include/cmsis_gcc.h ****
330:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
334:Drivers/CMSIS/Include/cmsis_gcc.h **** */
335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
336:Drivers/CMSIS/Include/cmsis_gcc.h **** {
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
343:Drivers/CMSIS/Include/cmsis_gcc.h **** }
344:Drivers/CMSIS/Include/cmsis_gcc.h ****
345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
346:Drivers/CMSIS/Include/cmsis_gcc.h ****
347:Drivers/CMSIS/Include/cmsis_gcc.h ****
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
350:Drivers/CMSIS/Include/cmsis_gcc.h ****
351:Drivers/CMSIS/Include/cmsis_gcc.h ****
352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
356:Drivers/CMSIS/Include/cmsis_gcc.h **** */
357:Drivers/CMSIS/Include/cmsis_gcc.h ****
358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
368:Drivers/CMSIS/Include/cmsis_gcc.h ****
369:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
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372:Drivers/CMSIS/Include/cmsis_gcc.h **** */
373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
374:Drivers/CMSIS/Include/cmsis_gcc.h **** {
375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop");
376:Drivers/CMSIS/Include/cmsis_gcc.h **** }
377:Drivers/CMSIS/Include/cmsis_gcc.h ****
378:Drivers/CMSIS/Include/cmsis_gcc.h ****
379:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
381:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
382:Drivers/CMSIS/Include/cmsis_gcc.h **** */
383:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
385:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfi");
386:Drivers/CMSIS/Include/cmsis_gcc.h **** }
387:Drivers/CMSIS/Include/cmsis_gcc.h ****
388:Drivers/CMSIS/Include/cmsis_gcc.h ****
389:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
390:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
391:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
392:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
393:Drivers/CMSIS/Include/cmsis_gcc.h **** */
394:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
395:Drivers/CMSIS/Include/cmsis_gcc.h **** {
396:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfe");
397:Drivers/CMSIS/Include/cmsis_gcc.h **** }
398:Drivers/CMSIS/Include/cmsis_gcc.h ****
399:Drivers/CMSIS/Include/cmsis_gcc.h ****
400:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
401:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
402:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
403:Drivers/CMSIS/Include/cmsis_gcc.h **** */
404:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
405:Drivers/CMSIS/Include/cmsis_gcc.h **** {
406:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("sev");
407:Drivers/CMSIS/Include/cmsis_gcc.h **** }
408:Drivers/CMSIS/Include/cmsis_gcc.h ****
409:Drivers/CMSIS/Include/cmsis_gcc.h ****
410:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
411:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
412:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
413:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
414:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed.
415:Drivers/CMSIS/Include/cmsis_gcc.h **** */
416:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
417:Drivers/CMSIS/Include/cmsis_gcc.h **** {
418:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
419:Drivers/CMSIS/Include/cmsis_gcc.h **** }
420:Drivers/CMSIS/Include/cmsis_gcc.h ****
421:Drivers/CMSIS/Include/cmsis_gcc.h ****
422:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
423:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier
424:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
425:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
426:Drivers/CMSIS/Include/cmsis_gcc.h **** */
427:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
428:Drivers/CMSIS/Include/cmsis_gcc.h **** {
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429:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
218 .loc 3 429 0
219 .syntax divided
220 @ 429 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
221 0000 BFF34F8F dsb 0xF
222 @ 0 "" 2
223 .thumb
224 .syntax unified
225 .LBE45:
226 .LBE44:
815:Drivers/CMSIS/Include/core_cm0plus.h **** }
816:Drivers/CMSIS/Include/core_cm0plus.h **** }
817:Drivers/CMSIS/Include/core_cm0plus.h ****
818:Drivers/CMSIS/Include/core_cm0plus.h ****
819:Drivers/CMSIS/Include/core_cm0plus.h **** /**
820:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Interrupt Priority
821:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the priority of an interrupt.
822:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify an external (device specific) interrupt,
823:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify an internal (core) interrupt.
824:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number.
825:Drivers/CMSIS/Include/core_cm0plus.h **** \return Interrupt Priority.
826:Drivers/CMSIS/Include/core_cm0plus.h **** Value is aligned automatically to the implemented priority bits of the microc
827:Drivers/CMSIS/Include/core_cm0plus.h **** */
828:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
829:Drivers/CMSIS/Include/core_cm0plus.h **** {
830:Drivers/CMSIS/Include/core_cm0plus.h ****
831:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) < 0)
832:Drivers/CMSIS/Include/core_cm0plus.h **** {
833:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
834:Drivers/CMSIS/Include/core_cm0plus.h **** }
835:Drivers/CMSIS/Include/core_cm0plus.h **** else
836:Drivers/CMSIS/Include/core_cm0plus.h **** {
837:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
838:Drivers/CMSIS/Include/core_cm0plus.h **** }
839:Drivers/CMSIS/Include/core_cm0plus.h **** }
840:Drivers/CMSIS/Include/core_cm0plus.h ****
841:Drivers/CMSIS/Include/core_cm0plus.h ****
842:Drivers/CMSIS/Include/core_cm0plus.h **** /**
843:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Reset
844:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initiates a system reset request to reset the MCU.
845:Drivers/CMSIS/Include/core_cm0plus.h **** */
846:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_SystemReset(void)
847:Drivers/CMSIS/Include/core_cm0plus.h **** {
848:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure all outstanding memor
849:Drivers/CMSIS/Include/core_cm0plus.h **** buffered write are completed
850:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
227 .loc 2 850 0
228 0004 034B ldr r3, .L15
229 0006 044A ldr r2, .L15+4
230 0008 DA60 str r2, [r3, #12]
231 .LBB46:
232 .LBB47:
233 .loc 3 429 0
234 .syntax divided
235 @ 429 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
236 000a BFF34F8F dsb 0xF
237 @ 0 "" 2
ARM GAS /tmp/ccd4VzkJ.s page 31
238 .thumb
239 .syntax unified
240 .L14:
241 .LBE47:
242 .LBE46:
243 .LBB48:
244 .LBB49:
375:Drivers/CMSIS/Include/cmsis_gcc.h **** }
245 .loc 3 375 0
246 .syntax divided
247 @ 375 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
248 000e C046 nop
249 @ 0 "" 2
250 .thumb
251 .syntax unified
252 0010 FDE7 b .L14
253 .L16:
254 0012 C046 .align 2
255 .L15:
256 0014 00ED00E0 .word -536810240
257 0018 0400FA05 .word 100270084
258 .LBE49:
259 .LBE48:
260 .LBE43:
261 .LBE42:
262 .cfi_endproc
263 .LFE42:
265 .section .text.HAL_SYSTICK_Config,"ax",%progbits
266 .align 1
267 .global HAL_SYSTICK_Config
268 .syntax unified
269 .code 16
270 .thumb_func
271 .fpu softvfp
273 HAL_SYSTICK_Config:
274 .LFB43:
196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* System Reset */
197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SystemReset();
198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts.
203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval status: - 0 Function succeeded.
205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * - 1 Function failed.
206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
275 .loc 1 208 0
276 .cfi_startproc
277 @ args = 0, pretend = 0, frame = 0
278 @ frame_needed = 0, uses_anonymous_args = 0
279 @ link register save eliminated.
280 .LVL16:
281 .LBB50:
282 .LBB51:
ARM GAS /tmp/ccd4VzkJ.s page 32
851:Drivers/CMSIS/Include/core_cm0plus.h **** SCB_AIRCR_SYSRESETREQ_Msk);
852:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure completion of memory
853:Drivers/CMSIS/Include/core_cm0plus.h ****
854:Drivers/CMSIS/Include/core_cm0plus.h **** for(;;) /* wait until reset */
855:Drivers/CMSIS/Include/core_cm0plus.h **** {
856:Drivers/CMSIS/Include/core_cm0plus.h **** __NOP();
857:Drivers/CMSIS/Include/core_cm0plus.h **** }
858:Drivers/CMSIS/Include/core_cm0plus.h **** }
859:Drivers/CMSIS/Include/core_cm0plus.h ****
860:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_NVICFunctions */
861:Drivers/CMSIS/Include/core_cm0plus.h ****
862:Drivers/CMSIS/Include/core_cm0plus.h ****
863:Drivers/CMSIS/Include/core_cm0plus.h ****
864:Drivers/CMSIS/Include/core_cm0plus.h **** /* ################################## SysTick function ########################################
865:Drivers/CMSIS/Include/core_cm0plus.h **** /**
866:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface
867:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
868:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that configure the System.
869:Drivers/CMSIS/Include/core_cm0plus.h **** @{
870:Drivers/CMSIS/Include/core_cm0plus.h **** */
871:Drivers/CMSIS/Include/core_cm0plus.h ****
872:Drivers/CMSIS/Include/core_cm0plus.h **** #if (__Vendor_SysTickConfig == 0U)
873:Drivers/CMSIS/Include/core_cm0plus.h ****
874:Drivers/CMSIS/Include/core_cm0plus.h **** /**
875:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Tick Configuration
876:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
877:Drivers/CMSIS/Include/core_cm0plus.h **** Counter is in free running mode to generate periodic interrupts.
878:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] ticks Number of ticks between two interrupts.
879:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Function succeeded.
880:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Function failed.
881:Drivers/CMSIS/Include/core_cm0plus.h **** \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
882:Drivers/CMSIS/Include/core_cm0plus.h **** function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
883:Drivers/CMSIS/Include/core_cm0plus.h **** must contain a vendor-specific implementation of this function.
884:Drivers/CMSIS/Include/core_cm0plus.h **** */
885:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
886:Drivers/CMSIS/Include/core_cm0plus.h **** {
887:Drivers/CMSIS/Include/core_cm0plus.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
283 .loc 2 887 0
284 0000 0138 subs r0, r0, #1
285 .LVL17:
286 0002 0A4B ldr r3, .L20
287 0004 9842 cmp r0, r3
288 0006 0FD8 bhi .L19
888:Drivers/CMSIS/Include/core_cm0plus.h **** {
889:Drivers/CMSIS/Include/core_cm0plus.h **** return (1UL); /* Reload value impossible */
890:Drivers/CMSIS/Include/core_cm0plus.h **** }
891:Drivers/CMSIS/Include/core_cm0plus.h ****
892:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
289 .loc 2 892 0
290 0008 094A ldr r2, .L20+4
291 000a 5060 str r0, [r2, #4]
292 .LVL18:
293 .LBB52:
294 .LBB53:
808:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
295 .loc 2 808 0
296 000c 0948 ldr r0, .L20+8
ARM GAS /tmp/ccd4VzkJ.s page 33
297 .LVL19:
298 000e 036A ldr r3, [r0, #32]
299 0010 1B02 lsls r3, r3, #8
300 0012 1B0A lsrs r3, r3, #8
301 0014 C021 movs r1, #192
302 0016 0906 lsls r1, r1, #24
303 0018 0B43 orrs r3, r1
304 001a 0362 str r3, [r0, #32]
305 .LVL20:
306 .LBE53:
307 .LBE52:
893:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
894:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val
308 .loc 2 894 0
309 001c 0023 movs r3, #0
310 001e 9360 str r3, [r2, #8]
895:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
311 .loc 2 895 0
312 0020 0733 adds r3, r3, #7
313 0022 1360 str r3, [r2]
896:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_TICKINT_Msk |
897:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi
898:Drivers/CMSIS/Include/core_cm0plus.h **** return (0UL); /* Function successful */
314 .loc 2 898 0
315 0024 0020 movs r0, #0
316 .LVL21:
317 .L17:
318 .LBE51:
319 .LBE50:
209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return SysTick_Config(TicksNumb);
210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
320 .loc 1 210 0
321 @ sp needed
322 0026 7047 bx lr
323 .LVL22:
324 .L19:
325 .LBB55:
326 .LBB54:
889:Drivers/CMSIS/Include/core_cm0plus.h **** }
327 .loc 2 889 0
328 0028 0120 movs r0, #1
329 .LVL23:
330 .LBE54:
331 .LBE55:
209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return SysTick_Config(TicksNumb);
332 .loc 1 209 0
333 002a FCE7 b .L17
334 .L21:
335 .align 2
336 .L20:
337 002c FFFFFF00 .word 16777215
338 0030 10E000E0 .word -536813552
339 0034 00ED00E0 .word -536810240
340 .cfi_endproc
341 .LFE43:
343 .section .text.HAL_NVIC_GetPriority,"ax",%progbits
344 .align 1
ARM GAS /tmp/ccd4VzkJ.s page 34
345 .global HAL_NVIC_GetPriority
346 .syntax unified
347 .code 16
348 .thumb_func
349 .fpu softvfp
351 HAL_NVIC_GetPriority:
352 .LFB44:
211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @}
213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Cortex control functions
217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** *
218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @verbatim
219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ##### Peripheral Control functions #####
221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ==============================================================================
222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** [..]
223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX
224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** (NVIC, SYSTICK) functionalities.
225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** @endverbatim
228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @{
229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Gets the priority of an interrupt.
234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number.
235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI
237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
353 .loc 1 240 0
354 .cfi_startproc
355 @ args = 0, pretend = 0, frame = 0
356 @ frame_needed = 0, uses_anonymous_args = 0
357 @ link register save eliminated.
358 .LVL24:
359 .LBB58:
360 .LBB59:
831:Drivers/CMSIS/Include/core_cm0plus.h **** {
361 .loc 2 831 0
362 0000 0028 cmp r0, #0
363 0002 0CDB blt .L25
837:Drivers/CMSIS/Include/core_cm0plus.h **** }
364 .loc 2 837 0
365 0004 8308 lsrs r3, r0, #2
366 0006 C033 adds r3, r3, #192
367 0008 9B00 lsls r3, r3, #2
368 000a 0E4A ldr r2, .L26
369 000c 9B58 ldr r3, [r3, r2]
370 000e 0322 movs r2, #3
ARM GAS /tmp/ccd4VzkJ.s page 35
371 0010 1040 ands r0, r2
372 .LVL25:
373 0012 C000 lsls r0, r0, #3
374 0014 C340 lsrs r3, r3, r0
375 0016 9809 lsrs r0, r3, #6
376 0018 0323 movs r3, #3
377 001a 1840 ands r0, r3
378 .LVL26:
379 .L22:
380 .LBE59:
381 .LBE58:
241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */
242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return NVIC_GetPriority(IRQn);
243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
382 .loc 1 243 0
383 @ sp needed
384 001c 7047 bx lr
385 .LVL27:
386 .L25:
387 .LBB61:
388 .LBB60:
833:Drivers/CMSIS/Include/core_cm0plus.h **** }
389 .loc 2 833 0
390 001e C0B2 uxtb r0, r0
391 0020 0F23 movs r3, #15
392 0022 0340 ands r3, r0
393 0024 083B subs r3, r3, #8
394 0026 9B08 lsrs r3, r3, #2
395 0028 0633 adds r3, r3, #6
396 002a 9B00 lsls r3, r3, #2
397 002c 064A ldr r2, .L26+4
398 002e 9446 mov ip, r2
399 0030 6344 add r3, r3, ip
400 0032 5B68 ldr r3, [r3, #4]
401 0034 0322 movs r2, #3
402 0036 1040 ands r0, r2
403 .LVL28:
404 0038 C000 lsls r0, r0, #3
405 003a C340 lsrs r3, r3, r0
406 003c 9B09 lsrs r3, r3, #6
407 003e 0320 movs r0, #3
408 0040 1840 ands r0, r3
409 0042 EBE7 b .L22
410 .L27:
411 .align 2
412 .L26:
413 0044 00E100E0 .word -536813312
414 0048 00ED00E0 .word -536810240
415 .LBE60:
416 .LBE61:
417 .cfi_endproc
418 .LFE44:
420 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits
421 .align 1
422 .global HAL_NVIC_SetPendingIRQ
423 .syntax unified
424 .code 16
ARM GAS /tmp/ccd4VzkJ.s page 36
425 .thumb_func
426 .fpu softvfp
428 HAL_NVIC_SetPendingIRQ:
429 .LFB45:
244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt.
247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number
248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
430 .loc 1 253 0
431 .cfi_startproc
432 @ args = 0, pretend = 0, frame = 0
433 @ frame_needed = 0, uses_anonymous_args = 0
434 @ link register save eliminated.
435 .LVL29:
436 .LBB62:
437 .LBB63:
782:Drivers/CMSIS/Include/core_cm0plus.h **** }
438 .loc 2 782 0
439 0000 1F23 movs r3, #31
440 0002 1840 ands r0, r3
441 .LVL30:
442 0004 1E3B subs r3, r3, #30
443 0006 8340 lsls r3, r3, r0
444 0008 0249 ldr r1, .L29
445 000a 8022 movs r2, #128
446 000c 5200 lsls r2, r2, #1
447 000e 8B50 str r3, [r1, r2]
448 .LVL31:
449 .LBE63:
450 .LBE62:
254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set interrupt pending */
255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn);
256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
451 .loc 1 256 0
452 @ sp needed
453 0010 7047 bx lr
454 .L30:
455 0012 C046 .align 2
456 .L29:
457 0014 00E100E0 .word -536813312
458 .cfi_endproc
459 .LFE45:
461 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits
462 .align 1
463 .global HAL_NVIC_GetPendingIRQ
464 .syntax unified
465 .code 16
466 .thumb_func
467 .fpu softvfp
469 HAL_NVIC_GetPendingIRQ:
470 .LFB46:
ARM GAS /tmp/ccd4VzkJ.s page 37
257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC
260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt).
261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number .
262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending.
265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * - 1 Interrupt status is pending.
266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
471 .loc 1 268 0
472 .cfi_startproc
473 @ args = 0, pretend = 0, frame = 0
474 @ frame_needed = 0, uses_anonymous_args = 0
475 @ link register save eliminated.
476 .LVL32:
477 .LBB64:
478 .LBB65:
771:Drivers/CMSIS/Include/core_cm0plus.h **** }
479 .loc 2 771 0
480 0000 044A ldr r2, .L32
481 0002 8023 movs r3, #128
482 0004 5B00 lsls r3, r3, #1
483 0006 D358 ldr r3, [r2, r3]
484 0008 1F22 movs r2, #31
485 000a 1040 ands r0, r2
486 .LVL33:
487 000c C340 lsrs r3, r3, r0
488 000e 0120 movs r0, #1
489 0010 1840 ands r0, r3
490 .LVL34:
491 .LBE65:
492 .LBE64:
269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Return 1 if pending else 0 */
270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn);
271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
493 .loc 1 271 0
494 @ sp needed
495 0012 7047 bx lr
496 .L33:
497 .align 2
498 .L32:
499 0014 00E100E0 .word -536813312
500 .cfi_endproc
501 .LFE46:
503 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits
504 .align 1
505 .global HAL_NVIC_ClearPendingIRQ
506 .syntax unified
507 .code 16
508 .thumb_func
509 .fpu softvfp
511 HAL_NVIC_ClearPendingIRQ:
512 .LFB47:
272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
ARM GAS /tmp/ccd4VzkJ.s page 38
273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt.
275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param IRQn: External interrupt number .
276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration
277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
513 .loc 1 281 0
514 .cfi_startproc
515 @ args = 0, pretend = 0, frame = 0
516 @ frame_needed = 0, uses_anonymous_args = 0
517 @ link register save eliminated.
518 .LVL35:
519 .LBB66:
520 .LBB67:
793:Drivers/CMSIS/Include/core_cm0plus.h **** }
521 .loc 2 793 0
522 0000 1F23 movs r3, #31
523 0002 1840 ands r0, r3
524 .LVL36:
525 0004 1E3B subs r3, r3, #30
526 0006 8340 lsls r3, r3, r0
527 0008 0249 ldr r1, .L35
528 000a C022 movs r2, #192
529 000c 5200 lsls r2, r2, #1
530 000e 8B50 str r3, [r1, r2]
531 .LVL37:
532 .LBE67:
533 .LBE66:
282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Clear pending interrupt */
283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn);
284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
534 .loc 1 284 0
535 @ sp needed
536 0010 7047 bx lr
537 .L36:
538 0012 C046 .align 2
539 .L35:
540 0014 00E100E0 .word -536813312
541 .cfi_endproc
542 .LFE47:
544 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits
545 .align 1
546 .global HAL_SYSTICK_CLKSourceConfig
547 .syntax unified
548 .code 16
549 .thumb_func
550 .fpu softvfp
552 HAL_SYSTICK_CLKSourceConfig:
553 .LFB48:
285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Configures the SysTick clock source.
289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param CLKSource: specifies the SysTick clock source.
ARM GAS /tmp/ccd4VzkJ.s page 39
290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * This parameter can be one of the following values:
291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock
292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
554 .loc 1 296 0
555 .cfi_startproc
556 @ args = 0, pretend = 0, frame = 0
557 @ frame_needed = 0, uses_anonymous_args = 0
558 @ link register save eliminated.
559 .LVL38:
297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
560 .loc 1 299 0
561 0000 0428 cmp r0, #4
562 0002 05D0 beq .L40
300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** else
304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
563 .loc 1 305 0
564 0004 054A ldr r2, .L41
565 0006 1368 ldr r3, [r2]
566 0008 0421 movs r1, #4
567 000a 8B43 bics r3, r1
568 000c 1360 str r3, [r2]
569 .L37:
306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
570 .loc 1 307 0
571 @ sp needed
572 000e 7047 bx lr
573 .L40:
301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
574 .loc 1 301 0
575 0010 024A ldr r2, .L41
576 0012 1368 ldr r3, [r2]
577 0014 0421 movs r1, #4
578 0016 0B43 orrs r3, r1
579 0018 1360 str r3, [r2]
580 001a F8E7 b .L37
581 .L42:
582 .align 2
583 .L41:
584 001c 10E000E0 .word -536813552
585 .cfi_endproc
586 .LFE48:
588 .section .text.HAL_SYSTICK_Callback,"ax",%progbits
589 .align 1
590 .weak HAL_SYSTICK_Callback
591 .syntax unified
592 .code 16
ARM GAS /tmp/ccd4VzkJ.s page 40
593 .thumb_func
594 .fpu softvfp
596 HAL_SYSTICK_Callback:
597 .LFB50:
308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request.
311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void)
314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Callback();
316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief SYSTICK callback.
320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
598 .loc 1 323 0
599 .cfi_startproc
600 @ args = 0, pretend = 0, frame = 0
601 @ frame_needed = 0, uses_anonymous_args = 0
602 @ link register save eliminated.
324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed,
325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file
326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
603 .loc 1 327 0
604 @ sp needed
605 0000 7047 bx lr
606 .cfi_endproc
607 .LFE50:
609 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits
610 .align 1
611 .global HAL_SYSTICK_IRQHandler
612 .syntax unified
613 .code 16
614 .thumb_func
615 .fpu softvfp
617 HAL_SYSTICK_IRQHandler:
618 .LFB49:
314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** HAL_SYSTICK_Callback();
619 .loc 1 314 0
620 .cfi_startproc
621 @ args = 0, pretend = 0, frame = 0
622 @ frame_needed = 0, uses_anonymous_args = 0
623 0000 10B5 push {r4, lr}
624 .LCFI1:
625 .cfi_def_cfa_offset 8
626 .cfi_offset 4, -8
627 .cfi_offset 14, -4
315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
628 .loc 1 315 0
629 0002 FFF7FEFF bl HAL_SYSTICK_Callback
630 .LVL39:
ARM GAS /tmp/ccd4VzkJ.s page 41
316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
631 .loc 1 316 0
632 @ sp needed
633 0006 10BD pop {r4, pc}
634 .cfi_endproc
635 .LFE49:
637 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits
638 .align 1
639 .global HAL_MPU_ConfigRegion
640 .syntax unified
641 .code 16
642 .thumb_func
643 .fpu softvfp
645 HAL_MPU_ConfigRegion:
646 .LFB51:
328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** #if (__MPU_PRESENT == 1)
330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /**
331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @brief Initialize and configure the Region and the memory to be protected.
332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * the initialization and configuration information.
334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** * @retval None
335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** */
336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
647 .loc 1 337 0
648 .cfi_startproc
649 @ args = 0, pretend = 0, frame = 0
650 @ frame_needed = 0, uses_anonymous_args = 0
651 @ link register save eliminated.
652 .LVL40:
338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set the Region number */
343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number;
653 .loc 1 343 0
654 0000 4279 ldrb r2, [r0, #5]
655 0002 134B ldr r3, .L49
656 0004 9A60 str r2, [r3, #8]
344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** if ((MPU_Init->Enable) == MPU_REGION_ENABLE)
657 .loc 1 345 0
658 0006 0379 ldrb r3, [r0, #4]
659 0008 012B cmp r3, #1
660 000a 04D0 beq .L48
346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Check the parameters */
348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
ARM GAS /tmp/ccd4VzkJ.s page 42
356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Set the base adsress and set the 4 LSB to 0 */
357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U;
358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** /* Fill the field RASR */
360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** else
370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** {
371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RBAR = 0x00U;
661 .loc 1 371 0
662 000c 104B ldr r3, .L49
663 000e 0022 movs r2, #0
664 0010 DA60 str r2, [r3, #12]
372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** MPU->RASR = 0x00U;
665 .loc 1 372 0
666 0012 1A61 str r2, [r3, #16]
667 .L45:
373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
668 .loc 1 374 0
669 @ sp needed
670 0014 7047 bx lr
671 .L48:
357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c ****
672 .loc 1 357 0
673 0016 0E33 adds r3, r3, #14
674 0018 0268 ldr r2, [r0]
675 001a 9A43 bics r2, r3
676 001c 0C49 ldr r1, .L49
677 001e CA60 str r2, [r1, #12]
360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
678 .loc 1 360 0
679 0020 837A ldrb r3, [r0, #10]
680 0022 1B07 lsls r3, r3, #28
361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
681 .loc 1 361 0
682 0024 427A ldrb r2, [r0, #9]
683 0026 1206 lsls r2, r2, #24
360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
684 .loc 1 360 0
685 0028 1343 orrs r3, r2
362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
686 .loc 1 362 0
687 002a C27A ldrb r2, [r0, #11]
688 002c 9204 lsls r2, r2, #18
361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
689 .loc 1 361 0
690 002e 1343 orrs r3, r2
363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
691 .loc 1 363 0
ARM GAS /tmp/ccd4VzkJ.s page 43
692 0030 027B ldrb r2, [r0, #12]
693 0032 5204 lsls r2, r2, #17
362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
694 .loc 1 362 0
695 0034 1343 orrs r3, r2
364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
696 .loc 1 364 0
697 0036 427B ldrb r2, [r0, #13]
698 0038 1204 lsls r2, r2, #16
363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
699 .loc 1 363 0
700 003a 1343 orrs r3, r2
365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
701 .loc 1 365 0
702 003c C279 ldrb r2, [r0, #7]
703 003e 1202 lsls r2, r2, #8
364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
704 .loc 1 364 0
705 0040 1343 orrs r3, r2
366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
706 .loc 1 366 0
707 0042 8279 ldrb r2, [r0, #6]
708 0044 5200 lsls r2, r2, #1
365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
709 .loc 1 365 0
710 0046 1343 orrs r3, r2
367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** }
711 .loc 1 367 0
712 0048 0279 ldrb r2, [r0, #4]
366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
713 .loc 1 366 0
714 004a 1343 orrs r3, r2
360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
715 .loc 1 360 0
716 004c 0B61 str r3, [r1, #16]
717 004e E1E7 b .L45
718 .L50:
719 .align 2
720 .L49:
721 0050 90ED00E0 .word -536810096
722 .cfi_endproc
723 .LFE51:
725 .text
726 .Letext0:
727 .file 4 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h"
728 .file 5 "/usr/arm-none-eabi/include/machine/_default_types.h"
729 .file 6 "/usr/arm-none-eabi/include/sys/_stdint.h"
730 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h"
731 .file 8 "/usr/arm-none-eabi/include/sys/lock.h"
732 .file 9 "/usr/arm-none-eabi/include/sys/_types.h"
733 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h"
734 .file 11 "/usr/arm-none-eabi/include/sys/reent.h"
735 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h"
ARM GAS /tmp/ccd4VzkJ.s page 44
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32l0xx_hal_cortex.c
/tmp/ccd4VzkJ.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t
/tmp/ccd4VzkJ.s:23 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
/tmp/ccd4VzkJ.s:111 .text.HAL_NVIC_SetPriority:0000000000000058 $d
/tmp/ccd4VzkJ.s:119 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t
/tmp/ccd4VzkJ.s:126 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ
/tmp/ccd4VzkJ.s:153 .text.HAL_NVIC_EnableIRQ:0000000000000010 $d
/tmp/ccd4VzkJ.s:158 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t
/tmp/ccd4VzkJ.s:165 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ
/tmp/ccd4VzkJ.s:193 .text.HAL_NVIC_DisableIRQ:0000000000000010 $d
/tmp/ccd4VzkJ.s:198 .text.HAL_NVIC_SystemReset:0000000000000000 $t
/tmp/ccd4VzkJ.s:205 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset
/tmp/ccd4VzkJ.s:256 .text.HAL_NVIC_SystemReset:0000000000000014 $d
/tmp/ccd4VzkJ.s:266 .text.HAL_SYSTICK_Config:0000000000000000 $t
/tmp/ccd4VzkJ.s:273 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config
/tmp/ccd4VzkJ.s:337 .text.HAL_SYSTICK_Config:000000000000002c $d
/tmp/ccd4VzkJ.s:344 .text.HAL_NVIC_GetPriority:0000000000000000 $t
/tmp/ccd4VzkJ.s:351 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority
/tmp/ccd4VzkJ.s:413 .text.HAL_NVIC_GetPriority:0000000000000044 $d
/tmp/ccd4VzkJ.s:421 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t
/tmp/ccd4VzkJ.s:428 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ
/tmp/ccd4VzkJ.s:457 .text.HAL_NVIC_SetPendingIRQ:0000000000000014 $d
/tmp/ccd4VzkJ.s:462 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t
/tmp/ccd4VzkJ.s:469 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ
/tmp/ccd4VzkJ.s:499 .text.HAL_NVIC_GetPendingIRQ:0000000000000014 $d
/tmp/ccd4VzkJ.s:504 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t
/tmp/ccd4VzkJ.s:511 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccd4VzkJ.s:540 .text.HAL_NVIC_ClearPendingIRQ:0000000000000014 $d
/tmp/ccd4VzkJ.s:545 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t
/tmp/ccd4VzkJ.s:552 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccd4VzkJ.s:584 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d
/tmp/ccd4VzkJ.s:589 .text.HAL_SYSTICK_Callback:0000000000000000 $t
/tmp/ccd4VzkJ.s:596 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback
/tmp/ccd4VzkJ.s:610 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t
/tmp/ccd4VzkJ.s:617 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler
/tmp/ccd4VzkJ.s:638 .text.HAL_MPU_ConfigRegion:0000000000000000 $t
/tmp/ccd4VzkJ.s:645 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion
/tmp/ccd4VzkJ.s:721 .text.HAL_MPU_ConfigRegion:0000000000000050 $d
.debug_frame:0000000000000010 $d
NO UNDEFINED SYMBOLS