From 2cad6ccf4dda3a563b10f6988ed4d07935896945 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ond=C5=99ej=20Hru=C5=A1ka?= <ondra@ondrovo.com>
Date: Thu, 2 Nov 2017 19:18:34 +0100
Subject: [PATCH] add some fils

---
 .cproject                                     |   99 +-
 .gitignore                                    |    0
 .mxproject                                    |    0
 .project                                      |    0
 .settings/language.settings.xml               |    4 +-
 .settings/org.eclipse.cdt.codan.core.prefs    |    0
 Bees3 Debug.cfg                               |   28 +
 CMakeLists.txt                                |    0
 .../Device/ST/STM32L0xx/Include/stm32l073xx.h |    0
 .../Device/ST/STM32L0xx/Include/stm32l0xx.h   |    0
 .../ST/STM32L0xx/Include/system_stm32l0xx.h   |    0
 Drivers/CMSIS/Include/arm_common_tables.h     |    0
 Drivers/CMSIS/Include/arm_const_structs.h     |    0
 Drivers/CMSIS/Include/arm_math.h              |    0
 Drivers/CMSIS/Include/cmsis_armcc.h           |    0
 Drivers/CMSIS/Include/cmsis_armcc_V6.h        |    0
 Drivers/CMSIS/Include/cmsis_gcc.h             |    0
 Drivers/CMSIS/Include/core_cm0.h              |    0
 Drivers/CMSIS/Include/core_cm0plus.h          |    0
 Drivers/CMSIS/Include/core_cm3.h              |    0
 Drivers/CMSIS/Include/core_cm4.h              |    0
 Drivers/CMSIS/Include/core_cm7.h              |    0
 Drivers/CMSIS/Include/core_cmFunc.h           |    0
 Drivers/CMSIS/Include/core_cmInstr.h          |    0
 Drivers/CMSIS/Include/core_cmSimd.h           |    0
 Drivers/CMSIS/Include/core_sc000.h            |    0
 Drivers/CMSIS/Include/core_sc300.h            |    0
 .../Inc/Legacy/stm32_hal_legacy.h             |    0
 .../Inc/stm32_assert_template-h               |   73 +
 .../STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h  |    4 -
 .../Inc/stm32l0xx_hal_adc.h                   | 1137 +++++
 .../Inc/stm32l0xx_hal_adc_ex.h                |  229 +
 .../Inc/stm32l0xx_hal_comp.h                  |  683 +++
 .../Inc/stm32l0xx_hal_comp_ex.h               |   89 +
 .../Inc/stm32l0xx_hal_conf_template.h         |  314 ++
 .../Inc/stm32l0xx_hal_cortex.h                |    0
 .../Inc/stm32l0xx_hal_crc.h                   |  382 ++
 .../Inc/stm32l0xx_hal_crc_ex.h                |  174 +
 .../Inc/stm32l0xx_hal_cryp.h                  |  427 ++
 .../Inc/stm32l0xx_hal_cryp_ex.h               |   97 +
 .../Inc/stm32l0xx_hal_dac.h                   |  441 ++
 .../Inc/stm32l0xx_hal_dac_ex.h                |  183 +
 .../Inc/stm32l0xx_hal_def.h                   |    2 -
 .../Inc/stm32l0xx_hal_dma.h                   |    0
 .../Inc/stm32l0xx_hal_firewall.h              |  384 ++
 .../Inc/stm32l0xx_hal_flash.h                 |    0
 .../Inc/stm32l0xx_hal_flash_ex.h              |    0
 .../Inc/stm32l0xx_hal_flash_ramfunc.h         |    0
 .../Inc/stm32l0xx_hal_gpio.h                  |    0
 .../Inc/stm32l0xx_hal_gpio_ex.h               |    0
 .../Inc/stm32l0xx_hal_i2c.h                   |    0
 .../Inc/stm32l0xx_hal_i2c_ex.h                |    0
 .../Inc/stm32l0xx_hal_i2s.h                   |  479 ++
 .../Inc/stm32l0xx_hal_irda.h                  |  843 ++++
 .../Inc/stm32l0xx_hal_irda_ex.h               |  209 +
 .../Inc/stm32l0xx_hal_iwdg.h                  |  255 ++
 .../Inc/stm32l0xx_hal_lcd.h                   |  804 ++++
 .../Inc/stm32l0xx_hal_lptim.h                 |  743 +++
 .../Inc/stm32l0xx_hal_lptim_ex.h              |  133 +
 .../Inc/stm32l0xx_hal_pcd.h                   |  808 ++++
 .../Inc/stm32l0xx_hal_pcd_ex.h                |  115 +
 .../Inc/stm32l0xx_hal_pwr.h                   |    0
 .../Inc/stm32l0xx_hal_pwr_ex.h                |    0
 .../Inc/stm32l0xx_hal_rcc.h                   |    0
 .../Inc/stm32l0xx_hal_rcc_ex.h                |    0
 .../Inc/stm32l0xx_hal_rng.h                   |  308 ++
 .../Inc/stm32l0xx_hal_rtc.h                   |    0
 .../Inc/stm32l0xx_hal_rtc_ex.h                |    0
 .../Inc/stm32l0xx_hal_smartcard.h             | 1095 +++++
 .../Inc/stm32l0xx_hal_smartcard_ex.h          |  188 +
 .../Inc/stm32l0xx_hal_smbus.h                 |  699 +++
 .../Inc/stm32l0xx_hal_spi.h                   |    0
 .../Inc/stm32l0xx_hal_tim.h                   |    0
 .../Inc/stm32l0xx_hal_tim_ex.h                |    0
 .../Inc/stm32l0xx_hal_tsc.h                   |  659 +++
 .../Inc/stm32l0xx_hal_uart.h                  |    0
 .../Inc/stm32l0xx_hal_uart_ex.h               |    0
 .../Inc/stm32l0xx_hal_usart.h                 |  710 +++
 .../Inc/stm32l0xx_hal_usart_ex.h              |  297 ++
 .../Inc/stm32l0xx_hal_wwdg.h                  |  283 ++
 .../Inc/stm32l0xx_ll_adc.h                    | 4049 +++++++++++++++++
 .../Inc/stm32l0xx_ll_bus.h                    | 1187 +++++
 .../Inc/stm32l0xx_ll_comp.h                   |  721 +++
 .../Inc/stm32l0xx_ll_cortex.h                 |  606 +++
 .../Inc/stm32l0xx_ll_crc.h                    |  477 ++
 .../Inc/stm32l0xx_ll_crs.h                    |  814 ++++
 .../Inc/stm32l0xx_ll_dac.h                    | 1434 ++++++
 .../Inc/stm32l0xx_ll_dma.h                    | 2153 +++++++++
 .../Inc/stm32l0xx_ll_exti.h                   | 1032 +++++
 .../Inc/stm32l0xx_ll_gpio.h                   |  959 ++++
 .../Inc/stm32l0xx_ll_i2c.h                    | 2244 +++++++++
 .../Inc/stm32l0xx_ll_iwdg.h                   |  361 ++
 .../Inc/stm32l0xx_ll_lptim.h                  | 1380 ++++++
 .../Inc/stm32l0xx_ll_lpuart.h                 | 2153 +++++++++
 .../Inc/stm32l0xx_ll_pwr.h                    |  759 +++
 .../Inc/stm32l0xx_ll_rcc.h                    | 2514 ++++++++++
 .../Inc/stm32l0xx_ll_rng.h                    |  353 ++
 .../Inc/stm32l0xx_ll_rtc.h                    | 3860 ++++++++++++++++
 .../Inc/stm32l0xx_ll_spi.h                    | 2036 +++++++++
 .../Inc/stm32l0xx_ll_system.h                 | 1108 +++++
 .../Inc/stm32l0xx_ll_tim.h                    | 3340 ++++++++++++++
 .../Inc/stm32l0xx_ll_usart.h                  | 3720 +++++++++++++++
 .../Inc/stm32l0xx_ll_utils.h                  |  284 ++
 .../Inc/stm32l0xx_ll_wwdg.h                   |  340 ++
 .../STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c  |    0
 .../Src/stm32l0xx_hal_adc.c                   | 2196 +++++++++
 .../Src/stm32l0xx_hal_adc_ex.c                |  361 ++
 .../Src/stm32l0xx_hal_comp.c                  |  824 ++++
 .../Src/stm32l0xx_hal_comp_ex.c               |  149 +
 .../Src/stm32l0xx_hal_cortex.c                |    0
 .../Src/stm32l0xx_hal_crc.c                   |  550 +++
 .../Src/stm32l0xx_hal_crc_ex.c                |  238 +
 .../Src/stm32l0xx_hal_cryp.c                  | 2177 +++++++++
 .../Src/stm32l0xx_hal_cryp_ex.c               |  118 +
 .../Src/stm32l0xx_hal_dac.c                   |  726 +++
 .../Src/stm32l0xx_hal_dac_ex.c                | 1049 +++++
 .../Src/stm32l0xx_hal_dma.c                   |    0
 .../Src/stm32l0xx_hal_firewall.c              |  305 ++
 .../Src/stm32l0xx_hal_flash.c                 |    0
 .../Src/stm32l0xx_hal_flash_ex.c              |    0
 .../Src/stm32l0xx_hal_flash_ramfunc.c         |    0
 .../Src/stm32l0xx_hal_gpio.c                  |    0
 .../Src/stm32l0xx_hal_i2c.c                   |    0
 .../Src/stm32l0xx_hal_i2c_ex.c                |    0
 .../Src/stm32l0xx_hal_i2s.c                   | 1436 ++++++
 .../Src/stm32l0xx_hal_irda.c                  | 2357 ++++++++++
 .../Src/stm32l0xx_hal_iwdg.c                  |  280 ++
 .../Src/stm32l0xx_hal_lcd.c                   |  625 +++
 .../Src/stm32l0xx_hal_lptim.c                 | 1654 +++++++
 .../Src/stm32l0xx_hal_msp_template-c          |  123 +
 .../Src/stm32l0xx_hal_pcd.c                   | 1431 ++++++
 .../Src/stm32l0xx_hal_pcd_ex.c                |  318 ++
 .../Src/stm32l0xx_hal_pwr.c                   |    0
 .../Src/stm32l0xx_hal_pwr_ex.c                |    0
 .../Src/stm32l0xx_hal_rcc.c                   |    0
 .../Src/stm32l0xx_hal_rcc_ex.c                |    0
 .../Src/stm32l0xx_hal_rng.c                   |  523 +++
 .../Src/stm32l0xx_hal_rtc.c                   |    0
 .../Src/stm32l0xx_hal_rtc_ex.c                |    0
 .../Src/stm32l0xx_hal_smartcard.c             | 2291 ++++++++++
 .../Src/stm32l0xx_hal_smartcard_ex.c          |  207 +
 .../Src/stm32l0xx_hal_smbus.c                 | 2161 +++++++++
 .../Src/stm32l0xx_hal_spi.c                   |    0
 .../Src/stm32l0xx_hal_tim.c                   |    0
 .../Src/stm32l0xx_hal_tim_ex.c                |    0
 .../Src/stm32l0xx_hal_tsc.c                   |  817 ++++
 .../Src/stm32l0xx_hal_uart.c                  |    0
 .../Src/stm32l0xx_hal_uart_ex.c               |    0
 .../Src/stm32l0xx_hal_usart.c                 | 2420 ++++++++++
 .../Src/stm32l0xx_hal_wwdg.c                  |  320 ++
 .../Src/stm32l0xx_ll_adc.c                    |  658 +++
 .../Src/stm32l0xx_ll_comp.c                   |  323 ++
 .../Src/stm32l0xx_ll_crc.c                    |  123 +
 .../Src/stm32l0xx_ll_crs.c                    |  102 +
 .../Src/stm32l0xx_ll_dac.c                    |  282 ++
 .../Src/stm32l0xx_ll_dma.c                    |  395 ++
 .../Src/stm32l0xx_ll_exti.c                   |  230 +
 .../Src/stm32l0xx_ll_gpio.c                   |  281 ++
 .../Src/stm32l0xx_ll_i2c.c                    |  255 ++
 .../Src/stm32l0xx_ll_lptim.c                  |  210 +
 .../Src/stm32l0xx_ll_lpuart.c                 |  257 ++
 .../Src/stm32l0xx_ll_pwr.c                    |  101 +
 .../Src/stm32l0xx_ll_rcc.c                    |  650 +++
 .../Src/stm32l0xx_ll_rng.c                    |  114 +
 .../Src/stm32l0xx_ll_rtc.c                    |  895 ++++
 .../Src/stm32l0xx_ll_spi.c                    |  532 +++
 .../Src/stm32l0xx_ll_tim.c                    |  864 ++++
 .../Src/stm32l0xx_ll_usart.c                  |  433 ++
 .../Src/stm32l0xx_ll_utils.c                  |  575 +++
 Inc/main.h                                    |    0
 .../Third_Party/Lora/Utilities/utilities.h    |    8 +-
 NUCLEO-L073RZ.xml                             |    0
 STM32L073RZTx_FLASH.ld                        |    0
 Src/main.c                                    |   14 +-
 Src/stm32l0xx_hw.c                            |    2 +-
 Src/system_stm32l0xx.c                        |  285 ++
 junk/gpio.c                                   |    0
 junk/gpio.h                                   |    0
 junk/i2c.c                                    |    0
 junk/i2c.h                                    |    0
 junk/main.c                                   |    0
 junk/rtc.c                                    |    0
 junk/rtc.h                                    |    0
 junk/spi.c                                    |    0
 junk/spi.h                                    |    0
 junk/stm32l0xx_hal_conf.h                     |    0
 junk/stm32l0xx_hal_msp.c-mx                   |    0
 junk/stm32l0xx_it.c-mx                        |    0
 junk/stm32l0xx_it.h                           |    0
 junk/system_stm32l0xx.c-                      |    0
 junk/usart.c                                  |    0
 junk/usart.h                                  |    0
 mx.scratch                                    |    0
 proj Debug.cfg                                |    0
 proj.ioc                                      |    0
 startup/startup_stm32l073xx.s                 |    0
 196 files changed, 84486 insertions(+), 21 deletions(-)
 mode change 100644 => 100755 .cproject
 mode change 100644 => 100755 .gitignore
 mode change 100644 => 100755 .mxproject
 mode change 100644 => 100755 .project
 mode change 100644 => 100755 .settings/language.settings.xml
 mode change 100644 => 100755 .settings/org.eclipse.cdt.codan.core.prefs
 create mode 100644 Bees3 Debug.cfg
 mode change 100644 => 100755 CMakeLists.txt
 mode change 100644 => 100755 Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
 mode change 100644 => 100755 Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h
 mode change 100644 => 100755 Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/arm_common_tables.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/arm_const_structs.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/arm_math.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/cmsis_armcc.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/cmsis_armcc_V6.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/cmsis_gcc.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cm0.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cm0plus.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cm3.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cm4.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cm7.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cmFunc.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cmInstr.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_cmSimd.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_sc000.h
 mode change 100644 => 100755 Drivers/CMSIS/Include/core_sc300.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32_assert_template-h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template-c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c
 mode change 100644 => 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
 create mode 100755 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
 mode change 100644 => 100755 Inc/main.h
 mode change 100644 => 100755 NUCLEO-L073RZ.xml
 mode change 100644 => 100755 STM32L073RZTx_FLASH.ld
 create mode 100755 Src/system_stm32l0xx.c
 mode change 100644 => 100755 junk/gpio.c
 mode change 100644 => 100755 junk/gpio.h
 mode change 100644 => 100755 junk/i2c.c
 mode change 100644 => 100755 junk/i2c.h
 mode change 100644 => 100755 junk/main.c
 mode change 100644 => 100755 junk/rtc.c
 mode change 100644 => 100755 junk/rtc.h
 mode change 100644 => 100755 junk/spi.c
 mode change 100644 => 100755 junk/spi.h
 mode change 100644 => 100755 junk/stm32l0xx_hal_conf.h
 mode change 100644 => 100755 junk/stm32l0xx_hal_msp.c-mx
 mode change 100644 => 100755 junk/stm32l0xx_it.c-mx
 mode change 100644 => 100755 junk/stm32l0xx_it.h
 mode change 100644 => 100755 junk/system_stm32l0xx.c-
 mode change 100644 => 100755 junk/usart.c
 mode change 100644 => 100755 junk/usart.h
 mode change 100644 => 100755 mx.scratch
 mode change 100644 => 100755 proj Debug.cfg
 mode change 100644 => 100755 proj.ioc
 mode change 100644 => 100755 startup/startup_stm32l073xx.s

diff --git a/.cproject b/.cproject
old mode 100644
new mode 100755
index 76bb2bb..062384e
--- a/.cproject
+++ b/.cproject
@@ -38,12 +38,20 @@
 									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Core"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Crypto"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Phy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Utilities"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac/region"/>
 								</option>
 								<option id="gnu.c.compiler.option.preprocessor.def.symbols.248526217" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="__weak=&quot;__attribute__((weak))&quot;"/>
 									<listOptionValue builtIn="false" value="__packed=&quot;__attribute__((__packed__))&quot;"/>
-									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
-									<listOptionValue builtIn="false" value="STM32L073xx"/>
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER=1"/>
+									<listOptionValue builtIn="false" value="STM32L073xx=1"/>
+									<listOptionValue builtIn="false" value="ARM_MATH_CM0=1"/>
+									<listOptionValue builtIn="false" value="REGION_EU868=1"/>
 								</option>
 								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.misc.other.193137038" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-fmessage-length=0" valueType="string"/>
 								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.336960885" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
@@ -72,11 +80,90 @@
 							</tool>
 						</toolChain>
 					</folderInfo>
+					<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1636346117.1680818898" name="/" resourcePath="Drivers/BSP/Components/sx1272">
+						<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug.1085503164" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug" unusedChildren="">
+							<option id="fr.ac6.managedbuild.option.gnu.cross.prefix.791131379.1458908717" name="Prefix" superClass="fr.ac6.managedbuild.option.gnu.cross.prefix.791131379"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.2087208385.87840295" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu.2087208385"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.board.465889387.915431321" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board.465889387"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.instructionSet.1756422888.2056861028" name="Instruction Set" superClass="fr.ac6.managedbuild.option.gnu.cross.instructionSet.1756422888"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.fpu.429835822.751588825" name="Floating point hardware" superClass="fr.ac6.managedbuild.option.gnu.cross.fpu.429835822"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.1613299758.1358594047" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi.1613299758"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.682286040" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677">
+								<option id="gnu.c.compiler.option.include.paths.1407158377" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Core"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Crypto"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Phy"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Utilities"/>
+									<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac/region"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/Components/sx1272"/>
+									<listOptionValue builtIn="false" value="../Drivers/BSP/sx1272mb2das/"/>
+								</option>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.1786322897" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.2069713447" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
+							</tool>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.23580943" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.1942740107"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.linker.1985391927" name="MCU GCC Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.linker.1585341127"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.753463299" name="MCU G++ Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.996257263"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.archiver.1425870723" name="MCU GCC Archiver" superClass="fr.ac6.managedbuild.tool.gnu.archiver.883778798"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.assembler.1532531737" name="MCU GCC Assembler" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.471130259">
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.789657598" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.1125779733" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<fileInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1636346117.1230981831" name="sx1272mb2das.c" rcbsApplicability="disable" resourcePath="Drivers/BSP/sx1272mb2das/sx1272mb2das.c" toolsToInvoke="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677.890206082">
+						<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677.890206082" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677">
+							<option id="gnu.c.compiler.option.include.paths.1630368414" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+								<listOptionValue builtIn="false" value="../Inc"/>
+								<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
+								<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy"/>
+								<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
+								<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Core"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Crypto"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Phy"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Utilities"/>
+								<listOptionValue builtIn="false" value="../Middlewares/Third_Party/Lora/Mac/region"/>
+								<listOptionValue builtIn="false" value="../Drivers/BSP/Components/sx1272"/>
+								<listOptionValue builtIn="false" value="../Drivers/BSP/sx1272mb2das"/>
+							</option>
+							<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.1713066265" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
+							<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.1095488994" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
+						</tool>
+					</fileInfo>
+					<fileInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1636346117.891745609" name="low_power.c" rcbsApplicability="disable" resourcePath="Middlewares/Third_Party/Lora/Utilities/low_power.c" toolsToInvoke="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677.463780228">
+						<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677.463780228" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.377147677">
+							<option id="gnu.c.compiler.option.preprocessor.def.symbols.1938548990" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+								<listOptionValue builtIn="false" value="__weak=&quot;__attribute__((weak))&quot;"/>
+								<listOptionValue builtIn="false" value="__packed=&quot;__attribute__((__packed__))&quot;"/>
+								<listOptionValue builtIn="false" value="USE_HAL_DRIVER=1"/>
+								<listOptionValue builtIn="false" value="STM32L073xx=1"/>
+								<listOptionValue builtIn="false" value="ARM_MATH_CM0=1"/>
+								<listOptionValue builtIn="false" value="REGION_EU868=1"/>
+								<listOptionValue builtIn="false" value="DEBUG=1"/>
+							</option>
+							<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.998724722" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
+							<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.1992215065" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
+						</tool>
+					</fileInfo>
 					<sourceEntries>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Inc"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Middlewares/Third_Party/Lora/Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Middlewares/Third_Party/Lora/Crypto"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Middlewares/Third_Party/Lora/Mac"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Middlewares/Third_Party/Lora/Phy"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Middlewares/Third_Party/Lora/Utilities"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -154,10 +241,10 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
-						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
 						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Inc"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
diff --git a/.gitignore b/.gitignore
old mode 100644
new mode 100755
diff --git a/.mxproject b/.mxproject
old mode 100644
new mode 100755
diff --git a/.project b/.project
old mode 100644
new mode 100755
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
old mode 100644
new mode 100755
index 98a02b0..f791c8f
--- a/.settings/language.settings.xml
+++ b/.settings/language.settings.xml
@@ -6,7 +6,7 @@
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
 			<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
-			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1807606491226787064" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -18,7 +18,7 @@
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
 			<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
-			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1807606491226787064" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs
old mode 100644
new mode 100755
diff --git a/Bees3 Debug.cfg b/Bees3 Debug.cfg
new file mode 100644
index 0000000..602e082
--- /dev/null
+++ b/Bees3 Debug.cfg	
@@ -0,0 +1,28 @@
+# This is an NUCLEO-L073RZ board with a single STM32L073RZTx chip
+#
+# Generated by System Workbench for STM32
+# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
+
+source [find interface/stlink.cfg] 
+
+set WORKAREASIZE 0x5000
+
+transport select "hla_swd"
+
+set CHIPNAME STM32L073RZTx
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 4000
+
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+
+source [find target/stm32l0x.cfg]
diff --git a/CMakeLists.txt b/CMakeLists.txt
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h b/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/arm_common_tables.h b/Drivers/CMSIS/Include/arm_common_tables.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/arm_const_structs.h b/Drivers/CMSIS/Include/arm_const_structs.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/arm_math.h b/Drivers/CMSIS/Include/arm_math.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/Drivers/CMSIS/Include/cmsis_armcc_V6.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cmFunc.h b/Drivers/CMSIS/Include/core_cmFunc.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cmInstr.h b/Drivers/CMSIS/Include/core_cmInstr.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_cmSimd.h b/Drivers/CMSIS/Include/core_cmSimd.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h
old mode 100644
new mode 100755
diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32_assert_template-h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32_assert_template-h
new file mode 100755
index 0000000..4ae7e25
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32_assert_template-h
@@ -0,0 +1,73 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
old mode 100644
new mode 100755
index 5c98c3f..f3c7367
--- a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
@@ -43,10 +43,6 @@
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-
-// added
-#include <stm32l073xx.h>
-
 #include "stm32l0xx_hal_conf.h"
 
 /** @addtogroup STM32L0xx_HAL_Driver
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
new file mode 100755
index 0000000..b68e202
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc.h
@@ -0,0 +1,1137 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_ADC_H
+#define __STM32L0xx_HAL_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_Oversampling_Ratio */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_Right_Bit_Shift */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
+}ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter 
+  *         (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_ClockPrescaler.
+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
+                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 
+                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
+                                       Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
+                                       Note: This parameter can be modified only if the ADC is disabled. */
+
+  uint32_t Resolution;            /*!< Configure the ADC resolution. 
+                                       This parameter can be a value of @ref ADC_Resolution */
+
+  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
+                                       Refer to reference manual for alignments formats versus resolutions.
+                                       This parameter can be a value of @ref ADC_Data_align */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of regular group.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+                                       Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
+                                       If only 1 channel is set: Conversion is performed in single mode.
+                                       If several channels are set:  Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                                                     Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  uint32_t LowPowerAutoWait;      /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
+                                       conversion (for ADC group regular) has been retrieved by user software,
+                                       using function HAL_ADC_GetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
+                                       for low frequency applications. 
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
+                                             to free the IRQ vector sequencer.
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
+
+  uint32_t LowPowerAutoPowerOff;  /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
+
+  uint32_t ContinuousConvMode;    /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+                                       after the first ADC conversion start trigger occurred (software start or external trigger).
+                                       This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
+                                       (main sequence subdivided in successive parts).
+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+                                                                                                        
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter can be a value of @ref ADC_Overrun.
+                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 
+                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 
+                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 
+                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+
+  uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
+                                       it is mandatory to first enable the Low Frequency Mode.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: This parameter can be modified only if there is no conversion is ongoing. */
+
+
+  uint32_t SamplingTime;                 /*!< The sample time common to all channels.
+                                              Unit: ADC clock cycles
+                                              This parameter can be a value of @ref ADC_sampling_times
+                                              Note: This parameter can be modified only if there is no conversion ongoing. */
+
+  uint32_t OversamplingMode;              /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
+
+
+  ADC_OversamplingTypeDef  Oversample;   /*!< Specify the Oversampling parameters
+                                              Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+}ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_channels
+                                        Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+  uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer. 
+                                        On STM32L0 devices,  number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number 
+                                        (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                        Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+                                        This parameter can be a value of @ref ADC_rank */
+}ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
+  *          - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
+  */
+typedef struct
+{
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all channels.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+                                   This parameter can be a value of @ref ADC_channels */
+
+  uint32_t ITMode;            /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                   this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+                                   this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Not available on this STM32 serie: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Not available on this STM32 serie: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
+
+
+
+/** 
+  * @brief  ADC handle Structure definition
+  */
+typedef struct
+{
+  ADC_TypeDef                   *Instance;              /*!< Register base address */
+
+  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
+
+  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
+
+  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
+
+  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
+
+  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
+}ADC_HandleTypeDef;
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error (problem of clocking,
+                                                          enable/disable, erroneous state, ...)        */
+#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                          */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
+  * @{
+  */
+
+  /* Fixed timeout values for ADC calibration, enable settling time, disable  */
+  /* settling time.                                                           */
+  /* Values defined to be higher than worst cases: low clocks freq,           */
+  /* maximum prescalers.                                                      */
+  /* Unit: ms                                                                 */      
+#define ADC_ENABLE_TIMEOUT            10U
+#define ADC_DISABLE_TIMEOUT           10U
+#define ADC_STOP_CONVERSION_TIMEOUT   10U
+
+  /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have  */
+  /* the minimum number of CPU cycles to fulfill this delay                   */
+  #define ADC_DELAY_10US_MIN_CPU_CYCLES         1800U 
+/**
+  * @}
+  */
+
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
+  * @{
+  */     
+#define ADC_CLOCK_ASYNC_DIV1              ((uint32_t)0x00000000U)                               /*!< ADC Asynchronous clock mode divided by 1 */
+#define ADC_CLOCK_ASYNC_DIV2              (ADC_CCR_PRESC_0)                                     /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV4              (ADC_CCR_PRESC_1)                                     /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV6              (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV8              (ADC_CCR_PRESC_2)                                     /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV10             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV12             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1)                   /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV16             (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV32             (ADC_CCR_PRESC_3)                                     /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV64             (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV128            (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC Asynchronous clock mode divided by 2 */
+#define ADC_CLOCK_ASYNC_DIV256            (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
+
+#define ADC_CLOCK_SYNC_PCLK_DIV1         ((uint32_t)ADC_CFGR2_CKMODE)    /*!< Synchronous clock mode divided by 1 
+                                                                               This configuration must be enabled only if PCLK has a 50%
+                                                                               duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
+                                                                               must by 50% duty cycle)*/
+#define ADC_CLOCK_SYNC_PCLK_DIV2         ((uint32_t)ADC_CFGR2_CKMODE_0)  /*!< Synchronous clock mode divided by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4         ((uint32_t)ADC_CFGR2_CKMODE_1)  /*!< Synchronous clock mode divided by 4 */
+
+/**                                                       
+  * @}
+  */ 
+
+/** @defgroup ADC_Resolution ADC Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B      ((uint32_t)0x00000000U)          /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B      ((uint32_t)ADC_CFGR1_RES_0)      /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B       ((uint32_t)ADC_CFGR1_RES_1)      /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B       ((uint32_t)ADC_CFGR1_RES)        /*!< ADC 6-bit resolution */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Data_align ADC conversion data alignment
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)
+#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CFGR1_ALIGN)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CFGR1_EXTEN_0)         
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CFGR1_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CFGR1_EXTEN)
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_EOCSelection ADC EOC Selection
+  * @{
+  */ 
+#define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
+#define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< reserved for future use */
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Overrun ADC Overrun
+  * @{
+  */ 
+#define ADC_OVR_DATA_PRESERVED              ((uint32_t)0x00000000U)
+#define ADC_OVR_DATA_OVERWRITTEN            ((uint32_t)ADC_CFGR1_OVRMOD)
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_rank ADC rank
+  * @{
+  */
+#define ADC_RANK_CHANNEL_NUMBER                 ((uint32_t)0x00001000U)  /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE                           ((uint32_t)0x00001001U)  /*!< Disable the selected rank (selected channel) from sequencer */
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_channels ADC_Channels
+  * @{
+  */
+#define ADC_CHANNEL_0           ((uint32_t)(ADC_CHSELR_CHSEL0))
+#define ADC_CHANNEL_1           ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_2           ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
+#define ADC_CHANNEL_3           ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_4           ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
+#define ADC_CHANNEL_5           ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_6           ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
+#define ADC_CHANNEL_7           ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_8           ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
+#define ADC_CHANNEL_9           ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_10          ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
+#define ADC_CHANNEL_11          ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_12          ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
+#define ADC_CHANNEL_13          ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_14          ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
+#define ADC_CHANNEL_15          ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+#define ADC_CHANNEL_16          ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
+#endif
+#define ADC_CHANNEL_17          ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_18          ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
+
+/* Internal channels */
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+#define ADC_CHANNEL_VLCD         ADC_CHANNEL_16    
+#endif
+#define ADC_CHANNEL_VREFINT      ADC_CHANNEL_17
+#define ADC_CHANNEL_TEMPSENSOR   ADC_CHANNEL_18    
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
+  * @{
+  */
+#define ADC_CHANNEL_MASK        ((uint32_t)0x0007FFFFU)
+#define ADC_CHANNEL_AWD_MASK    ((uint32_t)0x7C000000U)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_times ADC Sampling Cycles
+  * @{
+  */
+#define ADC_SAMPLETIME_1CYCLE_5       ((uint32_t)0x00000000U)                         /*!<  ADC sampling time 1.5 cycle */
+#define ADC_SAMPLETIME_3CYCLES_5      ((uint32_t)ADC_SMPR_SMPR_0)                     /*!<  ADC sampling time 3.5 CYCLES */
+#define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t)ADC_SMPR_SMPR_1)                     /*!<  ADC sampling time 7.5 CYCLES */
+#define ADC_SAMPLETIME_12CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!<  ADC sampling time 12.5 CYCLES */
+#define ADC_SAMPLETIME_19CYCLES_5     ((uint32_t)ADC_SMPR_SMPR_2)                     /*!<  ADC sampling time 19.5 CYCLES */
+#define ADC_SAMPLETIME_39CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!<  ADC sampling time 39.5 CYCLES */
+#define ADC_SAMPLETIME_79CYCLES_5     ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!<  ADC sampling time 79.5 CYCLES */
+#define ADC_SAMPLETIME_160CYCLES_5    ((uint32_t)ADC_SMPR_SMPR)                       /*!<  ADC sampling time 160.5 CYCLES */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC Scan mode
+  * @{
+  */
+/* Note: Scan mode values must be compatible with other STM32 devices having  */
+/*       a configurable sequencer.                                            */
+/*       Scan direction setting values are defined by taking in account       */
+/*       already defined values for other STM32 devices:                      */
+/*         ADC_SCAN_DISABLE         ((uint32_t)0x00000000)                    */
+/*         ADC_SCAN_ENABLE          ((uint32_t)0x00000001)                    */
+/*       Scan direction forward is considered as default setting equivalent   */
+/*       to scan enable.                                                      */
+/*       Scan direction backward is considered as additional setting.         */
+/*       In case of migration from another STM32 device, the user will be     */
+/*       warned of change of setting choices with assert check.               */
+#define ADC_SCAN_DIRECTION_FORWARD        ((uint32_t)0x00000001U)        /*!< Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_DIRECTION_BACKWARD       ((uint32_t)0x00000002U)        /*!< Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_ENABLE         ADC_SCAN_DIRECTION_FORWARD             /* For compatibility with other STM32 devices */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
+  * @{
+  */
+
+#define ADC_OVERSAMPLING_RATIO_2                    ((uint32_t)0x00000000U)  /*!<  ADC Oversampling ratio 2x */
+#define ADC_OVERSAMPLING_RATIO_4                    ((uint32_t)0x00000004U)  /*!<  ADC Oversampling ratio 4x */
+#define ADC_OVERSAMPLING_RATIO_8                    ((uint32_t)0x00000008U)  /*!<  ADC Oversampling ratio 8x */
+#define ADC_OVERSAMPLING_RATIO_16                   ((uint32_t)0x0000000CU)  /*!<  ADC Oversampling ratio 16x */
+#define ADC_OVERSAMPLING_RATIO_32                   ((uint32_t)0x00000010U)  /*!<  ADC Oversampling ratio 32x */
+#define ADC_OVERSAMPLING_RATIO_64                   ((uint32_t)0x00000014U)  /*!<  ADC Oversampling ratio 64x */
+#define ADC_OVERSAMPLING_RATIO_128                  ((uint32_t)0x00000018U)  /*!<  ADC Oversampling ratio 128x */
+#define ADC_OVERSAMPLING_RATIO_256                  ((uint32_t)0x0000001CU)  /*!<  ADC Oversampling ratio 256x */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
+  * @{
+  */
+#define ADC_RIGHTBITSHIFT_NONE                       ((uint32_t)0x00000000U)  /*!<  ADC No bit shift for oversampling */
+#define ADC_RIGHTBITSHIFT_1                          ((uint32_t)0x00000020U)  /*!<  ADC 1 bit shift for oversampling */
+#define ADC_RIGHTBITSHIFT_2                          ((uint32_t)0x00000040U)  /*!<  ADC 2 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_3                          ((uint32_t)0x00000060U)  /*!<  ADC 3 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_4                          ((uint32_t)0x00000080U)  /*!<  ADC 4 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_5                          ((uint32_t)0x000000A0U)  /*!<  ADC 5 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_6                          ((uint32_t)0x000000C0U)  /*!<  ADC 6 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_7                          ((uint32_t)0x000000E0U)  /*!<  ADC 7 bits shift for oversampling */
+#define ADC_RIGHTBITSHIFT_8                          ((uint32_t)0x00000100U)  /*!<  ADC 8 bits shift for oversampling */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER            ((uint32_t)0x00000000U)  /*!<  ADC No bit shift for oversampling */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER             ((uint32_t)0x00000200U)  /*!<  ADC No bit shift for oversampling */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+  * @{
+  */ 
+#define ADC_ANALOGWATCHDOG_NONE                     ((uint32_t) 0x00000000U)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG               ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG                  ((uint32_t) ADC_CFGR1_AWDEN)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_conversion_type ADC Conversion Group
+  * @{
+  */ 
+#define ADC_REGULAR_GROUP                         ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))                                              
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Event_type ADC Event
+  * @{
+  */
+#define ADC_AWD_EVENT              ((uint32_t)ADC_FLAG_AWD)
+#define ADC_OVR_EVENT              ((uint32_t)ADC_FLAG_OVR)
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE     /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE     /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE       /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSEQIE     /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE       /*!< ADC overrun interrupt source */
+#define ADC_IT_AWD           ADC_IER_AWDIE       /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IT_EOCAL         ADC_IER_EOCALIE     /*!< ADC End of Calibration interrupt source */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOSEQ    /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_AWD           ADC_ISR_AWD      /*!< ADC Analog watchdog flag */
+#define ADC_FLAG_EOCAL         ADC_ISR_EOCAL    /*!< ADC Enf Of Calibration flag */
+
+
+#define ADC_FLAG_ALL    (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS |  \
+                         ADC_FLAG_OVR | ADC_FLAG_AWD   | ADC_FLAG_EOCAL)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/** @brief Reset ADC handle state
+  * @param  __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+  * @brief Enable the ADC peripheral
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
+
+/**
+  * @brief Verification of hardware constraints before ADC can be enabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+  */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__)           \
+       (( ( ((__HANDLE__)->Instance->CR) &                  \
+            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \
+             ADC_CR_ADDIS | ADC_CR_ADEN )                   \
+           ) == RESET                                       \
+        ) ? SET : RESET)
+
+/**
+  * @brief Disable the ADC peripheral
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
+  do{                                                                          \
+         (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS;                           \
+          __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+  } while(0)
+    
+/**
+  * @brief Verification of hardware constraints before ADC can be disabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+  */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__)                             \
+       (( ( ((__HANDLE__)->Instance->CR) &                                     \
+            (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
+        ) ? SET : RESET)
+         
+/**
+  * @brief Verification of ADC state: enabled or disabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_IS_ENABLE(__HANDLE__)                                                    \
+       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
+        ) ? SET : RESET)
+         
+/**
+  * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__: ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+  (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+
+
+
+/**
+  * @brief Check if no conversion on going on regular group
+  * @param __HANDLE__: ADC handle
+  * @retval SET (conversion is on going) or RESET (no conversion is on going)
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
+  (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET                  \
+  ) ? RESET : SET)
+
+/**
+  * @brief Enable ADC continuous conversion mode.
+  * @param _CONTINUOUS_MODE_: Continuous mode.
+  * @retval None
+  */
+#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
+
+/**
+  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+  * @param _SCAN_MODE_: Scan conversion mode.
+  * @retval None
+  */
+#define ADC_SCANDIR(_SCAN_MODE_)                                   \
+  ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD)                           \
+    )? (ADC_CFGR1_SCANDIR) : (0x00000000U)                                      \
+  )
+
+/**
+  * @brief Configures the number of discontinuous conversions for the regular group channels.
+  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+  * @retval None
+  */
+#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
+
+/**
+  * @brief Enable the ADC DMA continuous request.
+  * @param _DMAContReq_MODE_: DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
+
+/**
+  * @brief Enable the ADC Auto Delay.
+  * @param _AutoDelay_: Auto delay bit enable or disable.
+  * @retval None
+  */
+#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
+
+/**
+  * @brief Enable the ADC LowPowerAutoPowerOff.
+  * @param _AUTOFF_: AutoOff bit enable or disable.
+  * @retval None
+  */
+#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
+
+/**
+  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+  * @param _Threshold_: Threshold value
+  * @retval None
+  */
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
+
+/**
+  * @brief Enable the ADC Low Frequency mode.
+  * @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
+  * @retval None
+  */
+#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
+
+/**
+  * @brief Shift the offset in function of the selected ADC resolution. 
+  *        Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the right.
+  *        If resolution 8 bits, shift of 4 ranks on the right.
+  *        If resolution 6 bits, shift of 6 ranks on the right.
+  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+  * @param __HANDLE__: ADC handle.
+  * @param _Offset_: Value to be shifted
+  * @retval None
+  */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
+        ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
+
+/**
+  * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
+  *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the right.
+  *        If resolution 8 bits, shift of 4 ranks on the right.
+  *        If resolution 6 bits, shift of 6 ranks on the right.
+  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+  * @param __HANDLE__: ADC handle.
+  * @param _Threshold_: Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+        ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
+
+/**
+  * @brief Shift the value on the left, less significant are set to 0. 
+  * @param _Value_: Value to be shifted
+  * @param _Shift_: Number of shift to be done
+  * @retval None
+  */
+#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
+
+
+/**
+  * @brief Enable the ADC end of conversion interrupt.
+  * @param __HANDLE__: ADC handle.
+  * @param __INTERRUPT__: ADC Interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)  \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable the ADC end of conversion interrupt.
+  * @param __HANDLE__: ADC handle.
+  * @param __INTERRUPT__: ADC interrupt.
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__: ADC handle
+  * @param __INTERRUPT__: ADC interrupt source to check
+  *            @arg ...
+  *            @arg ...
+  * @retval State of interruption (TRUE or FALSE)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief Clear the ADC's pending flags
+  * @param __HANDLE__: ADC handle.
+  * @param __FLAG__: ADC flag.
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+  * @brief Get the selected ADC's flag status.
+  * @param __HANDLE__: ADC handle.
+  * @param __FLAG__: ADC flag.
+  * @retval None
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+
+/**
+  * @brief Simultaneously clears and sets specific bits of the handle State
+  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Clear ADC error code (set it to error code: "no error")
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
+  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+
+/**
+  * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
+  * @param __HANDLE__: ADC handle
+  * @retval None
+  */
+
+#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__)                                       \
+  do{                                                                               \
+      if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) ||  \
+          (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) ||  \
+          (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4))    \
+      {                                                                             \
+        (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);                       \
+        (__HANDLE__)->Instance->CFGR2 |=  (__HANDLE__)->Init.ClockPrescaler;        \
+      }                                                                             \
+      else                                                                          \
+      {                                                                             \
+        /* CKMOD bits must be reset */                                              \
+        (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);                       \
+        ADC->CCR &= ~(ADC_CCR_PRESC);                                               \
+        ADC->CCR |=  (__HANDLE__)->Init.ClockPrescaler;                             \
+      }                                                                             \
+  } while(0)
+
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
+                                                ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+                                  ((ALIGN) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)   || \
+                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)      || \
+                                             ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+                               ((WATCHDOG) == ADC_RANK_NONE))
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
+                                 ((CHANNEL) == ADC_CHANNEL_VLCD))
+#else
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_VREFINT))
+#endif
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5   ) || \
+                                  ((TIME) == ADC_SAMPLETIME_3CYCLES_5  ) || \
+                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5  ) || \
+                                  ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \
+                                  ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \
+                                  ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \
+                                  ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \
+                                  ((TIME) == ADC_SAMPLETIME_160CYCLES_5))
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+                                     ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
+
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO)          (((RATIO) == ADC_OVERSAMPLING_RATIO_2   ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_4   ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_8   ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_16  ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_32  ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_64  ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
+                                                   ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
+
+#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT)               (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                     ((SHIFT) == ADC_RIGHTBITSHIFT_8   ))
+
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE)     (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)     (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE      )   || \
+                                                   ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)   || \
+                                                   ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG   ))
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION)   ((CONVERSION) == ADC_REGULAR_GROUP)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+                                  ((EVENT) == ADC_OVR_EVENT))
+
+
+/** @defgroup ADC_range_verification ADC Range Verification
+  * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+  * @{
+  */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
+   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \
+    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
+  * @{
+  */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32l0xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef    HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef    HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                 HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void                 HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef    HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef    HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef    HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef    HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef    HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef    HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef    HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef    HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t             HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                 HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void                 HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void                 HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void                 HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void                 HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef    HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef    HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t             HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__STM32L0xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
new file mode 100755
index 0000000..c88aeb8
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_adc_ex.h
@@ -0,0 +1,229 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_ADC_EX_H
+#define __STM32L0xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADCEx_Channel_Mode ADC Single Ended
+  * @{
+  */
+#define ADC_SINGLE_ENDED                        (uint32_t)0x00000000U   /* dummy value */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC External Trigger Source
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONV_T6_TRGO            ((uint32_t)0x00000000U)
+#define ADC_EXTERNALTRIGCONV_T21_CC2            (ADC_CFGR1_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T2_TRGO            (ADC_CFGR1_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_T2_CC4             (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
+#define ADC_EXTERNALTRIGCONV_T22_TRGO           (ADC_CFGR1_EXTSEL_2)
+#define ADC_EXTERNALTRIGCONV_T3_TRGO            (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1)
+#define ADC_EXTERNALTRIGCONV_EXT_IT11           (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)
+#define ADC_SOFTWARE_START                      (ADC_CFGR1_EXTSEL + (uint32_t)1)
+
+/* ADC group regular external trigger TIM21_TRGO available only on            */
+/* STM32L0 devices categories: Cat.2, Cat.3, Cat.5                            */
+#if defined (STM32L031xx) || defined (STM32L041xx) || \
+    defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
+    defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || \
+    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define ADC_EXTERNALTRIGCONV_T21_TRGO           (ADC_EXTERNALTRIGCONV_T22_TRGO)
+#endif
+
+/* ADC group regular external trigger TIM2_CC3 available only on              */
+/* STM32L0 devices categories: Cat.1, Cat.2, Cat.5                            */
+#if defined (STM32L011xx) || defined (STM32L021xx) || \
+    defined (STM32L031xx) || defined (STM32L041xx) || \
+    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define ADC_EXTERNALTRIGCONV_T2_CC3             (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_SYSCFG_internal_paths_flags_definition ADC SYSCFG internal paths Flags Definition
+  * @{
+  */
+#define ADC_FLAG_SENSOR         SYSCFG_CFGR3_VREFINT_RDYF
+#define ADC_FLAG_VREFINT        SYSCFG_VREFINT_ADC_RDYF
+/**
+  * @}
+  */
+   
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
+  * @{
+  */
+
+#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF)   ((SING_DIFF) == ADC_SINGLE_ENDED)
+
+/** @defgroup ADCEx_calibration_factor_length_verification ADC Calibration Factor Length Verification
+  * @{
+  */ 
+/**
+  * @brief Calibration factor length verification (7 bits maximum)
+  * @param _Calibration_Factor_: Calibration factor value
+  * @retval None
+  */
+#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7FU))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
+  * @{
+  */
+#if defined (STM32L031xx) || defined (STM32L041xx) || \
+    defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || \
+    defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3   ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+                              ((CONV) == ADC_SOFTWARE_START))
+#elif defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC3   ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+                              ((CONV) == ADC_SOFTWARE_START))
+#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || \
+    defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
+#define IS_ADC_EXTTRIG(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4   ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T21_TRGO ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_T3_TRGO  ) || \
+                              ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ) || \
+                              ((CONV) == ADC_SOFTWARE_START))
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef   HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
+uint32_t            HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef   HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
+
+/* ADC VrefInt and Temperature sensor functions specific to this STM32 serie */
+HAL_StatusTypeDef   HAL_ADCEx_EnableVREFINT(void);
+void                HAL_ADCEx_DisableVREFINT(void);
+HAL_StatusTypeDef   HAL_ADCEx_EnableVREFINTTempSensor(void);
+void                HAL_ADCEx_DisableVREFINTTempSensor(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L0xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h
new file mode 100755
index 0000000..8e90a40
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp.h
@@ -0,0 +1,683 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_comp.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_COMP_H
+#define __STM32L0xx_HAL_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup COMP_Exported_Types COMP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+typedef struct
+{
+
+  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
+                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
+                                    This parameter can be a value of @ref COMP_WindowMode */
+
+  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
+                                    Note: For the characteritics of comparator power modes
+                                          (propagation delay and power consumption), refer to device datasheet.
+                                    This parameter can be a value of @ref COMP_PowerMode */
+
+  uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).
+                                    This parameter can be a value of @ref COMP_InputPlus */
+
+  uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).
+                                    This parameter can be a value of @ref COMP_InputMinus */
+
+  uint32_t OutputPol;          /*!< Set comparator output polarity.
+                                    This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t LPTIMConnection;    /*!< Set comparator output connection to LPTIM peripheral.
+                                    This parameter can be a value of @ref COMP_LPTIMConnection */
+
+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+}COMP_InitTypeDef;
+
+/**
+  * @brief  HAL COMP state machine: HAL COMP states definition
+  */
+#define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)
+typedef enum
+{
+  HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+  HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
+  HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
+}HAL_COMP_StateTypeDef;
+
+/** 
+  * @brief  COMP Handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  HAL_LockTypeDef    Lock;            /*!< Locking object           */
+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
+} COMP_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_WindowMode COMP Window Mode
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_PowerMode COMP power mode
+  * @{
+  */
+/* Note: For the characteritics of comparator power modes                     */
+/*       (propagation delay and power consumption),                           */
+/*       refer to device datasheet.                                           */
+#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_COMP2SPEED)       /*!< COMP power mode to low power (indicated as "high speed" in reference manual) (only for COMP instance: COMP2) */
+#define COMP_POWERMODE_ULTRALOWPOWER   ((uint32_t)0x00000000U)     /*!< COMP power mode to ultra low power (indicated as "low speed" in reference manual) (only for COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+  * @{
+  */
+#define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000U)                            /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#define COMP_INPUT_PLUS_IO2            (COMP_CSR_COMP2INPSEL_0)                           /*!< Comparator input plus connected to IO2 (pin PB4 for COMP2) (only for COMP instance: COMP2) */
+#define COMP_INPUT_PLUS_IO3            (COMP_CSR_COMP2INPSEL_1)                           /*!< Comparator input plus connected to IO3 (pin PA5 for COMP2) (only for COMP instance: COMP2) */
+#define COMP_INPUT_PLUS_IO4            (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1)  /*!< Comparator input plus connected to IO4 (pin PB6 for COMP2) (only for COMP instance: COMP2) */
+#define COMP_INPUT_PLUS_IO5            (COMP_CSR_COMP2INPSEL_2)                           /*!< Comparator input plus connected to IO5 (pin PB7 for COMP2) (only for COMP instance: COMP2) */
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define COMP_INPUT_PLUS_IO6            (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0)  /*!< Comparator input plus connected to IO6 (pin PA7 for COMP2) (only for COMP instance: COMP2) (Available only on devices STM32L0 category 1) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+  * @{
+  */
+#define COMP_INPUT_MINUS_1_4VREFINT    (COMP_CSR_COMP2INNSEL_2                                                  ) /*!< Comparator input minus connected to 1/4 VREFINT (only for COMP instance: COMP2) */
+#define COMP_INPUT_MINUS_1_2VREFINT    (COMP_CSR_COMP2INNSEL_2 |                          COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to 1/2 VREFINT (only for COMP instance: COMP2) */
+#define COMP_INPUT_MINUS_3_4VREFINT    (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to 3/4 VREFINT (only for COMP instance: COMP2) */
+#define COMP_INPUT_MINUS_VREFINT       ((uint32_t)0x00000000U)                                                    /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1      (                         COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define COMP_INPUT_MINUS_DAC1_CH2      (                         COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define COMP_INPUT_MINUS_IO1           (                                                  COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define COMP_INPUT_MINUS_IO2           (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO2 (pin PB3 for COMP2) (only for COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+
+/** @defgroup COMP_LPTIMConnection COMP Low power timer connection definition
+  * @{
+  */
+
+#define COMP_LPTIMCONNECTION_DISABLED               ((uint32_t)0x00000000U)    /*!< COMPx signal is gated */
+#define COMP_LPTIMCONNECTION_IN1_ENABLED            ((uint32_t)0x00000001U)    /*!< COMPx signal is connected to LPTIM input 1 */
+#define COMP_LPTIMCONNECTION_IN2_ENABLED            ((uint32_t)0x00000002U)    /*!< COMPx signal is connected to LPTIM input 2 */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputPolarity COMP output Polarity
+  * @{
+  */
+#define COMP_OUTPUTPOL_NONINVERTED             ((uint32_t)0x00000000U)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OUTPUTPOL_INVERTED                COMP_CSR_COMPxPOLARITY       /*!< COMP output on GPIO is inverted */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+  * @{
+  */
+/* Note: Comparator output level values are fixed to "0" and "1",             */
+/* corresponding COMP register bit is managed by HAL function to match        */
+/* with these values (independently of bit position in register).             */
+
+/* When output polarity is not inverted, comparator output is low when
+   the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000U)
+/* When output polarity is not inverted, comparator output is high when
+   the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+  * @{
+  */
+#define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000U)                                    /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+  * @{
+  */
+
+/** @defgroup COMP_Handle_Management  COMP Handle Management
+  * @{
+  */
+
+/** @brief  Reset COMP handle state.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+
+/**
+  * @brief  Enable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+  * @brief  Disable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+  * @brief  Lock the specified comparator configuration.
+  * @note   Using this macro induce HAL COMP handle state machine being no
+  *         more in line with COMP instance state.
+  *         To keep HAL COMP handle state machine updated, it is recommended
+  *         to use function "HAL_COMP_Lock')".
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
+
+/**
+  * @brief  Check whether the specified comparator is locked.
+  * @param  __HANDLE__  COMP handle
+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+  */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK) == COMP_CSR_COMPxLOCK)
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exti_Management  COMP external interrupt line management
+  * @{
+  */
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Generate a software interrupt on the COMP1 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Generate a software interrupt on the COMP2 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()           SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+  * @{
+  */
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_LINE_COMP1           (EXTI_IMR_IM21)  /*!< EXTI line 21 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2           (EXTI_IMR_IM22)  /*!< EXTI line 22 connected to COMP2 output */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_IT                        ((uint32_t) 0x01U)  /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT                     ((uint32_t) 0x02U)  /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING                    ((uint32_t) 0x10U)  /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING                   ((uint32_t) 0x20U)  /*!< EXTI line event on falling edge */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators 
+  * @{
+  */
+/**
+  * @brief  Get the specified EXTI line for a comparator instance.
+  * @param  __INSTANCE__  specifies the COMP instance.
+  * @retval value of @ref COMP_ExtiLine
+  */
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ?                 \
+                                             COMP_EXTI_LINE_COMP1 : COMP_EXTI_LINE_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
+  * @{
+  */
+#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
+                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
+
+#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
+
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
+
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)                  \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+       (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1                                 \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO6)                            \
+      )                                                                        \
+  )
+#else
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)                  \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+       (__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1                                 \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO4)                            \
+       || ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO5)                            \
+      )                                                                        \
+  )
+#endif
+
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)                \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+          ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)                      \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)                     \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)                     \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)                          \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)                   \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)                   \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)                   \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)                      \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)                     \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)                     \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)                          \
+       || ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)                          \
+      )                                                                        \
+  )
+
+#define IS_COMP1_LPTIMCONNECTION(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
+
+#define IS_COMP2_LPTIMCONNECTION(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED) || \
+                                                     ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
+
+#define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION)   (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
+                                                                ((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
+
+#define IS_COMP_OUTPUTPOL(POL)  (((POL) == COMP_OUTPUTPOL_NONINVERTED)  || \
+                                 ((POL) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_TRIGGERMODE(__TRIGGERMODE__) (((__TRIGGERMODE__) == COMP_TRIGGERMODE_NONE)                 || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
+                                              ((__TRIGGERMODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING)   )
+
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include COMP HAL Extended module */
+#include "stm32l0xx_hal_comp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+  * @{
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h
new file mode 100755
index 0000000..4b4fa0a
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_comp_ex.h
@@ -0,0 +1,89 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_comp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_COMP_EX_H
+#define __STM32L0xx_HAL_COMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup COMPEx COMPEx
+  * @{
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMPEx_Exported_Functions COMPEx Exported Functions
+  * @{
+  */
+
+/** @defgroup COMPEx_Exported_Functions_Group1 Extended COMP VREFINT setup functions
+ * @{
+ */
+/* COMP specific functions to manage VREFINT *************************************/
+void HAL_COMPEx_EnableVREFINT(void);
+void HAL_COMPEx_DisableVREFINT(void);
+   
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_COMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h
new file mode 100755
index 0000000..9e28307
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_conf_template.h
@@ -0,0 +1,314 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l0xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CONF_H
+#define __STM32L0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+#define HAL_ADC_MODULE_ENABLED   
+#define HAL_COMP_MODULE_ENABLED 
+#define HAL_CRC_MODULE_ENABLED  
+#define HAL_CRYP_MODULE_ENABLED  
+#define HAL_DAC_MODULE_ENABLED   
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FIREWALL_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED   
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED 
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED  
+#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RNG_MODULE_ENABLED   
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED   
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED   
+#define HAL_UART_MODULE_ENABLED 
+#define HAL_USART_MODULE_ENABLED 
+#define HAL_IRDA_MODULE_ENABLED 
+#define HAL_SMARTCARD_MODULE_ENABLED 
+#define HAL_SMBUS_MODULE_ENABLED 
+#define HAL_WWDG_MODULE_ENABLED  
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED 
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator for USB (HSI48) value.
+  */
+#if !defined  (HSI48_VALUE) 
+#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Time out for LSE start up value in ms.
+  */
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+   
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U              
+#define  PREREAD_ENABLE               0U
+#define  BUFFER_CACHE_DISABLE         0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+  
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l0xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+ 
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+   
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h
new file mode 100755
index 0000000..fffdac0
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRC_H
+#define __STM32L0xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @{
+  */ 
+
+   /** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  CRC HAL State Structure definition  
+  */ 
+typedef enum
+{                                            
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+}HAL_CRC_StateTypeDef;
+
+
+/** 
+  * @brief CRC Init Structure definition  
+  */ 
+typedef struct
+{
+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.  
+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default 
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. 
+                                            In that case, there is no need to set GeneratingPolynomial field.
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
+
+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. 
+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.   
+                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set */
+
+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation, 
+                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE   */                                                
+
+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+                                           Value can be either one of
+                                           CRC_POLYLENGTH_32B                  (32-bit CRC)
+                                           CRC_POLYLENGTH_16B                  (16-bit CRC)
+                                           CRC_POLYLENGTH_8B                   (8-bit CRC)
+                                           CRC_POLYLENGTH_7B                   (7-bit CRC) */
+                                              
+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse 
+                                           is set to DEFAULT_INIT_VALUE_ENABLE   */                                                
+  
+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. 
+                                           Can be either one of the following values 
+                                           CRC_INPUTDATA_INVERSION_NONE      no input data inversion
+                                           CRC_INPUTDATA_INVERSION_BYTE      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+                                           CRC_INPUTDATA_INVERSION_HALFWORD  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+                                           CRC_INPUTDATA_INVERSION_WORD      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */  
+                                              
+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+                                            Can be either 
+                                            CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, or
+                                            CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
+}CRC_InitTypeDef;
+
+
+/** 
+  * @brief  CRC Handle Structure definition  
+  */ 
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */ 
+  
+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
+  
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+    
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+  
+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. 
+                                            Can be either 
+                                            CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
+                                            CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
+                                            CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bits data)                                                                                        
+                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+                                           must occur if InputBufferFormat is not one of the three values listed above  */ 
+}CRC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants   CRC Exported Constants
+  * @{
+  */
+  
+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
+  * @{
+  */
+#define DEFAULT_CRC32_POLY      0x04C11DB7U
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
+  * @{
+  */
+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)
+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)
+
+/**
+  * @}
+  */
+ 
+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
+  * @{
+  */                                      
+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U)
+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+  * @{
+  */
+#define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000U)
+#define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)
+#define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)
+#define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+  * @{
+  */
+#define HAL_CRC_LENGTH_32B     32U
+#define HAL_CRC_LENGTH_16B     16U
+#define HAL_CRC_LENGTH_8B       8U
+#define HAL_CRC_LENGTH_7B       7U
+
+/**
+  * @}
+  */  
+
+/** @defgroup CRC_Input_Buffer_Format CRC input buffer format
+  * @{
+  */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set 
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for 
+ * the CRC APIs to provide a correct result */   
+#define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000U)
+#define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001U)
+#define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002U)
+#define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003U)
+
+/** 
+  * @}
+  */   
+
+/** 
+  * @}
+  */ 
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state
+  * @param  __HANDLE__: CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__: CRC handle
+  * @retval None.
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief  Set CRC INIT non-default value
+  * @param  __HANDLE__    : CRC handle
+  * @param  __INIT__      : 32-bit initial value  
+  * @retval None.
+  */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    
+
+/**
+  * @brief Stores a 8-bit data in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+  * @param __HANDLE__: CRC handle
+  * @retval 8-bit value of the ID register 
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros   CRC Private Macros
+  * @{
+  */
+
+#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
+                                            ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
+                                   
+
+#define IS_DEFAULT_INIT_VALUE(__VALUE__)  (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
+                                           ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
+                                      
+#define IS_CRC_POL_LENGTH(__LENGTH__)     (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
+                                           ((__LENGTH__) == CRC_POLYLENGTH_16B) || \
+                                           ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \
+                                           ((__LENGTH__) == CRC_POLYLENGTH_7B))
+ 
+
+#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__)       (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
+                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+  * @}
+  */
+  
+/* Include CRC HAL Extension module */
+#include "stm32l0xx_hal_crc_ex.h"  
+
+/** @defgroup CRC_Exported_Constants   CRC Exported Constants
+  * @{
+  */
+
+/* Aliases for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup CRC_Private CRC Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h
new file mode 100755
index 0000000..7cef231
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc_ex.h
@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRC_EX_H
+#define __STM32L0xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRCEx CRCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Constants CRCEx Exported constants
+ * @{
+ */
+
+/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000U)
+#define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0)
+#define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1)
+#define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000U)
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)
+/**                                               
+  * @}
+  */
+
+
+/**
+ * @}
+ */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
+  * @{
+  */
+    
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__    : CRC handle
+  * @retval None.
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__    : CRC handle
+  * @retval None.
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__    : CRC handle
+  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial  
+  * @retval None.
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/** @defgroup  CRCEx_Private_Macros   CRCEx Private Macros
+  * @{
+  */
+  
+#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)     (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
+                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
+                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
+                                                 
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)    (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                       ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+  * @}
+  */
+/** @defgroup CRCEx_Exported_Functions CRCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
+  * @{
+  */
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h
new file mode 100755
index 0000000..f20a7c1
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp.h
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRYP_H
+#define __STM32L0xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYP CRYP
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  CRYP Configuration Structure definition  
+  */
+typedef struct
+{  
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                             This parameter can be a value of @ref CRYP_Data_Type */
+  
+  uint8_t* pKey;        /*!< The key used for encryption/decryption */
+  
+  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
+                             counter in CTR mode */
+  
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief HAL CRYP State structures definition  
+  */ 
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP internal processing is ongoing   */
+  HAL_CRYP_STATE_TIMEOUT           = 0x03U,  /*!< CRYP timeout state                    */
+  HAL_CRYP_STATE_ERROR             = 0x04U   /*!< CRYP error state                      */ 
+    
+}HAL_CRYP_STATETypeDef;
+
+/** 
+  * @brief HAL CRYP phase structures definition  
+  */ 
+typedef enum
+{
+  HAL_CRYP_PHASE_READY             = 0x01U,    /*!< CRYP peripheral is ready for initialization. */
+  HAL_CRYP_PHASE_PROCESS           = 0x02U,    /*!< CRYP peripheral is in processing phase */
+}HAL_PhaseTypeDef;
+
+/** 
+  * @brief  CRYP handle Structure definition  
+  */ 
+typedef struct
+{
+  AES_TypeDef                 *Instance;        /*!< Register base address        */
+
+  CRYP_InitTypeDef            Init;             /*!< CRYP required parameters */
+
+  uint8_t                     *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+  uint8_t                     *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+  __IO uint16_t               CrypInCount;      /*!< Counter of inputed data */
+
+  __IO uint16_t               CrypOutCount;     /*!< Counter of outputed data */
+
+  HAL_StatusTypeDef           Status;           /*!< CRYP peripheral status */
+
+  HAL_PhaseTypeDef            Phase;            /*!< CRYP peripheral phase */
+
+  DMA_HandleTypeDef           *hdmain;          /*!< CRYP In DMA handle parameters */
+
+  DMA_HandleTypeDef           *hdmaout;         /*!< CRYP Out DMA handle parameters */
+
+  HAL_LockTypeDef             Lock;             /*!< CRYP locking object */
+
+  __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
+
+}CRYP_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Data_Type CRYP Data Type
+  * @{
+  */
+#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000U)
+#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B          AES_CR_DATATYPE
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
+                                    ((DATATYPE) == CRYP_DATATYPE_1B))  
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction
+  * @{
+  */ 
+#define CRYP_CR_ALGOMODE_DIRECTION              (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
+
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        ((uint32_t)0x00000000U)
+#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT  (AES_CR_MODE)
+#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT        (AES_CR_CHMOD_0)
+#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT  ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
+#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT        (AES_CR_CHMOD_1)
+#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT        ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1))
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_AES_Interrupts AES Interrupts
+  * @{
+  */ 
+#define CRYP_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
+#define CRYP_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CRYP_AES_Flags AES Flags
+  * @{
+  */ 
+#define CRYP_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
+#define CRYP_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
+#define CRYP_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags
+  * @{
+  */ 
+#define CRYP_CLEARFLAG_CCF                       AES_CR_CCFC   /*!< Computation Complete Flag Clear */
+#define CRYP_CLEARFLAG_RDERR                     AES_CR_ERRC   /*!< Read Error Clear           */
+#define CRYP_CLEARFLAG_WRERR                     AES_CR_ERRC   /*!< Write Error Clear          */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRYP handle state
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
+/**
+  * @brief  Enable/Disable the CRYP peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
+#define __HAL_CRYP_DISABLE(__HANDLE__)                  CLEAR_BIT((__HANDLE__)->Instance->CR, AES_CR_EN)
+
+/**
+  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __MODE__: The algorithm mode.
+  * @retval None
+  */
+#define __HAL_CRYP_SET_MODE(__HANDLE__,__MODE__)             SET_BIT((__HANDLE__)->Instance->CR, (__MODE__))
+
+
+/** @brief  Check whether the specified CRYP flag is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_CCF   : Computation Complete Flag
+  *            @arg CRYP_FLAG_RDERR : Read Error Flag
+  *            @arg CRYP_FLAG_WRERR : Write Error Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CRYP_GET_FLAG(__HANDLE__,__FLAG__)         (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the CRYP pending flag.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
+  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
+  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__)   SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
+
+/**
+  * @brief  Enable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  * @retval None
+  */
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__,__INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: CRYP interrupt.
+  * @retval None
+  */
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__,__INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Checks if the specified CRYP interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param __INTERRUPT__: CRYP interrupt source to check
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_IT_CC   : Computation Complete interrupt
+  *            @arg CRYP_IT_ERR : Error interrupt (used for RDERR and WRERR)
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+    (( ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)       \
+     )? SET : RESET                                         \
+    )
+         
+/** @brief  Clear the CRYP pending IT.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __IT__: specifies the IT to clear.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_CLEARFLAG_CCF   : Computation Complete Clear Flag
+  *            @arg CRYP_CLEARFLAG_RDERR : Read Error Clear
+  *            @arg CRYP_CLEARFLAG_WRERR : Write Error Clear
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT((__HANDLE__)->Instance->CR, (__IT__))
+
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extension module */
+#include "stm32l0xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef     HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef     HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+
+/* MSP functions  *************************************************************/
+void                  HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void                  HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_Exported_Functions_Group2  AES processing functions
+  * @{
+  */
+
+/* AES encryption/decryption using polling  ***********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
+
+/* AES encryption/decryption using interrupt  *********************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/* AES encryption/decryption using DMA  ***************************************/
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
+HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup CRYP_Exported_Functions_Group3 DMA callback functions
+  * @{
+  */
+
+/* CallBack functions  ********************************************************/
+void                  HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void                  HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void                  HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+  * @{
+  */
+
+/* Processing functions  ********************************************************/
+void                  HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
+  * @{
+  */
+
+/* Peripheral State functions  **************************************************/
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup CRYP_Private CRYP Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h
new file mode 100755
index 0000000..4678d47
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cryp_ex.h
@@ -0,0 +1,97 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYPEx HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CRYP_EX_H
+#define __STM32L0xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRYPEx CRYPEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions
+  * @{
+  */
+
+/* CallBack functions  ********************************************************/
+void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h
new file mode 100755
index 0000000..535ca57
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac.h
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_dac.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DAC_H
+#define __STM32L0xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DAC DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
+ 
+}HAL_DAC_StateTypeDef;
+ 
+/** 
+  * @brief  DAC handle Structure definition  
+  */ 
+typedef struct
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
+#endif
+
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                   */
+
+}DAC_HandleTypeDef;
+
+/** 
+  * @brief   DAC Configuration regular Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
+                                   This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                   This parameter can be a value of @ref DAC_output_buffer */
+
+}DAC_ChannelConfTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+  * @{
+  */  
+
+/** @defgroup DAC_Error_Code DAC Error Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */
+#endif
+#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+  * @{
+  */
+#define DAC_TRIGGER_NONE       ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO    ((uint32_t)                                                    DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T21_TRGO   ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO    ((uint32_t)(DAC_CR_TSEL1_2 |                                   DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9    ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 |                  DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE   ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define DAC_TRIGGER_T3_TRGO    ((uint32_t)(                                  DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3  TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_CH3     ((uint32_t)(                 DAC_CR_TSEL1_1 |                  DAC_CR_TEN1)) /*!< TIM3  CH3  selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO    ((uint32_t)(DAC_CR_TSEL1_2 |                  DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7  TRGO selected as external conversion trigger for DAC channel */
+#endif
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T3_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T3_CH3)     || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T21_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#else /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T21_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)
+#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+  * @{
+  */
+#define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)
+#endif
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                 ((CHANNEL) == DAC_CHANNEL_2))
+#else
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement DAC data alignement
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)
+#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)
+#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data DAC data
+  * @{
+  */
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+  * @{
+  */ 
+#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition DAC IT definition
+  * @{
+  */ 
+#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @brief Reset DAC handle state
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __DAC_CHANNEL__: specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
+SET_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
+
+/** @brief Disable the DAC channel
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __DAC_CHANNEL__: specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
+CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__)))
+
+  
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief Disable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__: DAC handle
+  * @param __INTERRUPT__: DAC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (STM32L072xx STM32L073xx STM32L082xx STM32L083xx only)
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+(((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the FLAG.
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__)  \
+((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the FLAG.
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+  * @}
+  */ 
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+  * @{
+  */
+
+/** @brief Set DHR12R1 alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008U) + (__ALIGNEMENT__))
+
+/** @brief  Set DHR12R2 alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014U) + (__ALIGNEMENT__))
+
+/** @brief  Set DHR12RD alignment
+  * @param  __ALIGNEMENT__: specifies the DAC alignement
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020U) + (__ALIGNEMENT__))
+
+/** @brief Enable the DAC interrupt
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @retval None
+  */
+  
+/**
+  * @}
+  */ 
+
+
+/* Include DAC HAL Extension module */
+#include "stm32l0xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */ 
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+  * @{
+  */
+/* Peripheral State functions ***************************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L011xx && STM32L021xx && STM32L031xx && STM32L041xx && STM32L061xx && STM32L071xx && STM32L081xx*/
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L0xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h
new file mode 100755
index 0000000..3b65bfd
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dac_ex.h
@@ -0,0 +1,183 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_dac_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DAC_EX_H
+#define __STM32L0xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DACEx DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+   
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+  * @{
+  */ 
+   
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/  
+
+/* Exported functions --------------------------------------------------------*/  
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group1  Extended features functions
+  * @{
+  */
+/* Extension features functions ***********************************************/
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup DACEx_Private DACEx Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* !STM32L011xx && !STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx && !STM32L071xx && !STM32L081xx*/
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L0xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
old mode 100644
new mode 100755
index d93a2ee..678990b
--- a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h
@@ -46,8 +46,6 @@
 #include "stm32l0xx.h"
 #include "Legacy/stm32_hal_legacy.h"
 #include <stdio.h>
-#include <stdint.h>
-#include <stdbool.h>
 
 /* Exported types ------------------------------------------------------------*/
 
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h
new file mode 100755
index 0000000..c528970
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_firewall.h
@@ -0,0 +1,384 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_firewall.h
+  * @author  MCD Application Team
+  * @brief   Header file of FIREWALL HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_FIREWALL_H
+#define __STM32L0xx_HAL_FIREWALL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FIREWALL  FIREWALL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types
+  * @{
+  */ 
+
+/** 
+  * @brief FIREWALL Initialization Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CodeSegmentStartAddress;        /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are
+                                                reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t CodeSegmentLength;              /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are 
+                                                reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+
+  uint32_t NonVDataSegmentStartAddress;    /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 in order to allow a 256-byte granularity. */
+
+  uint32_t NonVDataSegmentLength;          /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */
+ 
+  uint32_t VDataSegmentStartAddress;       /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits
+                                                are reserved and forced to 0 in order to allow a 64-byte granularity. */
+
+  uint32_t VDataSegmentLength;             /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB
+                                                bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */
+  
+  uint32_t VolatileDataExecution;          /*!< Set VDE bit specifying whether or not the volatile data segment can be executed.
+                                                 When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Executable */  
+                                           
+  uint32_t VolatileDataShared;             /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a 
+                                                non-protected application code.
+                                                This parameter can be a value of @ref FIREWALL_VolatileData_Shared */  
+                                                                                                                                     
+}FIREWALL_InitTypeDef;
+
+
+/**
+  * @}
+  */
+
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants
+  * @{
+  */
+
+/** @defgroup FIREWALL_VolatileData_Executable   FIREWALL volatile data segment execution status
+  * @{
+  */
+#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE                 ((uint32_t)0x0000U)
+#define FIREWALL_VOLATILEDATA_EXECUTABLE                     ((uint32_t)FW_CR_VDE)
+/**
+  * @}
+  */ 
+
+/** @defgroup FIREWALL_VolatileData_Shared  FIREWALL volatile data segment share status
+  * @{
+  */ 
+#define FIREWALL_VOLATILEDATA_NOT_SHARED                ((uint32_t)0x0000U)
+#define FIREWALL_VOLATILEDATA_SHARED                    ((uint32_t)FW_CR_VDS) 
+/**
+  * @}
+  */ 
+
+/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status
+  * @{
+  */ 
+#define FIREWALL_PRE_ARM_RESET                 ((uint32_t)0x0000U)
+#define FIREWALL_PRE_ARM_SET                   ((uint32_t)FW_CR_FPA)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup FIREWALL_Private
+  * @{
+  */
+#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))                                                   
+#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE))
+
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE + FLASH_SIZE)))                                                   
+#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (FLASH_BASE + FLASH_SIZE)) 
+
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS)        (((ADDRESS) >= SRAM_BASE) && ((ADDRESS) < (SRAM_BASE + SRAM_SIZE_MAX)))
+#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= (SRAM_BASE + SRAM_SIZE_MAX))                                                        
+    
+  
+#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \
+                                               ((SHARE) == FIREWALL_VOLATILEDATA_SHARED))
+                                               
+#define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \
+                                                   ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE))                                                                                    
+/**
+  * @}
+  */  
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether the FIREWALL is enabled or not.
+  * @retval FIREWALL enabling status (TRUE or FALSE).
+  */            
+#define  __HAL_FIREWALL_IS_ENABLED()  HAL_IS_BIT_CLR(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN)  
+
+
+/** @brief Enable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       closes the Firewall, otherwise it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.    
+  */ 
+#define __HAL_FIREWALL_PREARM_ENABLE()                                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_FPA) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+
+                    
+/** @brief Disable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       closes the Firewall, otherwise, it generates a system reset.
+  * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API
+  *       but can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  */ 
+#define __HAL_FIREWALL_PREARM_DISABLE()                                        \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_FPA) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data sharing in setting VDS bit. 
+  * @note When VDS bit is set, the volatile data segment is shared with non-protected
+  *       application code. It can be accessed whatever the Firewall state (opened or closed). 
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE()                            \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDS) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data sharing in resetting VDS bit. 
+  * @note When VDS bit is reset, the volatile data segment is not shared and cannot be 
+  *       hit by a non protected executable code when the Firewall is closed. If it is 
+  *       accessed in such a condition, a system reset is generated by the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.     
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDS) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDS) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Enable volatile data execution in setting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be 
+  *       executed whatever the VDE bit value.  
+  * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When
+  *       the Firewall call is closed, a "call gate" entry procedure is required to open 
+  *       first the Firewall.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.         
+  */ 
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE()                         \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  SET_BIT(FIREWALL->CR, FW_CR_VDE) ;                           \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)
+
+/** @brief Disable volatile data execution in resetting VDE bit.
+  * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be 
+  *       executed whatever the VDE bit value.  
+  * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot  be executed.
+  * @note This macro can be executed inside a code area protected by the Firewall. 
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.        
+  */
+#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE()                           \
+             do {                                                              \
+                  __IO uint32_t tmpreg;                                        \
+                  CLEAR_BIT(FIREWALL->CR, FW_CR_VDE) ;                         \
+                  /* Read bit back to ensure it is taken into account by IP */ \
+                  /* (introduce proper delay inside macro execution) */        \
+                  tmpreg = READ_BIT(FIREWALL->CR, FW_CR_VDE) ;                 \
+                  UNUSED(tmpreg);                                              \
+                } while(0)   
+
+
+/** @brief Check whether or not the volatile data segment is shared.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval VDS bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FIREWALL->CR & FW_CR_VDS) == FW_CR_VDS)
+
+/** @brief Check whether or not the volatile data segment is declared executable.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval VDE bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FIREWALL->CR & FW_CR_VDE) == FW_CR_VDE)
+
+/** @brief Check whether or not the Firewall pre arm bit is set.
+  * @note This macro can be executed inside a code area protected by the Firewall.
+  * @note This macro can be executed whatever the Firewall state (opened or closed) when
+  *       NVDSL register is equal to 0. Otherwise (when NVDSL register is different from
+  *       0, that is, when the non volatile data segment is defined), the macro can be
+  *       executed only when the Firewall is opened.      
+  * @retval FPA bit setting status (TRUE or FALSE).
+  */
+#define __HAL_FIREWALL_GET_PREARM() ((FIREWALL->CR & FW_CR_FPA) == FW_CR_FPA)
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions
+  * @{
+  */
+  
+/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions
+  * @brief    Initialization and Configuration Functions  
+  * @{
+  */  
+  
+/* Initialization functions  ********************************/
+HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init);
+void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config);
+void HAL_FIREWALL_EnableFirewall(void);
+void HAL_FIREWALL_EnablePreArmFlag(void);
+void HAL_FIREWALL_DisablePreArmFlag(void);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */   
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup FIREWALL_Private FIREWALL Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_FIREWALL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h
new file mode 100755
index 0000000..1f50039
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h
@@ -0,0 +1,479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_i2s.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_I2S_H
+#define __STM32L0xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L011xx) && !defined (STM32L021xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"  
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2S I2S
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+  * @{
+  */
+
+/** 
+  * @brief I2S Init structure definition  
+  */
+typedef struct
+{
+  uint32_t Mode;         /*!< Specifies the I2S operating mode.
+                              This parameter can be a value of @ref I2S_Mode */
+
+  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
+                              This parameter can be a value of @ref I2S_Standard */
+
+  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
+                              This parameter can be a value of @ref I2S_Data_Format */
+
+  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                              This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                              This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
+                              This parameter can be a value of @ref I2S_Clock_Polarity */
+
+}I2S_InitTypeDef;
+
+/** 
+  * @brief  HAL State structures definition
+  */ 
+typedef enum
+{
+  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
+  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
+  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */   
+  HAL_I2S_STATE_BUSY_TX    = 0x12U,  /*!< Data Transmission process is ongoing               */ 
+  HAL_I2S_STATE_BUSY_RX    = 0x22U,  /*!< Data Reception process is ongoing                  */
+  HAL_I2S_STATE_TIMEOUT    = 0x03U,  /*!< I2S timeout state                                  */ 
+  HAL_I2S_STATE_ERROR      = 0x04U   /*!< I2S error state                                    */      
+}HAL_I2S_StateTypeDef;
+
+/** 
+  * @brief I2S handle Structure definition  
+  */
+typedef struct
+{
+  SPI_TypeDef                *Instance;    /* I2S registers base address        */
+
+  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
+  
+  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
+  
+  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
+  
+  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
+  
+  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
+  
+  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
+  
+  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter 
+                                              (This field is initialized at the 
+                                               same value as transfer size at the 
+                                               beginning of the transfer and 
+                                               decremented when a sample is received. 
+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
+
+  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
+  
+  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
+  
+  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
+
+  __IO  uint32_t             ErrorCode;    /* I2S Error code                    */
+
+}I2S_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+  * @{
+  */
+
+/**
+  * @defgroup  I2S_ErrorCode I2S Error Code
+  * @{
+  */
+#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00U)    /*!< No error                    */
+#define HAL_I2S_ERROR_UDR       ((uint32_t)0x01U)    /*!< I2S Underrun error          */
+#define HAL_I2S_ERROR_OVR       ((uint32_t)0x02U)    /*!< I2S Overrun error           */
+#define HAL_I2S_ERROR_FRE       ((uint32_t)0x04U)    /*!< I2S Frame format error      */
+#define HAL_I2S_ERROR_DMA       ((uint32_t)0x08U)    /*!< DMA transfer error          */
+  /**
+    * @}
+    */
+
+/** @defgroup I2S_Mode I2S Mode
+  * @{
+  */
+#define I2S_MODE_SLAVE_TX                ((uint32_t) 0x00000000U)
+#define I2S_MODE_SLAVE_RX                ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX               ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX               ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
+                                                     SPI_I2SCFGR_I2SCFG_1))
+/**
+  * @}
+  */
+  
+/** @defgroup I2S_Standard I2S Standard
+  * @{
+  */
+#define I2S_STANDARD_PHILIPS             ((uint32_t) 0x00000000U)
+#define I2S_STANDARD_MSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT           ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
+                                                     SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG            ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
+                                                     SPI_I2SCFGR_I2SSTD_1 |\
+                                                     SPI_I2SCFGR_PCMSYNC))
+/** @defgroup I2S_Legacy I2S Legacy
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup I2S_Data_Format I2S Data Format
+  * @{
+  */
+#define I2S_DATAFORMAT_16B               ((uint32_t) 0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t) SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+  * @{
+  */
+#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+  * @{
+  */
+#define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)
+#define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)
+#define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)
+#define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)
+#define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)
+#define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)
+#define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)
+#define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)
+#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)
+#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+  * @{
+  */
+#define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)
+#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+  * @{
+  */
+#define I2S_IT_TXE                      SPI_CR2_TXEIE
+#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
+#define I2S_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Flag_definition I2S Flag definition
+  * @{
+  */
+#define I2S_FLAG_TXE                    SPI_SR_TXE
+#define I2S_FLAG_RXNE                   SPI_SR_RXNE
+
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define I2S_FLAG_OVR                    SPI_SR_OVR
+#define I2S_FLAG_FRE                    SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_BSY                    SPI_SR_BSY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+  * @{
+  */
+
+/** @brief  Reset I2S handle state
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief  Enable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @retval None
+  */
+#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief  Disable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @retval None
+  */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief  Enable the specified I2S interrupts.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval None
+  */  
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief  Disable the specified I2S interrupts.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval None
+  */ 
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+ 
+/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2S flag is set or not.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
+  *            @arg I2S_FLAG_UDR: Underrun flag
+  *            @arg I2S_FLAG_OVR: Overrun flag
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
+  *            @arg I2S_FLAG_BSY: Busy flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */                                                                                                   
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
+                                                             tmpreg = (__HANDLE__)->Instance->SR;\
+                                                             UNUSED(tmpreg);\
+                                              }while(0)
+/** @brief Clears the I2S UDR pending flag.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+/**
+  * @}
+  */ 
+                                                
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+  * @{
+  */
+                                                
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral Control and State functions
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private I2S Private
+  * @{
+  */
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
+                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
+                           ((MODE) == I2S_MODE_MASTER_TX) || \
+                           ((MODE) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
+                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
+                                    ((FORMAT) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
+                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+                           ((CPOL) == I2S_CPOL_HIGH))
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup I2S_Private I2S Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* !STM32L031xx && !STM32L041xx && !STM32L011xx && !STM32L021xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h
new file mode 100755
index 0000000..2887d93
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda.h
@@ -0,0 +1,843 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_irda.h
+  * @author  MCD Application Team
+  * @brief   Header file of IRDA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_IRDA_H
+#define __STM32L0xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+  * @{
+  */
+
+/**
+  * @brief IRDA Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref IRDA_Word_Length */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref IRDA_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+                                           to achieve low-power frequency.
+                                           @note Prescaler value 0 is forbidden */
+
+  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
+                                           This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+  * @brief HAL IRDA State structures definition
+  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains IRDA state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_IRDA_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing 
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_ERROR             = 0xE0U    /*!< Error
+                                                   Value is allowed for gState only */
+}HAL_IRDA_StateTypeDef;
+
+/**
+  * @brief  HAL IRDA Error Code structure definition
+  */
+
+#define  HAL_IRDA_ERROR_NONE      ((uint32_t)0x00U)    /*!< No error            */
+#define  HAL_IRDA_ERROR_PE        ((uint32_t)0x01U)    /*!< Parity error        */
+#define  HAL_IRDA_ERROR_NE        ((uint32_t)0x02U)    /*!< Noise error         */
+#define  HAL_IRDA_ERROR_FE        ((uint32_t)0x04U)    /*!< frame error         */
+#define  HAL_IRDA_ERROR_ORE       ((uint32_t)0x08U)    /*!< Overrun error       */
+#define  HAL_IRDA_ERROR_DMA       ((uint32_t)0x10U)    /*!< DMA transfer error  */
+
+/**
+  * @brief IRDA clock sources definition
+  */
+typedef enum
+{
+  IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
+  IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
+  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
+  IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
+  IRDA_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
+  IRDA_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+  * @brief  IRDA handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef            *Instance;        /*!< IRDA registers base address        */
+
+  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
+
+  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
+
+  uint16_t                 Mask;             /*!< IRDA RX RDR register mask          */
+
+  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
+
+  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management 
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO uint32_t           ErrorCode;        /*!< IRDA Error code                    */
+
+}IRDA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+  * @{
+  */
+
+/** @defgroup IRDA_Word_Length IRDA Word Length
+  * @{
+  */
+#define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long frame */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Parity IRDA Parity
+  * @{
+  */
+#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000U)                     /*!< No parity   */
+#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+  * @{
+  */
+#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+  * @{
+  */
+#define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000U)      /*!< IRDA normal power mode */ 
+#define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)   /*!< IRDA low power mode    */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_State IRDA State
+  * @{
+  */
+#define IRDA_STATE_DISABLE                  ((uint32_t)0x00000000U)    /*!< IRDA disabled  */ 
+#define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)   /*!< IRDA enabled   */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Mode IRDA Mode
+  * @{
+  */
+#define IRDA_MODE_DISABLE                   ((uint32_t)0x00000000U)     /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE                    ((uint32_t)USART_CR3_IREN)  /*!< Associated UART enabled in IRDA mode  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000U)      /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+  * @{
+  */
+#define IRDA_DMA_TX_DISABLE                 ((uint32_t)0x00000000U)      /*!< IRDA DMA TX disabled */ 
+#define IRDA_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)   /*!< IRDA DMA TX enabled  */ 
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Rx  IRDA DMA Rx
+  * @{
+  */
+#define IRDA_DMA_RX_DISABLE                 ((uint32_t)0x00000000)       /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)   /*!< IRDA DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+  * @{
+  */
+#define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request      */
+#define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Flags IRDA Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define IRDA_FLAG_REACK                     USART_ISR_REACK  /*!< IRDA Receive enable acknowledge flag  */
+#define IRDA_FLAG_TEACK                     USART_ISR_TEACK  /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY                      USART_ISR_BUSY   /*!< IRDA Busy flag                        */
+#define IRDA_FLAG_ABRF                      USART_ISR_ABRF   /*!< IRDA Auto baud rate flag              */
+#define IRDA_FLAG_ABRE                      USART_ISR_ABRE   /*!< IRDA Auto baud rate error             */
+#define IRDA_FLAG_TXE                       USART_ISR_TXE    /*!< IRDA Transmit data register empty     */
+#define IRDA_FLAG_TC                        USART_ISR_TC     /*!< IRDA Transmission complete            */
+#define IRDA_FLAG_RXNE                      USART_ISR_RXNE   /*!< IRDA Read data register not empty     */
+#define IRDA_FLAG_ORE                       USART_ISR_ORE    /*!< IRDA Overrun error                    */
+#define IRDA_FLAG_NE                        USART_ISR_NE     /*!< IRDA Noise error                      */
+#define IRDA_FLAG_FE                        USART_ISR_FE     /*!< IRDA Framing error                    */
+#define IRDA_FLAG_PE                        USART_ISR_PE     /*!< IRDA Parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define IRDA_IT_PE                          ((uint16_t)0x0028U)     /*!< IRDA Parity error interruption                 */
+#define IRDA_IT_TXE                         ((uint16_t)0x0727U)     /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC                          ((uint16_t)0x0626U)     /*!< IRDA Transmission complete interruption        */
+#define IRDA_IT_RXNE                        ((uint16_t)0x0525U)     /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE                        ((uint16_t)0x0424U)     /*!< IRDA Idle interruption                         */
+
+/**       Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  */
+#define IRDA_IT_ERR                         ((uint16_t)0x0060U)       /*!< IRDA Error interruption        */
+
+/**       Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  */
+#define IRDA_IT_ORE                         ((uint16_t)0x0300U)      /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE                          ((uint16_t)0x0200U)      /*!< IRDA Noise error interruption   */
+#define IRDA_IT_FE                          ((uint16_t)0x0100U)      /*!< IRDA Frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_IT_CLEAR_Flags   IRDA Interruption Clear Flags
+  * @{
+  */
+#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interruption_Mask    IRDA interruptions flags mask
+  * @{
+  */
+#define IRDA_IT_MASK  ((uint16_t)0x001FU)                             /*!< IRDA Interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset IRDA handle state.
+  * @param  __HANDLE__: IRDA handle.
+  * @retval None
+  */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                     } while(0)
+
+/** @brief  Flush the IRDA DR register.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
+    do{                                                                    \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified IRDA pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF
+  *            @arg @ref IRDA_CLEAR_FEF
+  *            @arg @ref IRDA_CLEAR_NEF
+  *            @arg @ref IRDA_CLEAR_OREF
+  *            @arg @ref IRDA_CLEAR_TCF
+  *            @arg @ref IRDA_CLEAR_IDLEF
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the IRDA PE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief  Clear the IRDA FE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief  Clear the IRDA NE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief  Clear the IRDA ORE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief  Clear the IRDA IDLE pending flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
+  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
+  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
+  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
+  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
+  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief  Disable the specified IRDA interrupt.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief  Check whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
+  *            @arg @ref IRDA_IT_NE Noise Error interrupt
+  *            @arg @ref IRDA_IT_FE Framing Error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
+
+/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT__: specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief  Set a specific IRDA request flag.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the IRDA one bit sample method.
+  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros   IRDA Private Macros
+  * @{
+  */
+
+/** @brief  Compute the mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
+  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
+
+/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
+  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
+
+/**
+  * @brief Ensure that IRDA frame length is valid.
+  * @param __LENGTH__: IRDA frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */ 
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that IRDA frame parity is valid.
+  * @param __PARITY__: IRDA frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
+                                    ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+  * @brief Ensure that IRDA communication mode is valid.
+  * @param __MODE__: IRDA communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+  * @brief Ensure that IRDA power mode is valid.
+  * @param __MODE__: IRDA power mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+  * @brief Ensure that IRDA state is valid.
+  * @param __STATE__: IRDA state mode. 
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */ 
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+                                  ((__STATE__) == IRDA_STATE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA associated UART/USART mode is valid.
+  * @param __MODE__: IRDA associated UART/USART mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
+                                 ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA sampling rate is valid.
+  * @param __ONEBIT__: IRDA sampling rate. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */ 
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA TX mode is valid.
+  * @param __DMATX__: IRDA DMA TX mode. 
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */ 
+#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA DMA RX mode is valid.
+  * @param __DMARX__: IRDA DMA RX mode. 
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */ 
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that IRDA request is valid.
+  * @param __PARAM__: IRDA request. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */ 
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32l0xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h
new file mode 100755
index 0000000..1a37b7d
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_irda_ex.h
@@ -0,0 +1,209 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_irda_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of IRDA HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_IRDA_EX_H
+#define __STM32L0xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the IRDA clock source.
+  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART2)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
+
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h
new file mode 100755
index 0000000..8d2e2a7
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_iwdg.h
@@ -0,0 +1,255 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_IWDG_H
+#define __STM32L0xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  IWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+                            This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/** 
+  * @brief  IWDG Handle Structure definition  
+  */
+typedef struct
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+
+}IWDG_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */
+#define IWDG_PRESCALER_4                0x00000000U                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)   /*!< IWDG prescaler set to 256 */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+  * @{
+  */
+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+  * @{
+  */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAU  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCU  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555U  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000U  /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+  * @brief  Check IWDG window value.
+  * @param  __WINDOW__  IWDG window value
+  * @retval None
+  */
+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h
new file mode 100755
index 0000000..fa3c3a2
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lcd.h
@@ -0,0 +1,804 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_lcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of LCD Controller HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_LCD_H
+#define __STM32L0xx_HAL_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LCD LCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LCD_Exported_Types LCD Exported Types
+  * @{
+  */
+
+/** 
+  * @brief LCD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Prescaler;       /*!< Configures the LCD Prescaler. 
+                                 This parameter can be one value of @ref LCD_Prescaler */
+  uint32_t Divider;         /*!< Configures the LCD Divider.
+                                 This parameter can be one value of @ref LCD_Divider */
+  uint32_t Duty;            /*!< Configures the LCD Duty.
+                                 This parameter can be one value of @ref LCD_Duty */
+  uint32_t Bias;            /*!< Configures the LCD Bias.
+                                 This parameter can be one value of @ref LCD_Bias */ 
+  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
+                                 This parameter can be one value of @ref LCD_Voltage_Source */  
+  uint32_t Contrast;        /*!< Configures the LCD Contrast.
+                                 This parameter can be one value of @ref LCD_Contrast */
+  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
+                                 This parameter can be one value of @ref LCD_DeadTime */
+  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
+                                 This parameter can be one value of @ref LCD_PulseOnDuration */
+  uint32_t HighDrive;      /*!< Configures the LCD High Drive.
+                                 This parameter can be one value of @ref LCD_HighDrive */
+  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
+                                 This parameter can be one value of @ref LCD_BlinkMode */
+  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
+                                 This parameter can be one value of @ref LCD_BlinkFrequency */
+  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
+                                 This parameter can be one value of @ref LCD_MuxSegment */
+}LCD_InitTypeDef;
+
+/** 
+  * @brief HAL LCD State structures definition
+  */ 
+typedef enum
+{
+  HAL_LCD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized */
+  HAL_LCD_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
+  HAL_LCD_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
+  HAL_LCD_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
+  HAL_LCD_STATE_ERROR             = 0x04U     /*!< Error */
+}HAL_LCD_StateTypeDef;
+
+/** 
+  * @brief  UART handle Structure definition
+  */  
+typedef struct
+{
+  LCD_TypeDef                   *Instance;  /* LCD registers base address */
+  
+  LCD_InitTypeDef               Init;       /* LCD communication parameters */
+
+  HAL_LockTypeDef               Lock;       /* Locking object */
+
+  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
+  
+  __IO uint32_t                 ErrorCode;  /* LCD Error code */
+  
+}LCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup LCD_Exported_Constants LCD Exported Constants
+  * @{
+  */
+
+/** @defgroup  LCD_ErrorCode LCD Error Code
+  * @{
+  */ 
+#define HAL_LCD_ERROR_NONE       ((uint32_t)0x00U)    /*!< No error */
+#define HAL_LCD_ERROR_FCRSF      ((uint32_t)0x01U)    /*!< Synchro flag timeout error */
+#define HAL_LCD_ERROR_UDR        ((uint32_t)0x02U)    /*!< Update display request flag timeout error */
+#define HAL_LCD_ERROR_UDD        ((uint32_t)0x04U)    /*!< Update display done flag timeout error */
+#define HAL_LCD_ERROR_ENS        ((uint32_t)0x08U)    /*!< LCD enabled status flag timeout error */
+#define HAL_LCD_ERROR_RDY        ((uint32_t)0x10U)    /*!< LCD Booster ready timeout error */
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Prescaler LCD Prescaler
+  * @{
+  */
+
+#define LCD_PRESCALER_1        ((uint32_t)0x00000000U)  /*!< CLKPS = LCDCLK        */
+#define LCD_PRESCALER_2        ((uint32_t)0x00400000U)  /*!< CLKPS = LCDCLK/2      */
+#define LCD_PRESCALER_4        ((uint32_t)0x00800000U)  /*!< CLKPS = LCDCLK/4      */
+#define LCD_PRESCALER_8        ((uint32_t)0x00C00000U)  /*!< CLKPS = LCDCLK/8      */
+#define LCD_PRESCALER_16       ((uint32_t)0x01000000U)  /*!< CLKPS = LCDCLK/16     */
+#define LCD_PRESCALER_32       ((uint32_t)0x01400000U)  /*!< CLKPS = LCDCLK/32     */
+#define LCD_PRESCALER_64       ((uint32_t)0x01800000U)  /*!< CLKPS = LCDCLK/64     */
+#define LCD_PRESCALER_128      ((uint32_t)0x01C00000U)  /*!< CLKPS = LCDCLK/128    */
+#define LCD_PRESCALER_256      ((uint32_t)0x02000000U)  /*!< CLKPS = LCDCLK/256    */
+#define LCD_PRESCALER_512      ((uint32_t)0x02400000U)  /*!< CLKPS = LCDCLK/512    */
+#define LCD_PRESCALER_1024     ((uint32_t)0x02800000U)  /*!< CLKPS = LCDCLK/1024   */
+#define LCD_PRESCALER_2048     ((uint32_t)0x02C00000U)  /*!< CLKPS = LCDCLK/2048   */
+#define LCD_PRESCALER_4096     ((uint32_t)0x03000000U)  /*!< CLKPS = LCDCLK/4096   */
+#define LCD_PRESCALER_8192     ((uint32_t)0x03400000U)  /*!< CLKPS = LCDCLK/8192   */
+#define LCD_PRESCALER_16384    ((uint32_t)0x03800000U)  /*!< CLKPS = LCDCLK/16384  */
+#define LCD_PRESCALER_32768    ((uint32_t)LCD_FCR_PS)  /*!< CLKPS = LCDCLK/32768  */
+
+#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
+                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
+
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Divider LCD Divider
+  * @{
+  */
+
+#define LCD_DIVIDER_16    ((uint32_t)0x00000000U)  /*!< LCD frequency = CLKPS/16 */
+#define LCD_DIVIDER_17    ((uint32_t)0x00040000U)  /*!< LCD frequency = CLKPS/17 */
+#define LCD_DIVIDER_18    ((uint32_t)0x00080000U)  /*!< LCD frequency = CLKPS/18 */
+#define LCD_DIVIDER_19    ((uint32_t)0x000C0000U)  /*!< LCD frequency = CLKPS/19 */
+#define LCD_DIVIDER_20    ((uint32_t)0x00100000U)  /*!< LCD frequency = CLKPS/20 */
+#define LCD_DIVIDER_21    ((uint32_t)0x00140000U)  /*!< LCD frequency = CLKPS/21 */
+#define LCD_DIVIDER_22    ((uint32_t)0x00180000U)  /*!< LCD frequency = CLKPS/22 */
+#define LCD_DIVIDER_23    ((uint32_t)0x001C0000U)  /*!< LCD frequency = CLKPS/23 */
+#define LCD_DIVIDER_24    ((uint32_t)0x00200000U)  /*!< LCD frequency = CLKPS/24 */
+#define LCD_DIVIDER_25    ((uint32_t)0x00240000U)  /*!< LCD frequency = CLKPS/25 */
+#define LCD_DIVIDER_26    ((uint32_t)0x00280000U)  /*!< LCD frequency = CLKPS/26 */
+#define LCD_DIVIDER_27    ((uint32_t)0x002C0000U)  /*!< LCD frequency = CLKPS/27 */
+#define LCD_DIVIDER_28    ((uint32_t)0x00300000U)  /*!< LCD frequency = CLKPS/28 */
+#define LCD_DIVIDER_29    ((uint32_t)0x00340000U)  /*!< LCD frequency = CLKPS/29 */
+#define LCD_DIVIDER_30    ((uint32_t)0x00380000U)  /*!< LCD frequency = CLKPS/30 */
+#define LCD_DIVIDER_31    ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
+
+#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
+                                     ((__DIVIDER__) == LCD_DIVIDER_31))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LCD_Duty LCD Duty
+  * @{
+  */
+  
+#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000U)           /*!< Static duty */
+#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
+#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
+#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
+#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
+
+#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
+                               ((__DUTY__) == LCD_DUTY_1_2)     || \
+                               ((__DUTY__) == LCD_DUTY_1_3)     || \
+                               ((__DUTY__) == LCD_DUTY_1_4)     || \
+                               ((__DUTY__) == LCD_DUTY_1_8))
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup LCD_Bias LCD Bias
+  * @{
+  */
+  
+#define LCD_BIAS_1_4                    ((uint32_t)0x00000000U) /*!< 1/4 Bias */
+#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
+#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
+
+#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
+                               ((__BIAS__) == LCD_BIAS_1_2) || \
+                               ((__BIAS__) == LCD_BIAS_1_3))
+/**
+  * @}
+  */ 
+    
+/** @defgroup LCD_Voltage_Source LCD Voltage Source
+  * @{
+  */
+  
+#define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000U) /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
+
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
+                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
+
+/**
+  * @}
+  */  
+
+/** @defgroup LCD_Interrupts LCD Interrupts
+  * @{
+  */
+#define LCD_IT_SOF                      LCD_FCR_SOFIE
+#define LCD_IT_UDD                      LCD_FCR_UDDIE
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
+  * @{
+  */
+
+#define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000U)         /*!< Pulse ON duration = 0 pulse   */
+#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
+#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
+#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
+#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
+#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
+#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
+#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
+
+#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
+                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_HighDrive LCD HighDrive
+  * @{
+  */
+
+#define LCD_HIGHDRIVE_0           ((uint32_t)0x00000000U)         /*!< Low resistance Drive   */
+#define LCD_HIGHDRIVE_1           (LCD_FCR_HD)                    /*!< High resistance Drive  */
+
+#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
+                                         ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_DeadTime LCD Dead Time
+  * @{
+  */
+
+#define LCD_DEADTIME_0                  ((uint32_t)0x00000000U)           /*!< No dead Time  */
+#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
+#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
+#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
+#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
+#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
+#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
+#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
+
+#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
+                                    ((__TIME__) == LCD_DEADTIME_1) || \
+                                    ((__TIME__) == LCD_DEADTIME_2) || \
+                                    ((__TIME__) == LCD_DEADTIME_3) || \
+                                    ((__TIME__) == LCD_DEADTIME_4) || \
+                                    ((__TIME__) == LCD_DEADTIME_5) || \
+                                    ((__TIME__) == LCD_DEADTIME_6) || \
+                                    ((__TIME__) == LCD_DEADTIME_7))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BlinkMode LCD Blink Mode
+  * @{
+  */
+
+#define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000U) /*!< Blink disabled            */
+#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
+#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to 
+                                                                    8 pixels according to the programmed duty)  */
+#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
+
+#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
+                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
+                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
+/**
+  * @}
+  */    
+
+/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
+  * @{
+  */
+
+#define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000U)               /*!< The Blink frequency = fLCD/8    */
+#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
+#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
+#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
+#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
+#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
+#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
+#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
+
+#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
+                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Contrast LCD Contrast
+  * @{
+  */
+
+#define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000U)       /*!< Maximum Voltage = 2.60V    */
+#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
+#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
+#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
+#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
+#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V    */
+#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V    */
+#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.51V    */
+
+#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
+                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
+/**
+  * @}
+  */
+      
+/** @defgroup LCD_MuxSegment LCD Mux Segment
+  * @{
+  */
+
+#define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000U)       /*!< SEG pin multiplexing disabled */
+#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
+
+#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
+                                      ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_BUFEN LCD Voltage output buffer enable
+  * @{
+  */
+
+#define LCD_VOLTBUFOUT_DISABLE            ((uint32_t)0x00000000U)       /*!< Voltage output buffer disabled */
+#define LCD_VOLTBUFOUT_ENABLE             (LCD_CR_BUFEN)                /*!< BUFEN[1] Voltage output buffer enabled    */
+
+#define IS_LCD_VOLTBUFOUT(__VALUE__) (((__VALUE__) == LCD_VOLTBUFOUT_ENABLE) || \
+                                      ((__VALUE__) == LCD_VOLTBUFOUT_DISABLE))
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Flag LCD Flag
+  * @{
+  */
+
+#define LCD_FLAG_ENS                    LCD_SR_ENS
+#define LCD_FLAG_SOF                    LCD_SR_SOF
+#define LCD_FLAG_UDR                    LCD_SR_UDR
+#define LCD_FLAG_UDD                    LCD_SR_UDD
+#define LCD_FLAG_RDY                    LCD_SR_RDY
+#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR
+
+/**
+  * @}
+  */   
+
+/** @defgroup LCD_RAMRegister LCD RAMRegister
+  * @{
+  */
+
+#define LCD_RAM_REGISTER0               ((uint32_t)0x00000000U) /*!< LCD RAM Register 0  */
+#define LCD_RAM_REGISTER1               ((uint32_t)0x00000001U) /*!< LCD RAM Register 1  */
+#define LCD_RAM_REGISTER2               ((uint32_t)0x00000002U) /*!< LCD RAM Register 2  */
+#define LCD_RAM_REGISTER3               ((uint32_t)0x00000003U) /*!< LCD RAM Register 3  */
+#define LCD_RAM_REGISTER4               ((uint32_t)0x00000004U) /*!< LCD RAM Register 4  */
+#define LCD_RAM_REGISTER5               ((uint32_t)0x00000005U) /*!< LCD RAM Register 5  */
+#define LCD_RAM_REGISTER6               ((uint32_t)0x00000006U) /*!< LCD RAM Register 6  */
+#define LCD_RAM_REGISTER7               ((uint32_t)0x00000007U) /*!< LCD RAM Register 7  */
+#define LCD_RAM_REGISTER8               ((uint32_t)0x00000008U) /*!< LCD RAM Register 8  */
+#define LCD_RAM_REGISTER9               ((uint32_t)0x00000009U) /*!< LCD RAM Register 9  */
+#define LCD_RAM_REGISTER10              ((uint32_t)0x0000000AU) /*!< LCD RAM Register 10 */
+#define LCD_RAM_REGISTER11              ((uint32_t)0x0000000BU) /*!< LCD RAM Register 11 */
+#define LCD_RAM_REGISTER12              ((uint32_t)0x0000000CU) /*!< LCD RAM Register 12 */
+#define LCD_RAM_REGISTER13              ((uint32_t)0x0000000DU) /*!< LCD RAM Register 13 */
+#define LCD_RAM_REGISTER14              ((uint32_t)0x0000000EU) /*!< LCD RAM Register 14 */
+#define LCD_RAM_REGISTER15              ((uint32_t)0x0000000FU) /*!< LCD RAM Register 15 */
+
+#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
+                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
+
+/**
+  * @}
+  */  
+   
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup LCD_Exported_Macros LCD Exported Macros
+  * @{
+  */
+
+/** @brief Reset LCD handle state
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
+
+/** @brief  macros to enables or disables the LCD
+  * @param  __HANDLE__: specifies the LCD Handle.  
+  * @retval None
+  */     
+#define __HAL_LCD_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
+#define __HAL_LCD_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
+
+/** @brief  macros to enables or disables the Voltage output buffer
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @retval None
+  */
+#define __HAL_LCD_VOLTOUTBUFFER_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
+#define __HAL_LCD_VOLTOUTBUFFER_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN))
+
+/** @brief  Macros to enable or disable the low resistance divider. Displays with high 
+  *         internal resistance may need a longer drive time to achieve 
+  *         satisfactory contrast. This function is useful in this case if some 
+  *         additional power consumption can be tolerated.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
+  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
+  * @retval None
+  */
+#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                                \
+                              do{                                              \
+                                  SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                                  LCD_WaitForSynchro(__HANDLE__);              \
+                                 }while(0)
+
+#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                               \
+                              do{                                              \
+                                  CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
+                                  LCD_WaitForSynchro(__HANDLE__);              \
+                                 }while(0)
+
+/**
+  * @brief  Macro to configure the LCD pulses on duration.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DURATION__: specifies the LCD pulse on duration in terms of 
+  *         CK_PS (prescaled LCD clock period) pulses.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_PULSEONDURATION_0: 0 pulse
+  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
+  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
+  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
+  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
+  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
+  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
+  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
+  * @retval None
+  */
+#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                \
+        do{                                                                       \
+            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
+            LCD_WaitForSynchro(__HANDLE__);                                       \
+           }while(0)
+
+/**
+  * @brief  Macro to configure the LCD dead time.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __DEADTIME__: specifies the LCD dead time.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_DEADTIME_0: No dead Time
+  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
+  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame 
+  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
+  * @retval None
+  */
+#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                        \
+        do{                                                                        \
+            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
+            LCD_WaitForSynchro(__HANDLE__);                                        \
+           }while(0)
+
+/**
+  * @brief  Macro to configure the LCD Contrast.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __CONTRAST__: specifies the LCD Contrast.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
+  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
+  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
+  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
+  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
+  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
+  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
+  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
+  * @retval None
+  */
+#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                       \
+        do{                                                                       \
+            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
+            LCD_WaitForSynchro(__HANDLE__);                                       \
+           } while(0) 
+
+/**
+  * @brief  Macro to configure the LCD Blink mode and Blink frequency.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __BLINKMODE__: specifies the LCD blink mode.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
+  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
+  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8 
+  *                                       pixels according to the programmed duty)
+  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM 
+  *                                       (all pixels)
+  * @param  __BLINKFREQUENCY__: specifies the LCD blink frequency.
+  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
+  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
+  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
+  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64 
+  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
+  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
+  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
+  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
+  * @retval None
+  */
+#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)  \
+        do{                                                                    \
+            MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
+            LCD_WaitForSynchro(__HANDLE__);                                    \
+          }while(0)
+
+/** @brief  Enables or disables the specified LCD interrupt.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                                \
+                         do{                                                          \
+                             SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));   \
+                             LCD_WaitForSynchro(__HANDLE__);                          \
+                            }while(0)         
+#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                               \
+                         do{                                                          \
+                             CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
+                             LCD_WaitForSynchro(__HANDLE__);                          \
+                            }while(0)
+
+/** @brief  Checks whether the specified LCD interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __IT__: specifies the LCD interrupt source to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_IT_SOF: Start of Frame Interrupt
+  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
+  * @note If the device is in STOP mode (PCLK not provided) UDD will not 
+  *          generate an interrupt even if UDDIE = 1. 
+  *          If the display is not enabled the UDD interrupt will never occur.
+  * @retval The state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
+
+/** @brief  Checks whether the specified LCD flag is set or not.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR 
+  *             goes from 0 to 1. On deactivation it reflects the real status of 
+  *             LCD so it becomes 0 at the end of the last displayed frame.  
+  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at 
+  *             the beginning of a new frame, at the same time as the display data is 
+  *             updated.
+  *        @arg LCD_FLAG_UDR: Update Display Request flag.
+  *        @arg LCD_FLAG_UDD: Update Display Done flag. 
+  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status 
+  *             of the step-up converter.
+  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. 
+  *             This flag is set by hardware each time the LCD_FCR register is updated 
+  *             in the LCDCLK domain. 
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
+
+/** @brief  Clears the specified LCD pending flag.
+  * @param  __HANDLE__: specifies the LCD Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be any combination of the following values:
+  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
+  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CLR = (__FLAG__))
+
+/**
+  * @}
+  */
+  
+/* Exported functions ------------------------------------------------------- */
+
+/** @defgroup LCD_Exported_Functions LCD Exported Functions
+  * @{
+  */
+
+/** @defgroup LCD_Exported_Functions_Group1 Initialization and de-initialization methods
+  * @{
+  */
+
+/* Initialization/de-initialization methods  **********************************/
+HAL_StatusTypeDef     HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef     HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
+void                  HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
+void                  HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
+  * @{
+  */
+
+/* IO operation methods *******************************************************/
+HAL_StatusTypeDef     HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
+HAL_StatusTypeDef     HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
+HAL_StatusTypeDef     HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
+  * @{
+  */
+
+/* Peripheral State methods  **************************************************/
+HAL_LCD_StateTypeDef  HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
+uint32_t              HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup LCD_Private
+  * @{
+  */
+
+/* Private functions ---------------------------------------------------------*/
+HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
+
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup LCD_Private LCD Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_LCD_H */
+
+/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
new file mode 100755
index 0000000..8bd6309
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h
@@ -0,0 +1,743 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_lptim.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_LPTIM_H
+#define __STM32L0xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LPTIM LPTIM (Low power timer)
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+  * @{
+  */
+
+/** @defgroup LPTIM_Clock_Configuration LPTIM Clock configuration structure
+  * @{
+  */
+#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  ((uint32_t)EXTI_IMR_IM29)  /*!< External interrupt line 29 Connected to the LPTIM EXTI Line */
+
+/** 
+  * @brief  LPTIM Clock configuration definition  
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Selects the clock source.
+                           This parameter can be a value of @ref LPTIM_Clock_Source   */
+
+  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
+                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+  
+}LPTIM_ClockConfigTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_ULPClock_Configuration LPTIM ULP Clock configuration structure
+  * @{
+  */
+/** 
+  * @brief  LPTIM ULP Clock configuration definition
+  */
+typedef struct
+{
+  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
+                           if the ULPTIM input is selected.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           Note: If the polarity is configured on 'both edges', an auxiliary clock
+                           (one of the Low power oscillator) must be active.
+                           This parameter can be a value of @ref LPTIM_Clock_Polarity */ 
+  
+  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */  
+  
+}LPTIM_ULPClockConfigTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Configuration LPTIM Trigger configuration structure
+  * @{
+  */
+/** 
+  * @brief  LPTIM Trigger configuration structure
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Selects the Trigger source.
+                          This parameter can be a value of @ref LPTIM_Trigger_Source */
+  
+  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+  
+  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */  
+}LPTIM_TriggerConfigTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Init_Configuration LPTIM Initialization configuration structure
+  * @{
+  */
+/** 
+  * @brief  LPTIM Initialization Structure definition  
+  */
+typedef struct
+{                                                    
+  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
+                                                    
+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
+                                                    
+  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
+                                                    
+  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
+                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
+                                                    
+  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare
+                                                    values is done immediately or after the end of current period.
+                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
+                                                    or each external event.
+                                                    This parameter can be a value of @ref LPTIM_Counter_Source */  
+  
+}LPTIM_InitTypeDef;
+/**
+  * @}
+  */
+/** @defgroup LPTIM_State_structure  LPTIM state definition
+  * @{
+  */
+/** 
+  * @brief  HAL LPTIM State structure definition  
+  */ 
+typedef enum __HAL_LPTIM_StateTypeDef
+{
+  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */    
+  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */  
+  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                */                                                                             
+}HAL_LPTIM_StateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Handle  LPTIM handler
+  * @{
+  */
+/** 
+  * @brief  LPTIM handle Structure definition  
+  */ 
+typedef struct
+{
+      LPTIM_TypeDef              *Instance;         /*!< Register base address     */
+      
+      LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
+  
+      HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */  
+  
+      HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
+  
+   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
+  
+}LPTIM_HandleTypeDef;
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported constants
+  * @{
+  */
+
+/* Check autoreload value */
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFU)
+
+/* Check compare value */
+#define IS_LPTIM_COMPARE(__COMPARE__)          ((__COMPARE__) <= 0x0000FFFFU)
+
+/** @defgroup LPTIM_Clock_Source Clock source
+  * @{
+  */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00U)
+#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
+/**                                             
+  * @}
+  */
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+
+/** @defgroup LPTIM_Clock_Prescaler Prescaler
+  * @{
+  */
+#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000U)
+#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
+#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
+/**
+  * @}
+  */
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
+
+
+/** @defgroup LPTIM_Output_Polarity Output polarity
+  * @{
+  */
+#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000U)
+#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
+/**
+  * @}
+  */
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+
+/** @defgroup LPTIM_Clock_Sample_Time Clock sample time
+  * @{
+  */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT
+/**
+  * @}
+  */
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
+                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
+                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+/** @defgroup LPTIM_Clock_Polarity Clock polarity
+  * @{
+  */
+#define LPTIM_CLOCKPOLARITY_RISING                   ((uint32_t)0x00000000U)
+#define LPTIM_CLOCKPOLARITY_FALLING                  LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING           LPTIM_CFGR_CKPOL_1
+/**
+  * @}
+  */
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+/** @defgroup LPTIM_External_Trigger_Polarity Trigger polarity
+  * @{
+  */
+#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
+/**
+  * @}
+  */
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)   (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
+                                                ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
+                                                ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+/** @defgroup LPTIM_Trigger_Sample_Time Trigger sample time
+  * @{
+  */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000U)
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS       LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS       LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS       LPTIM_CFGR_TRGFLT
+/**
+  * @}
+  */
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
+
+
+/** @defgroup LPTIM_Updating_Mode Updating mode
+  * @{
+  */
+
+#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000U)
+#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
+/**
+  * @}
+  */
+#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+
+
+/** @defgroup LPTIM_Counter_Source Counter source
+  * @{
+  */
+#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000U)
+#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
+/**
+  * @}
+  */
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+
+
+/* Check for period value */
+#define IS_LPTIM_PERIOD(__PERIOD__)               ((__PERIOD__) <= 0x0000FFFFU)
+
+/* Check for pulse value */
+#define IS_LPTIM_PULSE(__PULSE__)                 ((__PULSE__) <= 0x0000FFFFU)
+
+/** @defgroup LPTIM_Flag_Definition Flag definition
+  * @{
+  */
+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
+#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
+#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Interrupts_Definition Interrupts definition
+  * @{
+  */
+#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
+#define LPTIM_IT_UP                              LPTIM_IER_UPIE
+#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
+#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
+#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
+#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
+#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @brief Reset LPTIM handle state
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+
+/**
+  * @brief  Enable/Disable the LPTIM peripheral.
+  * @param  __HANDLE__: LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
+#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Starts the LPTIM peripheral in Continuous or in single mode.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
+ 
+    
+/**
+  * @brief  Writes the passed parameter in the Autoreload register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__ : Autoreload value
+  * @retval None
+  */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
+
+/**
+  * @brief  Writes the passed parameter in the Compare register.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __VALUE__ : Compare value
+  * @retval None
+  */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
+
+/**
+  * @brief  Checks whether the specified LPTIM flag is set or not.
+  * @param  __HANDLE__: LPTIM handle
+  * @param  __FLAG__  : LPTIM flag to check
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval The state of the specified flag (SET or RESET).
+  */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clears the specified LPTIM flag.
+  * @param  __HANDLE__: LPTIM handle.
+  * @param  __FLAG__  : LPTIM flag to clear.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
+  * @retval None.
+  */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))
+
+/**
+  * @brief  Enable the specified LPTIM interrupt.
+  * @param  __HANDLE__    : LPTIM handle.
+  * @param  __INTERRUPT__ : LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None.
+  */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
+
+ /**
+  * @brief  Disable the specified LPTIM interrupt.
+  * @param  __HANDLE__    : LPTIM handle.
+  * @param  __INTERRUPT__ : LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval None.
+  */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
+
+  /**
+  * @brief  Checks whether the specified LPTIM interrupt is set or not.
+  * @param  __HANDLE__    : LPTIM handle.
+  * @param  __INTERRUPT__ : LPTIM interrupt to check.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
+  * @retval Interrupt status.
+  */
+    
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. 
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief  Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+  * @brief  Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
+                                                                     __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
+                                                                    }while(0)
+
+/**
+  * @brief  Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
+                                                                      __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+                                                                     }while(0)
+
+/**
+  * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
+  * @retval Line Status.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
+  * @retval None.
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+  * @}
+  */
+
+
+/* Include LPTIM HAL Extension module */
+#include "stm32l0xx_hal_lptim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+
+/* MSP functions  *************************************************************/
+
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+
+/**
+  * @}
+  */
+
+/* Start/Stop operation functions  *********************************************/
+
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
+  * @{
+  */
+
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out  Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/**
+  * @}
+  */
+
+/* Reading operation functions ************************************************/
+
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
+  * @{
+  */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
+
+/* LPTIM IRQ functions  *******************************************************/
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler
+  * @{
+  */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions  ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
+/* Peripheral State functions  ************************************************/
+/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions
+  * @{
+  */
+
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim_ex.h
new file mode 100755
index 0000000..d38c9f4
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim_ex.h
@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_lptim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPTIM Extended HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_LPTIM_EX_H
+#define __STM32L0xx_HAL_LPTIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LPTIMEx LPTIMEx
+  * @{
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup LPTIMEx_Exported_Constants LPTIMEx Exported Constants
+  * @{
+  */
+
+
+/** @defgroup LPTIM_Trigger_Source Trigger source
+  * @{
+  */
+#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFFU)
+#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000U)
+#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
+
+#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+    defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+    defined (STM32L031xx) || defined (STM32L041xx)
+#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#endif
+
+#define LPTIM_TRIGSOURCE_6                      ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+   /** @addtogroup LPTIMEx_Private
+  * @{
+  */
+#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
+  defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
+  defined (STM32L031xx) || defined (STM32L041xx)
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+#else
+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_LPTIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h
new file mode 100755
index 0000000..d3af2f8
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h
@@ -0,0 +1,808 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_PCD_H
+#define __STM32L0xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"  
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @{
+  */ 
+
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/ 
+
+   /** 
+  * @brief  PCD State structures definition  
+  */  
+typedef enum 
+{
+  HAL_PCD_STATE_RESET    = 0x00U,
+  HAL_PCD_STATE_READY    = 0x01U,
+  HAL_PCD_STATE_ERROR    = 0x02U,
+  HAL_PCD_STATE_BUSY     = 0x03U,
+  HAL_PCD_STATE_TIMEOUT  = 0x04U
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum  
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+}PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  /* double buffered endpoint direction */
+  PCD_EP_DBUF_OUT,
+  PCD_EP_DBUF_IN,
+  PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/* endpoint buffer number */
+typedef enum 
+{
+  PCD_EP_NOBUF,
+  PCD_EP_BUF0,
+  PCD_EP_BUF1
+}PCD_EP_BUF_NUM;  
+
+
+/** 
+  * @brief  PCD Initialization Structure definition  
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 
+
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref PCD_Speed                */ 
+                             
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref PCD_USB_EP0_MPS                   */ 
+                       
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref PCD_USB_Core_PHY                  */ 
+                                
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.
+                                      This parameter can be set to ENABLE or DISABLE                        */  
+  
+  uint32_t low_power_enable;       /*!< Enable or disable Low Power mode
+                                        This parameter can be set to ENABLE or DISABLE                      */ 
+  
+  uint32_t lpm_enable;             /*!< Enable or disable Link Power Management.
+                                        This parameter can be set to ENABLE or DISABLE */ 
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
+                                         This parameter can be set to ENABLE or DISABLE */ 
+                                
+}PCD_InitTypeDef;
+
+typedef struct
+{
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
+                                
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref PCD_USB_EP_Type                     */ 
+                                
+  uint16_t  pmaadress;      /*!< PMA Address
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */ 
+  
+  
+  uint16_t  pmaaddr0;       /*!< PMA Address0
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */   
+  
+  
+  uint16_t  pmaaddr1;        /*!< PMA Address1
+                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */   
+  
+  
+  uint8_t   doublebuffer;    /*!< Double buffer enable
+                                 This parameter can be 0 or 1                                             */    
+                                
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+                                
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+}PCD_EPTypeDef;
+
+typedef   USB_TypeDef PCD_TypeDef; 
+
+/** 
+  * @brief  PCD Handle Structure definition  
+  */ 
+typedef struct
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
+  PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address            */  
+  PCD_EPTypeDef           IN_ep[8];  /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[8]; /*!< OUT endpoint parameters            */ 
+  HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
+  uint32_t                Setup[12];  /*!< Setup packet buffer                */
+    PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
+  uint32_t                BESL;
+  
+  
+  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+
+  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+  void                    *pData;      /*!< Pointer to upper stack Handler     */    
+  
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+#include "stm32l0xx_hal_pcd_ex.h"    
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_EndPoint PCD End Point
+  * @{
+  */
+
+
+#define PCD_ENDP0                             ((uint8_t)0U)
+#define PCD_ENDP1                             ((uint8_t)1U)
+#define PCD_ENDP2                             ((uint8_t)2U)
+#define PCD_ENDP3                             ((uint8_t)3U)
+#define PCD_ENDP4                             ((uint8_t)4U)
+#define PCD_ENDP5                             ((uint8_t)5U)
+#define PCD_ENDP6                             ((uint8_t)6U)
+#define PCD_ENDP7                             ((uint8_t)7U)
+
+/*  Endpoint Kind */
+#define PCD_SNG_BUF                                      0U
+#define PCD_DBL_BUF                                      1U
+
+#define IS_PCD_ALL_INSTANCE            IS_USB_ALL_INSTANCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_HIGH               0U /* Not Supported */
+#define PCD_SPEED_FULL               2U
+/**
+  * @}
+  */
+  
+  /** @defgroup PCD_USB_Core_PHY PCD USB Core PHY
+  * @{
+  */
+#define PCD_PHY_EMBEDDED             2U
+/**
+  * @}
+  */
+
+  /** @defgroup PCD_USB_EP0_MPS PCD USB EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0U
+#define DEP0CTL_MPS_32                         1U
+#define DEP0CTL_MPS_16                         2U
+#define DEP0CTL_MPS_8                          3U
+
+#define PCD_EP0MPS_64                          DEP0CTL_MPS_64
+#define PCD_EP0MPS_32                          DEP0CTL_MPS_32
+#define PCD_EP0MPS_16                          DEP0CTL_MPS_16
+#define PCD_EP0MPS_08                          DEP0CTL_MPS_8 
+/**
+  * @}
+  */ 
+  
+/** @defgroup PCD_USB_EP_Type PCD USB EP Type
+  * @{
+  */
+#define PCD_EP_TYPE_CTRL                                 0U
+#define PCD_EP_TYPE_ISOC                                 1U
+#define PCD_EP_TYPE_BULK                                 2U
+#define PCD_EP_TYPE_INTR                                 3U
+/**
+  * @}
+  */
+
+  
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PCD_Interrupt_Clock PCD Interrupt
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->ISTR) &= (uint16_t) ~(__INTERRUPT__))
+
+#define  USB_WAKEUP_EXTI_LINE              (EXTI_IMR_IM18)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_WAKEUP_EXTI_LINE)
+
+/* Internal macros -----------------------------------------------------------*/
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&USBx->EP0R + bEpNum * 2U)= (uint16_t)wRegValue)
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum)        (*(&USBx->EP0R + bEpNum * 2U))
+
+
+
+/**
+  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wType: Endpoint Type.
+  * @retval None
+  */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT(USBx, bEpNum,\
+                                  ((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_T_MASK) | wType )))
+
+/**
+  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Endpoint Type
+  */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_T_FIELD)
+
+
+/**
+  * @brief free buffer used from the application realizing it to the line
+  *         toggles bit SW_BUF in the double buffered endpoint register
+  * @param  USBx: USB device.
+  * @param   bEpNum, bDir
+  * @retval None
+  */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+do {\
+  if (bDir == PCD_EP_DBUF_OUT)\
+  { /* OUT double buffered endpoint */\
+    PCD_TX_DTOG(USBx, bEpNum);\
+  }\
+  else if (bDir == PCD_EP_DBUF_IN)\
+  { /* IN double buffered endpoint */\
+    PCD_RX_DTOG(USBx, bEpNum);\
+  }\
+} while(0)
+
+/**
+  * @brief gets direction of the double buffered endpoint
+  * @param  USBx: USB device.
+  * @param   bEpNum: Endpoint Number.
+  * @retval EP_DBUF_OUT, EP_DBUF_IN,
+  *         EP_DBUF_ERR if the endpoint counter not yet programmed.
+  */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+do {\
+  if ((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum) & 0xFC00U) != 0U)\
+    return(PCD_EP_DBUF_OUT);\
+  else if (((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x03FFU) != 0U)\
+    return(PCD_EP_DBUF_IN);\
+  else\
+    return(PCD_EP_DBUF_ERR);\
+} while(0)
+
+/**
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do {\
+   register uint16_t _wRegVal;       \
+   \
+    _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_DTOGMASK;\
+   /* toggle first bit ? */     \
+   if((USB_EPTX_DTOG1 & wState)!= 0U)      \
+     _wRegVal ^= USB_EPTX_DTOG1;        \
+   /* toggle second bit ?  */         \
+   if((USB_EPTX_DTOG2 & wState)!= 0U)      \
+     _wRegVal ^= USB_EPTX_DTOG2;        \
+   PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));    \
+  } while(0) /* PCD_SET_EP_TX_STATUS */
+
+/**
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wState: new state
+  * @retval None
+  */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do {\
+    register uint16_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_DTOGMASK;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & wState)!= 0U) \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & wState)!= 0U) \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    PCD_SET_ENDPOINT(USBx, bEpNum, (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+  } while(0) /* PCD_SET_EP_RX_STATUS */
+
+/**
+  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wStaterx: new state.
+  * @param  wStatetx: new state.
+  * @retval None
+  */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) do {\
+    register uint32_t _wRegVal;   \
+    \
+    _wRegVal = PCD_GET_ENDPOINT(USBx, bEpNum) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+    /* toggle first bit ? */  \
+    if((USB_EPRX_DTOG1 & wStaterx)!= 0U) \
+      _wRegVal ^= USB_EPRX_DTOG1;  \
+    /* toggle second bit ? */  \
+    if((USB_EPRX_DTOG2 & wStaterx)!= 0U) \
+      _wRegVal ^= USB_EPRX_DTOG2;  \
+    /* toggle first bit ? */     \
+    if((USB_EPTX_DTOG1 & wStatetx)!= 0U)      \
+      _wRegVal ^= USB_EPTX_DTOG1;        \
+    /* toggle second bit ?  */         \
+    if((USB_EPTX_DTOG2 & wStatetx)!= 0U)      \
+      _wRegVal ^= USB_EPTX_DTOG2;        \
+    PCD_SET_ENDPOINT(USBx, bEpNum, _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
+  } while(0) /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
+  *         /STAT_RX[1:0])
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval status
+  */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPTX_STAT)
+
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPRX_STAT)
+
+/**
+  * @brief  sets directly the VALID tx/rx-status into the endpoint register
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum)     (PCD_SET_EP_TX_STATUS(USBx, bEpNum, USB_EP_TX_VALID))
+
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum)     (PCD_SET_EP_RX_STATUS(USBx, bEpNum, USB_EP_RX_VALID))
+
+/**
+  * @brief  checks stall condition in an endpoint.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval TRUE = endpoint in stall condition.
+  */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS(USBx, bEpNum) \
+                                   == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS(USBx, bEpNum) \
+                                   == USB_EP_RX_STALL)
+
+/**
+  * @brief  set & clear EP_KIND bit.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT(USBx, bEpNum, \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT(USBx, bEpNum) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT(USBx, bEpNum, \
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPKIND_MASK))))
+
+/**
+  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum)    PCD_SET_EP_KIND(USBx, bEpNum)
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)  PCD_CLEAR_EP_KIND(USBx, bEpNum)
+
+/**
+  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF(USBx, bEpNum)   PCD_SET_EP_KIND(USBx, bEpNum)
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND(USBx, bEpNum)
+
+/**
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT(USBx, bEpNum,\
+                                   PCD_GET_ENDPOINT(USBx, bEpNum) & 0x7FFFU & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT(USBx, bEpNum,\
+                                   PCD_GET_ENDPOINT(USBx, bEpNum) & 0xFF7FU & USB_EPREG_MASK))
+
+/**
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT(USBx, bEpNum, \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT(USBx, bEpNum, \
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK)))
+
+/**
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_DTOG_RX) != 0)\
+    PCD_RX_DTOG(USBx, bEpNum)
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EP_DTOG_TX) != 0)\
+    PCD_TX_DTOG(USBx, bEpNum)
+      
+/**
+  * @brief  Sets address in an endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bAddr: Address.
+  * @retval None
+  */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT(USBx, bEpNum,\
+    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPREG_MASK) | bAddr)
+
+/**
+  * @brief  Gets address in an endpoint register.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT(USBx, bEpNum) & USB_EPADDR_FIELD))
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U)+     ((uint32_t)USBx + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+2U)+  ((uint32_t)USBx + 0x400U)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+4U)+  ((uint32_t)USBx + 0x400U)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8U+6U)+  ((uint32_t)USBx + 0x400U)))
+
+/**
+  * @brief  sets address of the tx/rx buffer.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wAddr: address to be set (must be word aligned).
+  * @retval None
+  */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS(USBx, bEpNum) = ((wAddr >> 1U) << 1U))
+
+/**
+  * @brief  Gets address of the tx/rx buffer.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval address of the buffer.
+  */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS(USBx, bEpNum))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS(USBx, bEpNum))
+
+/**
+  * @brief  Sets counter of rx buffer with no. of blocks.
+  * @param  dwReg: Register.
+  * @param  wCount: Counter.
+  * @param  wNBlocks: Nb of block
+  * @retval None
+  */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) do {\
+    wNBlocks = wCount >> 5;\
+    if((wCount & 0x1f) == 0)\
+      wNBlocks--;\
+    *pdwReg = (uint16_t)((wNBlocks << 10U) | 0x8000U);\
+  } while(0) /* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) do {\
+    wNBlocks = wCount >> 1;\
+    if((wCount & 0x1) != 0)\
+      wNBlocks++;\
+    *pdwReg = (uint16_t)(wNBlocks << 10U);\
+  } while(0) /* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  do {\
+    uint16_t wNBlocks;\
+    if(wCount > 62){PCD_CALC_BLK32(dwReg,wCount,wNBlocks);}\
+    else {PCD_CALC_BLK2(dwReg,wCount,wNBlocks);}\
+  } while(0) /* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) do {\
+    uint16_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+  } while(0)
+/**
+  * @brief  sets counter for the tx/rx buffer.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wCount: Counter value.
+  * @retval None
+  */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT(USBx, bEpNum) = wCount)
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) do {\
+    uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+  } while(0)
+
+/**
+  * @brief  gets counter of the tx buffer.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval Counter value
+  */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT(USBx, bEpNum)) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT(USBx, bEpNum)) & 0x3ffU)
+
+/**
+  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @retval Counter value
+  */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wBuf0Addr);}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wBuf1Addr);}
+
+/**
+  * @brief  Sets addresses in a double buffer endpoint.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  wBuf0Addr: buffer 0 address.
+  * @param  wBuf1Addr = buffer 1 address.
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+    PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr);\
+    PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr);\
+  } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS(USBx, bEpNum))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS(USBx, bEpNum))
+
+/**
+  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT and EP_DBUF_IN  = IN
+  * @param  wCount: Counter value 
+  * @retval None
+  */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if(bDir == PCD_EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount);} \
+    else if(bDir == PCD_EP_DBUF_IN)\
+      /* IN endpoint */ \
+      *PCD_EP_TX_CNT(USBx, bEpNum) = (uint32_t)wCount;  \
+  } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
+    if(bDir == PCD_EP_DBUF_OUT)\
+      /* OUT endpoint */ \
+    {PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount);}\
+    else if(bDir == PCD_EP_DBUF_IN)\
+      /* IN endpoint */\
+      *PCD_EP_RX_CNT(USBx, bEpNum) = (uint32_t)wCount; \
+  } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do {\
+    PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount); \
+    PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount); \
+  } while(0) /* PCD_SET_EP_DBUF_CNT  */
+
+/**
+  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
+  * @param  USBx: USB device.
+  * @param  bEpNum: Endpoint Number.
+  * @retval None
+  */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT(USBx, bEpNum))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT(USBx, bEpNum))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+/** @defgroup PCD_Exported_Functions_Group2 IO Data transfers functions
+ *  @brief   Data transfers functions
+ *  @{
+ */
+
+ /* I/O operation functions  *****************************************************/
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   management functions
+ *  @{
+ */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+/**
+  * @}
+  */
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
+ *  @{
+ */
+
+/* Peripheral State functions  **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup PCD_Private PCD Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L0xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h
new file mode 100755
index 0000000..e155f67
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h
@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_PCD_EX_H
+#define __STM32L0xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"  
+   
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+typedef enum  
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+
+typedef enum  
+{
+  PCD_BCD_ERROR                     = 0xFF, 
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+  
+}PCD_BCD_MsgTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx__Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ */
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
+                                     uint16_t ep_addr,
+                                     uint16_t ep_kind,
+                                     uint32_t pmaadress);
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L0xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h
new file mode 100755
index 0000000..544702f
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h
@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_rng.h
+
+  * @author  MCD Application Team
+  * @brief   Header file of RNG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_RNG_H
+#define __STM32L0xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) ||  defined (STM32L063xx) || \
+    defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) ||  defined (STM32L083xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RNG RNG
+  * @brief RNG HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup RNG_Exported_Types RNG Exported Types
+  * @{
+  */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition 
+  * @{
+  */
+typedef enum
+{
+  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
+    
+}HAL_RNG_StateTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   
+  * @{
+  */ 
+typedef struct
+{
+  RNG_TypeDef                 *Instance;    /*!< Register base address   */ 
+  
+  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
+  
+  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
+  
+  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
+  
+}RNG_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+   
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
+  * @{
+  */ 
+#define RNG_IT_DRDY  ((uint32_t)RNG_SR_DRDY)  /*!< Data ready interrupt */
+#define RNG_IT_CEI   ((uint32_t)RNG_SR_CEIS)  /*!< Clock error interrupt */
+#define RNG_IT_SEI   ((uint32_t)RNG_SR_SEIS)  /*!< Seed error interrupt  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
+  * @{
+  */ 
+#define RNG_FLAG_DRDY   ((uint32_t)RNG_SR_DRDY)  /*!< Data ready                 */
+#define RNG_FLAG_CECS   ((uint32_t)RNG_SR_CECS)  /*!< Clock error current status */
+#define RNG_FLAG_SECS   ((uint32_t)RNG_SR_SECS)  /*!< Seed error current status  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @brief Reset RNG handle state
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+  * @brief  Enables the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
+
+/**
+  * @brief  Disables the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+  * @brief  Check the selected RNG flag status.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY:  Data ready                
+  *            @arg RNG_FLAG_CECS:  Clock error current status
+  *            @arg RNG_FLAG_SECS:  Seed error current status 
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+
+/**
+  * @brief  Clears the selected RNG flag status.
+  * @param  __HANDLE__: RNG handle
+  * @param  __FLAG__: RNG flag to clear  
+  * @note   WARNING: This is a dummy macro for HAL code alignment,
+  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
+
+
+
+/**
+  * @brief  Enables the RNG interrupts.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
+    
+/**
+  * @brief  Disables the RNG interrupts.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RNG_IT_DRDY: Data ready interrupt              
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+
+/**
+  * @brief  Clears the RNG interrupt status flags.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:            
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+  * @}
+  */ 
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */  
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */ 
+
+/* Peripheral Control functions  ************************************************/
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+
+/**
+  * @}
+  */ 
+
+/* Peripheral State functions  **************************************************/
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup RNG_Private RNG Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+#endif /*  if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) ||  defined (STM32L063xx) || \
+           defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) ||  defined (STM32L083xx)         */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_RNG_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h
new file mode 100755
index 0000000..6c02d07
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard.h
@@ -0,0 +1,1095 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smartcard.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMARTCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_SMARTCARD_H
+#define __STM32L0xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+  * @{
+  */
+
+/**
+  * @brief SMARTCARD Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+  uint16_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref SMARTCARD_Parity
+                                           @note The parity is enabled by default (PCE is forced to 1).
+                                                 Since the WordLength is forced to 8 bits + parity, M is
+                                                 forced to 1 and the parity bit is the 9th bit. */
+
+  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Mode */
+
+  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
+
+  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
+                                           in case of parity error.
+                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
+                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
+                                           it is used to implement the Character Wait Time (CWT) and
+                                           Block Wait Time (BWT). It is coded over 24 bits. */
+
+  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+                                           This parameter can be any value from 0x0 to 0xFF */
+
+  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
+                                            receive and transmit mode). When set to 0, retransmission is
+                                            disabled. Otherwise, its maximum value is 7 (before signalling
+                                            an error) */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+  * @brief  SMARTCARD advanced features initalization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
+                                           advanced features may be initialized at the same time. This parameter
+                                           can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+
+  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
+
+  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
+
+  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
+                                           vs negative/inverted logic).
+                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
+                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
+                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL SMARTCARD State structures definition
+  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains SMARTCARD state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing 
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                        Value is allowed for RxState only */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                        Not to be used for neither gState nor RxState.
+                                                        Value is result of combination (Or) between gState and RxState values */
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
+                                                        Value is allowed for gState only */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+  * @brief  HAL SMARTCARD Error Code structure definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error                */
+  HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error            */
+  HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error             */
+  HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error             */
+  HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error           */
+  HAL_SMARTCARD_ERROR_DMA       = 0x10,    /*!< DMA transfer error      */
+  HAL_SMARTCARD_ERROR_RTO       = 0x20     /*!< Receiver TimeOut error  */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/**
+  * @brief  SMARTCARD handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
+
+  SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
+
+  SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
+
+  uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
+
+  uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
+
+  __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
+
+  uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
+
+  uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
+
+  __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
+
+  DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
+
+  DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
+
+  HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
+
+  __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management 
+                                                         and also related to Tx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  __IO uint32_t                   ErrorCode;        /*!< SmartCard Error code                                  */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+  * @brief  SMARTCARD clock sources
+  */
+typedef enum
+{
+  SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source     */
+  SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01U, /*!< PCLK2 clock source     */
+  SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source       */
+  SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source    */
+  SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source       */
+  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+  * @{
+  */
+#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+  * @{
+  */
+#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
+#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+  * @{
+  */
+#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+  * @{
+  */
+#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
+#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
+#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+  * @{
+  */
+#define SMARTCARD_POLARITY_LOW              ((uint32_t)0x00000000)                   /*!< SMARTCARD frame low polarity  */
+#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+  * @{
+  */
+#define SMARTCARD_PHASE_1EDGE               ((uint32_t)0x00000000)                  /*!< SMARTCARD frame phase on first clock transition  */
+#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+  * @{
+  */
+#define SMARTCARD_LASTBIT_DISABLE           ((uint32_t)0x00000000)                 /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+  * @{
+  */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)                 /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
+/**
+  * @}
+  */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE              ((uint32_t)0x00000000)                /*!< SMARTCARD NACK transmission enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+  * @{
+  */
+#define SMARTCARD_TIMEOUT_DISABLE           ((uint32_t)0x00000000)                /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA Requests
+  * @{
+  */
+
+#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)
+#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  ((uint32_t)0x00000000U)               /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  ((uint32_t)0x00000000U)               /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  ((uint32_t)0x00000000U)             /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000U)               /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000U)             /*!< RX overrun enable  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   ((uint32_t)0x00000000U)        /*!< DMA enable on Reception Error  */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000U)          /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+  * @{
+  */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
+/**
+  * @}
+  */
+
+
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
+#define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
+#define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
+#define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
+#define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+  
+#define SMARTCARD_IT_PE                          ((uint16_t)0x0028U)    /*!< SMARTCARD parity error interruption                 */
+#define SMARTCARD_IT_TXE                         ((uint16_t)0x0727U)    /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC                          ((uint16_t)0x0626U)    /*!< SMARTCARD transmission complete interruption        */
+#define SMARTCARD_IT_RXNE                        ((uint16_t)0x0525U)    /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE                        ((uint16_t)0x0424U)    /*!< SMARTCARD idle line detection interruption          */
+
+#define SMARTCARD_IT_ERR                         ((uint16_t)0x0060U)    /*!< SMARTCARD error interruption         */
+#define SMARTCARD_IT_ORE                         ((uint16_t)0x0300U)    /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE                          ((uint16_t)0x0200U)    /*!< SMARTCARD noise error interruption   */
+#define SMARTCARD_IT_FE                          ((uint16_t)0x0100U)    /*!< SMARTCARD frame error interruption   */
+
+#define SMARTCARD_IT_EOB                         ((uint16_t)0x0C3BU)    /*!< SMARTCARD end of block interruption     */
+#define SMARTCARD_IT_RTO                         ((uint16_t)0x0B3AU)    /*!< SMARTCARD receiver timeout interruption */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags
+  * @{
+  */
+#define SMARTCARD_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */          
+#define SMARTCARD_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */         
+#define SMARTCARD_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */        
+#define SMARTCARD_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */         
+#define SMARTCARD_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */
+#define SMARTCARD_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */ 
+#define SMARTCARD_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */     
+#define SMARTCARD_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */          
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+  * @{
+  */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS       ((uint32_t) 17U)   /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+  * @{
+  */
+#define SMARTCARD_GTPR_GT_LSB_POS           ((uint32_t) 8U)   /*!<  SMARTCARD guard time value LSB position in GTPR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+  * @{
+  */
+#define SMARTCARD_RTOR_BLEN_LSB_POS         ((uint32_t) 24U)  /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+  * @{
+  */
+#define SMARTCARD_IT_MASK               ((uint16_t)0x001FU)   /*!< SMARTCARD interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMARTCARD handle states.
+  * @param  __HANDLE__: SMARTCARD handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
+                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                          } while(0)
+
+/** @brief  Flush the Smartcard Data registers.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
+    do{                                                                              \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified SMARTCARD pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the SMARTCARD PE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief  Clear the SMARTCARD FE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief  Clear the SMARTCARD NE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief  Clear the SMARTCARD ORE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief  Clear the SMARTCARD IDLE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
+  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
+  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
+  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
+  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag  
+  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
+  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
+  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
+  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief  Disable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt   
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
+  *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
+  *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) 
+
+/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
+                                                           (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
+                                                           (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag    
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific SMARTCARD request flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable the USART associated to the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable the USART associated to the SMARTCARD Handle
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/** @brief  Macros to enable or disable the SmartCard DMA request.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  *         The Handle Instance which can be USART1 or USART2.
+  * @param  __REQUEST__: specifies the SmartCard DMA request.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+  */
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
+
+/**
+  * @}
+  */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+  * @{
+  */
+
+/** @brief  Check the Baud rate range. 
+  * @note   The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz)
+  *         divided by the oversampling used on the SMARTCARD (i.e. 16).
+  * @param  __BAUDRATE__: Baud rate set by the configuration function.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001U)
+
+/** @brief  Check the block length range.
+  * @note   The maximum SMARTCARD block length is 0xFF.
+  * @param  __LENGTH__: block length.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief  Check the receiver timeout value. 
+  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__: receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief  Check the SMARTCARD autoretry counter value. 
+  * @note   The maximum number of retransmissions is 0x7.
+  * @param  __COUNT__: number of retransmissions.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
+
+/**
+  * @brief Ensure that SMARTCARD frame length is valid.
+  * @param __LENGTH__: SMARTCARD frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */ 
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+  * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+  * @param __STOPBITS__: SMARTCARD frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */ 
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/**
+  * @brief Ensure that SMARTCARD frame parity is valid.
+  * @param __PARITY__: SMARTCARD frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+  * @brief Ensure that SMARTCARD communication mode is valid.
+  * @param __MODE__: SMARTCARD communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+
+/**
+  * @brief Ensure that SMARTCARD frame polarity is valid.
+  * @param __CPOL__: SMARTCARD frame polarity. 
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */ 
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that SMARTCARD frame phase is valid.
+  * @param __CPHA__: SMARTCARD frame phase. 
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. 
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame sampling is valid.
+  * @param __ONEBIT__: SMARTCARD frame sampling. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+  * @param __NACK__: SMARTCARD NACK transmission setting. 
+  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+  */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+  * @param __TIMEOUT__: SMARTCARD receiver timeout setting. 
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD advanced features initialization is valid.
+  * @param __INIT__: SMARTCARD advanced features initialization. 
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
+                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
+                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
+                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+  * @param __TXINV__: SMARTCARD frame TX inversion setting. 
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+  * @param __RXINV__: SMARTCARD frame RX inversion setting. 
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+  * @param __DATAINV__: SMARTCARD frame data inversion setting. 
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+  * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. 
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame overrun setting is valid.
+  * @param __OVERRUN__: SMARTCARD frame overrun setting. 
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+  * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. 
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+  * @param __MSBFIRST__: SMARTCARD frame MSB first setting. 
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD request parameter is valid.
+  * @param __PARAM__: SMARTCARD request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32l0xx_hal_smartcard_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+  * @{
+  */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h
new file mode 100755
index 0000000..2f84a9d
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smartcard_ex.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smartcard_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMARTCARD HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_SMARTCARD_EX_H
+#define __STM32L0xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARDEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/  
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+  * @{
+  */
+  
+/** @brief  Report the SMARTCARD clock source.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART2)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+
+#else /* (STM32L031xx) || defined (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
+
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h
new file mode 100755
index 0000000..c46525e
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h
@@ -0,0 +1,699 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smbus.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMBUS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_SMBUS_H
+#define __STM32L0xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+  * @{
+  */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+  * @brief  SMBUS Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
+                                     This parameter calculated by referring to SMBUS initialization
+                                            section in Reference manual */
+  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
+                                     This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+                                     This parameter can be a value of @ref SMBUS_addressing_mode */
+
+  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+                                     This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
+                                     This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
+                                     This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+                                      (Enable bits and different timeout values)
+                                     This parameter calculated by referring to SMBUS initialization
+                                         section in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_definition HAL state definition
+  * @brief  HAL State definition
+  * @{
+  */
+#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
+#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
+#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
+#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
+#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+  * @brief  SMBUS Error Code definition
+  * @{
+  */
+#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
+#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
+#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
+#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
+#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
+#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
+#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+  * @brief  SMBUS handle Structure definition
+  * @{
+  */
+typedef struct
+{
+  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
+
+  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
+
+  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
+
+  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
+
+  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
+
+  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
+
+  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
+
+  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
+
+  __IO uint32_t                State;           /*!< SMBUS communication state          */
+
+  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
+
+} SMBUS_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+  * @{
+  */
+#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+  * @{
+  */
+#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
+#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+  * @{
+  */
+
+#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+  * @{
+  */
+
+#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+  * @{
+  */
+#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
+  * @{
+  */
+#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+  * @{
+  */
+#define SMBUS_PEC_DISABLE                       (0x00000000U)
+#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+  * @{
+  */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+  * @{
+  */
+
+#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
+#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
+#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
+#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+  * @{
+  */
+
+#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
+#define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+  * @{
+  */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
+#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
+#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
+#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+  * @brief SMBUS Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
+#define SMBUS_IT_TCI                            I2C_CR1_TCIE
+#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI                            I2C_CR1_RXIE
+#define SMBUS_IT_TXI                            I2C_CR1_TXIE
+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXXXXXX  : Flag mask
+  * @{
+  */
+
+#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
+#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
+#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
+#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
+#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
+#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
+#define  SMBUS_FLAG_TC                          I2C_ISR_TC
+#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
+#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
+#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
+#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
+#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
+#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
+#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
+#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
+#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMBUS handle state.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief  Enable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SMBUS flag is set or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
+  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define SMBUS_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Enable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+  * @{
+  */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
+                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
+                                                          ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
+                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \
+                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
+                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
+                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
+                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
+                                                          IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @{
+ */
+
+/* Peripheral State and Errors functions  **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l0xx_hal_smbus.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L0xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h
new file mode 100755
index 0000000..cacef33
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tsc.h
@@ -0,0 +1,659 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_tsc.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the TSC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_TSC_H
+#define __STM32L0xx_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TSC TSC
+  * @{
+  */ 
+
+   /** @defgroup TSC_Exported_Types TSC Exported Types
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief TSC state structure definition  
+  */ 
+typedef enum
+{
+  HAL_TSC_STATE_RESET  = 0x00U, /*!< TSC registers have their reset value */
+  HAL_TSC_STATE_READY  = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
+  HAL_TSC_STATE_BUSY   = 0x02U, /*!< TSC initialization or acquisition is on-going */
+  HAL_TSC_STATE_ERROR  = 0x03U  /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/** 
+  * @brief TSC group status structure definition  
+  */ 
+typedef enum
+{
+  TSC_GROUP_ONGOING   = 0x00U, /*!< Acquisition on group is on-going or not started */
+  TSC_GROUP_COMPLETED = 0x01U  /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/** 
+  * @brief TSC init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CTPulseHighLength;       /*!< Charge-transfer high pulse length */
+  uint32_t CTPulseLowLength;        /*!< Charge-transfer low pulse length */
+  uint32_t SpreadSpectrum;          /*!< Spread spectrum activation */
+  uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
+  uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
+  uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
+  uint32_t MaxCountValue;           /*!< Max count value */
+  uint32_t IODefaultMode;           /*!< IO default mode */
+  uint32_t SynchroPinPolarity;      /*!< Synchro pin polarity */
+  uint32_t AcquisitionMode;         /*!< Acquisition mode */
+  uint32_t MaxCountInterrupt;       /*!< Max count interrupt activation */
+  uint32_t ChannelIOs;              /*!< Channel IOs mask */
+  uint32_t ShieldIOs;               /*!< Shield IOs mask */
+  uint32_t SamplingIOs;             /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/** 
+  * @brief TSC IOs configuration structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ChannelIOs;  /*!< Channel IOs mask */
+  uint32_t ShieldIOs;   /*!< Shield IOs mask */
+  uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/** 
+  * @brief  TSC handle Structure definition  
+  */ 
+typedef struct
+{
+  TSC_TypeDef               *Instance; /*!< Register base address */
+  TSC_InitTypeDef           Init;      /*!< Initialization parameters */
+  __IO HAL_TSC_StateTypeDef State;     /*!< Peripheral state */
+  HAL_LockTypeDef           Lock;      /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+  * @{
+  */ 
+
+
+#define TSC_CTPH_1CYCLE   ((uint32_t)((uint32_t) 0U << 28U))
+#define TSC_CTPH_2CYCLES  ((uint32_t)((uint32_t) 1U << 28U))
+#define TSC_CTPH_3CYCLES  ((uint32_t)((uint32_t) 2U << 28U))
+#define TSC_CTPH_4CYCLES  ((uint32_t)((uint32_t) 3U << 28U))
+#define TSC_CTPH_5CYCLES  ((uint32_t)((uint32_t) 4U << 28U))
+#define TSC_CTPH_6CYCLES  ((uint32_t)((uint32_t) 5U << 28U))
+#define TSC_CTPH_7CYCLES  ((uint32_t)((uint32_t) 6U << 28U))
+#define TSC_CTPH_8CYCLES  ((uint32_t)((uint32_t) 7U << 28U))
+#define TSC_CTPH_9CYCLES  ((uint32_t)((uint32_t) 8U << 28U))
+#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9U << 28U))
+#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10U << 28U))
+#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11U << 28U))
+#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12U << 28U))
+#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13U << 28U))
+#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14U << 28U))
+#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15U << 28U))
+
+#define TSC_CTPL_1CYCLE   ((uint32_t)((uint32_t) 0U << 24U))
+#define TSC_CTPL_2CYCLES  ((uint32_t)((uint32_t) 1U << 24U))
+#define TSC_CTPL_3CYCLES  ((uint32_t)((uint32_t) 2U << 24U))
+#define TSC_CTPL_4CYCLES  ((uint32_t)((uint32_t) 3U << 24U))
+#define TSC_CTPL_5CYCLES  ((uint32_t)((uint32_t) 4U << 24U))
+#define TSC_CTPL_6CYCLES  ((uint32_t)((uint32_t) 5U << 24U))
+#define TSC_CTPL_7CYCLES  ((uint32_t)((uint32_t) 6U << 24U))
+#define TSC_CTPL_8CYCLES  ((uint32_t)((uint32_t) 7U << 24U))
+#define TSC_CTPL_9CYCLES  ((uint32_t)((uint32_t) 8U << 24U))
+#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9U << 24U))
+#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10U << 24U))
+#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11U << 24U))
+#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12U << 24U))
+#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13U << 24U))
+#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14U << 24U))
+#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15U << 24U))
+
+#define TSC_SS_PRESC_DIV1 ((uint32_t)0U)  
+#define TSC_SS_PRESC_DIV2  (TSC_CR_SSPSC) 
+
+#define TSC_PG_PRESC_DIV1   ((uint32_t)(0U << 12U))
+#define TSC_PG_PRESC_DIV2   ((uint32_t)(1U << 12U))
+#define TSC_PG_PRESC_DIV4   ((uint32_t)(2U << 12U))
+#define TSC_PG_PRESC_DIV8   ((uint32_t)(3U << 12U))
+#define TSC_PG_PRESC_DIV16  ((uint32_t)(4U << 12U))
+#define TSC_PG_PRESC_DIV32  ((uint32_t)(5U << 12U))
+#define TSC_PG_PRESC_DIV64  ((uint32_t)(6U << 12U))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
+#define TSC_MCV_255   ((uint32_t)(0U << 5U))
+#define TSC_MCV_511   ((uint32_t)(1U << 5U))
+#define TSC_MCV_1023  ((uint32_t)(2U << 5U))
+#define TSC_MCV_2047  ((uint32_t)(3U << 5U))
+#define TSC_MCV_4095  ((uint32_t)(4U << 5U))
+#define TSC_MCV_8191  ((uint32_t)(5U << 5U))
+#define TSC_MCV_16383 ((uint32_t)(6U << 5U))
+
+#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0U)
+#define TSC_IODEF_IN_FLOAT   (TSC_CR_IODEF)
+
+#define TSC_SYNC_POLARITY_FALLING      ((uint32_t)0U)
+#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
+
+#define TSC_ACQ_MODE_NORMAL  ((uint32_t)0U)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+
+#define TSC_IOMODE_UNUSED   ((uint32_t)0U)
+#define TSC_IOMODE_CHANNEL  ((uint32_t)1U)
+#define TSC_IOMODE_SHIELD   ((uint32_t)2U)
+#define TSC_IOMODE_SAMPLING ((uint32_t)3U)
+
+/** @defgroup TSC_interrupts_definition TSC Interrupts Definition
+  * @{
+  */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)  
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TSC_flags_definition TSC Flags Definition
+  * @{
+  */ 
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+  * @}
+  */
+
+#define TSC_NB_OF_GROUPS (8)
+
+#define TSC_GROUP1 ((uint32_t)0x00000001U)
+#define TSC_GROUP2 ((uint32_t)0x00000002U)
+#define TSC_GROUP3 ((uint32_t)0x00000004U)
+#define TSC_GROUP4 ((uint32_t)0x00000008U)
+#define TSC_GROUP5 ((uint32_t)0x00000010U)
+#define TSC_GROUP6 ((uint32_t)0x00000020U)
+#define TSC_GROUP7 ((uint32_t)0x00000040U)
+#define TSC_GROUP8 ((uint32_t)0x00000080U)
+#define TSC_ALL_GROUPS ((uint32_t)0x000000FFU)
+
+#define TSC_GROUP1_IDX ((uint32_t)0U)
+#define TSC_GROUP2_IDX ((uint32_t)1U)
+#define TSC_GROUP3_IDX ((uint32_t)2U)
+#define TSC_GROUP4_IDX ((uint32_t)3U)
+#define TSC_GROUP5_IDX ((uint32_t)4U)
+#define TSC_GROUP6_IDX ((uint32_t)5U)
+#define TSC_GROUP7_IDX ((uint32_t)6U)
+#define TSC_GROUP8_IDX ((uint32_t)7U)
+
+#define TSC_GROUP1_IO1 ((uint32_t)0x00000001U)
+#define TSC_GROUP1_IO2 ((uint32_t)0x00000002U)
+#define TSC_GROUP1_IO3 ((uint32_t)0x00000004U)
+#define TSC_GROUP1_IO4 ((uint32_t)0x00000008U)
+#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000FU)
+
+#define TSC_GROUP2_IO1 ((uint32_t)0x00000010U)
+#define TSC_GROUP2_IO2 ((uint32_t)0x00000020U)
+#define TSC_GROUP2_IO3 ((uint32_t)0x00000040U)
+#define TSC_GROUP2_IO4 ((uint32_t)0x00000080U)
+#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0U)
+
+#define TSC_GROUP3_IO1 ((uint32_t)0x00000100U)
+#define TSC_GROUP3_IO2 ((uint32_t)0x00000200U)
+#define TSC_GROUP3_IO3 ((uint32_t)0x00000400U)
+#define TSC_GROUP3_IO4 ((uint32_t)0x00000800U)
+#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00U)
+
+#define TSC_GROUP4_IO1 ((uint32_t)0x00001000U)
+#define TSC_GROUP4_IO2 ((uint32_t)0x00002000U)
+#define TSC_GROUP4_IO3 ((uint32_t)0x00004000U)
+#define TSC_GROUP4_IO4 ((uint32_t)0x00008000U)
+#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000U)
+
+#define TSC_GROUP5_IO1 ((uint32_t)0x00010000U)
+#define TSC_GROUP5_IO2 ((uint32_t)0x00020000U)
+#define TSC_GROUP5_IO3 ((uint32_t)0x00040000U)
+#define TSC_GROUP5_IO4 ((uint32_t)0x00080000U)
+#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000U)
+
+#define TSC_GROUP6_IO1 ((uint32_t)0x00100000U)
+#define TSC_GROUP6_IO2 ((uint32_t)0x00200000U)
+#define TSC_GROUP6_IO3 ((uint32_t)0x00400000U)
+#define TSC_GROUP6_IO4 ((uint32_t)0x00800000U)
+#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000U)
+
+#define TSC_GROUP7_IO1 ((uint32_t)0x01000000U)
+#define TSC_GROUP7_IO2 ((uint32_t)0x02000000U)
+#define TSC_GROUP7_IO3 ((uint32_t)0x04000000U)
+#define TSC_GROUP7_IO4 ((uint32_t)0x08000000U)
+#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000U)
+
+#define TSC_GROUP8_IO1 ((uint32_t)0x10000000U)
+#define TSC_GROUP8_IO2 ((uint32_t)0x20000000U)
+#define TSC_GROUP8_IO3 ((uint32_t)0x40000000U)
+#define TSC_GROUP8_IO4 ((uint32_t)0x80000000U)
+#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000U)
+
+#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFFU)
+
+/**
+  * @}
+  */ 
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+  * @{
+  */
+
+/** @brief Reset TSC handle state
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+  * @brief Enable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+  * @brief Disable the TSC peripheral.
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+  * @brief Start acquisition
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+  * @brief Stop acquisition
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+  * @brief Set IO default mode to output push-pull low
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+  * @brief Set IO default mode to input floating
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+  * @brief Set synchronization polarity to falling edge
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+  * @brief Set synchronization polarity to rising edge and high level
+  * @param  __HANDLE__: TSC handle
+  * @retval None
+  */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+  * @brief Enable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief Disable TSC interrupt.
+  * @param  __HANDLE__: TSC handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check if the specified TSC interrupt source is enabled or disabled.
+  * @param  __HANDLE__: TSC Handle
+  * @param  __INTERRUPT__: TSC interrupt
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief Get the selected TSC's flag status.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+  * @brief Clear the TSC's pending flag.
+  * @param  __HANDLE__: TSC handle
+  * @param  __FLAG__: TSC flag
+  * @retval None
+  */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief Enable schmitt trigger hysteresis on a group of IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable schmitt trigger hysteresis on a group of IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Open analog switch on a group of IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Close analog switch on a group of IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Enable a group of IOs in channel mode
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of channel IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable a group of IOs in sampling mode
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+  * @brief Disable a group of sampling IOs
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_IOY_MASK__: IOs mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+  * @brief Enable acquisition groups
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+  * @brief Disable acquisition groups
+  * @param  __HANDLE__: TSC handle
+  * @param  __GX_MASK__: Groups mask
+  * @retval None
+  */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status
+  * @param  __HANDLE__: TSC Handle
+  * @param  __GX_INDEX__: Group index
+  * @retval SET or RESET
+  */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+  * @{
+  */
+#define IS_TSC_ALL_INSTANCE(PERIPH) ((PERIPH) == TSC)
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+                          ((VAL) == TSC_CTPH_2CYCLES) || \
+                          ((VAL) == TSC_CTPH_3CYCLES) || \
+                          ((VAL) == TSC_CTPH_4CYCLES) || \
+                          ((VAL) == TSC_CTPH_5CYCLES) || \
+                          ((VAL) == TSC_CTPH_6CYCLES) || \
+                          ((VAL) == TSC_CTPH_7CYCLES) || \
+                          ((VAL) == TSC_CTPH_8CYCLES) || \
+                          ((VAL) == TSC_CTPH_9CYCLES) || \
+                          ((VAL) == TSC_CTPH_10CYCLES) || \
+                          ((VAL) == TSC_CTPH_11CYCLES) || \
+                          ((VAL) == TSC_CTPH_12CYCLES) || \
+                          ((VAL) == TSC_CTPH_13CYCLES) || \
+                          ((VAL) == TSC_CTPH_14CYCLES) || \
+                          ((VAL) == TSC_CTPH_15CYCLES) || \
+                          ((VAL) == TSC_CTPH_16CYCLES))
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+                          ((VAL) == TSC_CTPL_2CYCLES) || \
+                          ((VAL) == TSC_CTPL_3CYCLES) || \
+                          ((VAL) == TSC_CTPL_4CYCLES) || \
+                          ((VAL) == TSC_CTPL_5CYCLES) || \
+                          ((VAL) == TSC_CTPL_6CYCLES) || \
+                          ((VAL) == TSC_CTPL_7CYCLES) || \
+                          ((VAL) == TSC_CTPL_8CYCLES) || \
+                          ((VAL) == TSC_CTPL_9CYCLES) || \
+                          ((VAL) == TSC_CTPL_10CYCLES) || \
+                          ((VAL) == TSC_CTPL_11CYCLES) || \
+                          ((VAL) == TSC_CTPL_12CYCLES) || \
+                          ((VAL) == TSC_CTPL_13CYCLES) || \
+                          ((VAL) == TSC_CTPL_14CYCLES) || \
+                          ((VAL) == TSC_CTPL_15CYCLES) || \
+                          ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+                              ((VAL) == TSC_PG_PRESC_DIV2) || \
+                              ((VAL) == TSC_PG_PRESC_DIV4) || \
+                              ((VAL) == TSC_PG_PRESC_DIV8) || \
+                              ((VAL) == TSC_PG_PRESC_DIV16) || \
+                              ((VAL) == TSC_PG_PRESC_DIV32) || \
+                              ((VAL) == TSC_PG_PRESC_DIV64) || \
+                              ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+                         ((VAL) == TSC_MCV_511) || \
+                         ((VAL) == TSC_MCV_1023) || \
+                         ((VAL) == TSC_MCV_2047) || \
+                         ((VAL) == TSC_MCV_4095) || \
+                         ((VAL) == TSC_MCV_8191) || \
+                         ((VAL) == TSC_MCV_16383))
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+                            ((VAL) == TSC_IOMODE_CHANNEL) || \
+                            ((VAL) == TSC_IOMODE_SHIELD) || \
+                            ((VAL) == TSC_IOMODE_SAMPLING))
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+
+/** @defgroup TSC_Exported_Functions TSC Exported Functions
+  * @{
+  */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+
+/**
+  * @}
+  */
+/** @defgroup HAL_TSC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+
+/**
+  * @}
+  */
+/** @defgroup HAL_TSC_Exported_Functions_Group4 State callback and error Functions
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+
+/* Callback functions *********************************************************/
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup TSC_Private TSC Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L0xx_TSC_H */
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h
new file mode 100755
index 0000000..57ef3b2
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h
@@ -0,0 +1,710 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_USART_H
+#define __STM32L0xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+  * @{
+  */
+
+/**
+  * @brief USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits. */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode. */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_Clock_Polarity. */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_Clock_Phase. */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_Last_Bit. */
+}USART_InitTypeDef;
+
+/**
+  * @brief HAL USART State structures definition
+  */
+typedef enum
+{
+  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
+  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
+  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
+  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
+  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
+  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
+}HAL_USART_StateTypeDef;
+
+/**
+  * @brief  HAL USART Error Code structure definition
+  */
+#define   HAL_USART_ERROR_NONE      ((uint32_t)0x00U)    /*!< No error            */
+#define   HAL_USART_ERROR_PE        ((uint32_t)0x01U)    /*!< Parity error        */
+#define   HAL_USART_ERROR_NE        ((uint32_t)0x02U)    /*!< Noise error         */
+#define   HAL_USART_ERROR_FE        ((uint32_t)0x04U)    /*!< frame error         */
+#define   HAL_USART_ERROR_ORE       ((uint32_t)0x08U)    /*!< Overrun error       */
+#define   HAL_USART_ERROR_DMA       ((uint32_t)0x10U)    /*!< DMA transfer error  */
+
+/**
+  * @brief  USART clock sources definitions
+  */
+typedef enum
+{
+  USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source     */
+  USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source     */
+  USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source       */
+  USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source    */
+  USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
+  USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
+}USART_ClockSourceTypeDef;
+
+
+/**
+  * @brief  USART handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
+
+  USART_InitTypeDef             Init;             /*!< USART communication parameters      */
+
+  uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */
+
+  uint16_t                      Mask;             /*!< USART Rx RDR register mask          */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef               Lock;             /*!< Locking object                      */
+
+  __IO HAL_USART_StateTypeDef   State;            /*!< USART communication state           */
+
+  __IO uint32_t                 ErrorCode;        /*!< USART Error code                    */
+
+}USART_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_Stop_Bits  USART Number of Stop Bits
+  * @{
+  */
+#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                      /*!< USART frame with 0.5 stop bit  */
+#define USART_STOPBITS_1                     ((uint32_t)0x00000000)                /*!< USART frame with 1 stop bit    */   
+#define USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ 
+#define USART_STOPBITS_2                     USART_CR2_STOP_1                      /*!< USART frame with 2 stop bits   */ 
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity    USART Parity
+  * @{
+  */
+#define USART_PARITY_NONE                   ((uint32_t)0x00000000U)                     /*!< No parity   */
+#define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)                   /*!< Even parity */
+#define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))  /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode   USART Mode
+  * @{
+  */
+#define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)                   /*!< RX mode        */
+#define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)                   /*!< TX mode        */
+#define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock  USART Clock
+  * @{
+  */
+#define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000U)       /*!< USART clock disable */
+#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)   /*!< USART clock enable  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity  USART Clock Polarity
+  * @{
+  */
+#define USART_POLARITY_LOW                  ((uint32_t)0x00000000U)      /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)   /*!< USART Clock signal is steady High  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase   USART Clock Phase
+  * @{
+  */
+#define USART_PHASE_1EDGE                   ((uint32_t)0x00000000U)      /*!< USART frame phase on first clock transition  */
+#define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)   /*!< USART frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit  USART Last Bit
+  * @{
+  */
+#define USART_LASTBIT_DISABLE               ((uint32_t)0x00000000U)      /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)   /*!< USART frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Request_Parameters  USART Request Parameters
+  * @{
+  */
+#define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request  */
+#define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags      USART Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define USART_FLAG_REACK                     USART_ISR_REACK /*!< USART receive enable acknowledge flag  */
+#define USART_FLAG_TEACK                     USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY                      USART_ISR_BUSY  /*!< USART busy flag                        */
+#define USART_FLAG_CTS                       USART_ISR_CTS   /*!< USART clear to send flag               */
+#define USART_FLAG_CTSIF                     USART_ISR_CTSIF /*!< USART clear to send interrupt flag     */
+#define USART_FLAG_LBDF                      USART_ISR_LBDF  /*!< USART LIN break detection flag         */
+#define USART_FLAG_TXE                       USART_ISR_TXE   /*!< USART transmit data register empty     */
+#define USART_FLAG_TC                        USART_ISR_TC    /*!< USART transmission complete            */
+#define USART_FLAG_RXNE                      USART_ISR_RXNE  /*!< USART read data register not empty     */
+#define USART_FLAG_IDLE                      USART_ISR_IDLE  /*!< USART idle flag                        */
+#define USART_FLAG_ORE                       USART_ISR_ORE   /*!< USART overrun error                    */
+#define USART_FLAG_NE                        USART_ISR_NE    /*!< USART noise error                      */
+#define USART_FLAG_FE                        USART_ISR_FE    /*!< USART frame error                      */
+#define USART_FLAG_PE                        USART_ISR_PE    /*!< USART parity error                     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+
+#define USART_IT_PE                          ((uint16_t)0x0028U)     /*!< USART parity error interruption                 */   
+#define USART_IT_TXE                         ((uint16_t)0x0727U)     /*!< USART transmit data register empty interruption */   
+#define USART_IT_TC                          ((uint16_t)0x0626U)     /*!< USART transmission complete interruption        */   
+#define USART_IT_RXNE                        ((uint16_t)0x0525U)     /*!< USART read data register not empty interruption */   
+#define USART_IT_IDLE                        ((uint16_t)0x0424U)     /*!< USART idle interruption                         */   
+#define USART_IT_ERR                         ((uint16_t)0x0060U)     /*!< USART error interruption                        */
+#define USART_IT_ORE                         ((uint16_t)0x0300U)     /*!< USART overrun error interruption                */ 
+#define USART_IT_NE                          ((uint16_t)0x0200U)     /*!< USART noise error interruption                  */ 
+#define USART_IT_FE                          ((uint16_t)0x0100U)     /*!< USART frame error interruption                  */ 
+/**
+  * @}
+  */
+
+/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
+  * @{
+  */
+#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag        */
+#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
+  * @{
+  */
+#define USART_IT_MASK                             ((uint16_t)0x001FU)     /*!< USART interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @brief Reset USART handle state.
+  * @param  __HANDLE__: USART handle.
+  * @retval None
+  */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief  Flush the USART Data registers
+  * @param  __HANDLE__: specifies the USART Handle.
+  */
+#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+      SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
+      SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
+    } while(0)
+
+
+/** @brief  Check whether the specified USART flag is set or not.
+  * @param  __HANDLE__: specifies the USART Handle
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref USART_FLAG_BUSY  Busy flag
+  *            @arg @ref USART_FLAG_CTS   CTS Change flag
+  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref USART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref USART_FLAG_ORE   OverRun Error flag
+  *            @arg @ref USART_FLAG_NE    Noise Error flag
+  *            @arg @ref USART_FLAG_FE    Framing Error flag
+  *            @arg @ref USART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified USART pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref USART_CLEAR_PEF
+  *            @arg @ref USART_CLEAR_FEF
+  *            @arg @ref USART_CLEAR_NEF
+  *            @arg @ref USART_CLEAR_OREF
+  *            @arg @ref USART_CLEAR_IDLEF
+  *            @arg @ref USART_CLEAR_TCF
+  *            @arg @ref USART_CLEAR_CTSF
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the USART PE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief  Clear the USART FE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief  Clear the USART NE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief  Clear the USART ORE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief  Clear the USART IDLE pending flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief  Enable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief  Disable the specified USART interrupt.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC   Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_PE   Parity Error interrupt
+  *            @arg @ref USART_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief  Check whether the specified USART interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
+
+/** @brief  Check whether the specified USART interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT__: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TC  Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_IDLE Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE OverRun Error interrupt
+  *            @arg @ref USART_IT_NE Noise Error interrupt
+  *            @arg @ref USART_IT_FE Framing Error interrupt
+  *            @arg @ref USART_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1U << \
+                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+  *            @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+  *            @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific USART request flag.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __REQ__: specifies the request flag to set.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+
+/** @brief  Enable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.  
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the USART one bit sample method.
+  * @param  __HANDLE__: specifies the USART Handle.  
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable USART.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros   USART Private Macros
+  * @{
+  */
+
+/** @brief  Check USART Baud rate.
+  * @param  __BAUDRATE__: Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8).
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U)
+
+
+/**
+  * @brief Ensure that USART frame number of stop bits is valid.
+  * @param __STOPBITS__: USART frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+  * @brief Ensure that USART frame parity is valid.
+  * @param __PARITY__: USART frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+                                     ((__PARITY__) == USART_PARITY_EVEN) || \
+                                     ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+  * @brief Ensure that USART communication mode is valid.
+  * @param __MODE__: USART communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_USART_MODE(MODE)     (((MODE) == USART_MODE_RX) || \
+                                 ((MODE) == USART_MODE_TX) || \
+                                 ((MODE) == USART_MODE_TX_RX))
+
+/**
+  * @brief Ensure that USART clock state is valid.
+  * @param __CLOCK__: USART clock state. 
+  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+  */ 
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+                                   ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+  * @brief Ensure that USART frame polarity is valid.
+  * @param __CPOL__: USART frame polarity. 
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */ 
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that USART frame phase is valid.
+  * @param __CPHA__: USART frame phase. 
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that USART frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: USART frame last bit clock pulse setting. 
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that USART request parameter is valid.
+  * @param __PARAM__: USART request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include USART HAL Extended module */
+#include "stm32l0xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h
new file mode 100755
index 0000000..d5a2d42
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h
@@ -0,0 +1,297 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_usart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_USART_EX_H
+#define __STM32L0xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+  * @{
+  */
+  
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+  * @{
+  */
+#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */ 
+#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)    /*!< 8-bit long USART frame */ 
+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the USART clock source.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the USART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx)
+
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+
+#elif defined(STM32L071xx) || defined (STM32L081xx) || defined(STM32L072xx) || defined (STM32L082xx) || defined(STM32L073xx) || defined (STM32L083xx)
+
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART4)                  \
+    {                                                          \
+      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART5)                  \
+    {                                                          \
+      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;             \
+    }                                                          \
+  } while(0)
+
+#else
+
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART2)                       \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+       {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+       }                                                       \
+    }                                                          \
+  } while(0)
+
+#endif
+
+/** @brief  Compute the USART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__: specifies the USART Handle.
+  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define USART_MASK_COMPUTATION(__HANDLE__)                            \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+
+/**
+  * @brief Ensure that USART frame length is valid.
+  * @param __LENGTH__: USART frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_9B))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h
new file mode 100755
index 0000000..8981926
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_wwdg.h
@@ -0,0 +1,283 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_wwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of WWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_WWDG_H
+#define __STM32L0xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  WWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
+
+}WWDG_InitTypeDef;
+
+/**
+  * @brief  WWDG handle Structure definition
+  */
+typedef struct
+{
+  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+  * @{
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+  * @brief WWDG Flag definition
+  * @{
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+  * @{
+  */
+#define WWDG_PRESCALER_1                    0x00000000U       /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000U       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the WWDG peripheral.
+  * @param  __HANDLE__  WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+  * @brief  Enable the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
+  *        This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief  Clear the WWDG interrupt pending bits.
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the WWDG's pending flags.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval None
+  */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
+  * @param  __HANDLE__  WWDG Handle.
+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
+  * @retval state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h
new file mode 100755
index 0000000..05fc80c
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h
@@ -0,0 +1,4049 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_ADC_H
+#define __STM32L0xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 1U)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 2U)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 3U))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
+
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel identifier defined by bitfield                                   */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR1_AWDCH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR1_AWDCH_1                    )
+#define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR1_AWDCH_2                                        )
+#define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR1_AWDCH_2                     | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1                    )
+#define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR1_AWDCH_3                                                            )
+#define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR1_AWDCH_3                                         | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR1_AWDCH_3                     | ADC_CFGR1_AWDCH_1                    )
+#define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR1_AWDCH_3                     | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2                                        )
+#define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2                     | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1                    )
+#define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR1_AWDCH_4                                                                                )
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR1_AWDCH_4                                                             | ADC_CFGR1_AWDCH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR1_AWDCH_4                                         | ADC_CFGR1_AWDCH_1                    )
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_CHSELR_CHSEL0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_CHSELR_CHSEL1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_CHSELR_CHSEL2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_CHSELR_CHSEL3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_CHSELR_CHSEL4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_CHSELR_CHSEL5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_CHSELR_CHSEL6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_CHSELR_CHSEL7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_CHSELR_CHSEL8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_CHSELR_CHSEL9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_CHSELR_CHSEL10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_CHSELR_CHSEL11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_CHSELR_CHSEL12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_CHSELR_CHSEL13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_CHSELR_CHSEL14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_CHSELR_CHSEL15)
+#if  defined(ADC_CCR_VLCDEN)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_CHSELR_CHSEL16)
+#endif
+#define ADC_CHANNEL_17_BITFIELD            (ADC_CHSELR_CHSEL17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_CHSELR_CHSEL18)
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 families)).       */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC group regular).                              */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR1_RES_BITOFFSET_POS        ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
+#define ADC_CFGR1_AWDSGL_BITOFFSET_POS     ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
+#define ADC_TR_HT_BITOFFSET_POS            ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+#define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
+#define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
+#define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
+#define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
+#define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
+#define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
+#define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
+#define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
+#define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
+#define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
+#define ADC_CHSELR_CHSEL10_BITOFFSET_POS   ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
+#define ADC_CHSELR_CHSEL11_BITOFFSET_POS   ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
+#define ADC_CHSELR_CHSEL12_BITOFFSET_POS   ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
+#define ADC_CHSELR_CHSEL13_BITOFFSET_POS   ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
+#define ADC_CHSELR_CHSEL14_BITOFFSET_POS   ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
+#define ADC_CHSELR_CHSEL15_BITOFFSET_POS   ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
+#if  defined(ADC_CCR_VLCDEN)
+#define ADC_CHSELR_CHSEL16_BITOFFSET_POS   ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
+#endif
+#define ADC_CHSELR_CHSEL17_BITOFFSET_POS   ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
+#define ADC_CHSELR_CHSEL18_BITOFFSET_POS   ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FF80078U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+/* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
+#if !defined(STM32L011xx)
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FF8007AU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L0, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#endif
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FF8007EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#if !defined(STM32L011xx)
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#endif
+#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  130)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+  * @}
+  */
+
+
+#if  defined(USE_FULL_LL_DRIVER)
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Clock;                       /*!< Set ADC instance clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
+                                             @note On this STM32 serie, this parameter has some clock ratio constraints:
+                                                   ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
+                                                   (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
+                                             
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
+                                             For more details, refer to description of this function. */
+
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is enabled
+                                                   (several ADC channels enabled in group regular sequencer).
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD        /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_ASYNC_DIV1            ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchonous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE  ADC common - Clock frequency mode
+  * @{
+  */
+#define LL_ADC_CLOCK_FREQ_MODE_HIGH        ((uint32_t)0x00000000U)/*!< ADC clock mode to high frequency. On STM32L0, ADC clock frequency above 2.8MHz.  */
+#define LL_ADC_CLOCK_FREQ_MODE_LOW         (ADC_CCR_LFMEN)        /*!< ADC clock mode to low frequency. On STM32L0, ADC clock frequency below 2.8MHz.  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VLCD          (ADC_CCR_VLCDEN)       /*!< ADC measurement path to internal channel Vlcd */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CLOCK_SOURCE  ADC instance - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1)                                  /*!< ADC synchronous clock derived from AHB clock divided by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0)                                  /*!< ADC synchronous clock derived from AHB clock divided by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0)             /*!< ADC synchronous clock derived from AHB clock not divided  */
+#define LL_ADC_CLOCK_ASYNC                 ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                  ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                  ) /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR1_ALIGN)      /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_MODE_NONE                ((uint32_t)0x00000000U)             /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)                    /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF)                  /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */
+#if defined(ADC_CCR_VLCDEN)
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_VLCD                (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vlcd: Vlcd voltage through a divider ladder of factor 1/4, 1/3 or 1/2 (set by LCD voltage generator biasing),  to have Vlcd always below Vdda. */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                                        /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM21_CH2      (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external IP: TIM21 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH4       (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM22_TRGO     (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external IP: TIM22 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (                    ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR1_EXTEN_1                    ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)        /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+* @{
+*/
+#define LL_ADC_REG_OVR_DATA_PRESERVED      ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD)     /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    ((uint32_t)0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR)    /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                                                               /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5       ((uint32_t)0x00000000U)                               /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_3CYCLES_5      (ADC_SMPR_SMP_0)                                      /*!< Sampling time 3.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP_1)                                      /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)                     /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR_SMP_2)                                      /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_39CYCLES_5     (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)                     /*!< Sampling time 39.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_79CYCLES_5     (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)                     /*!< Sampling time 79.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_160CYCLES_5    (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)    /*!< Sampling time 160.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                    /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                    ADC_CFGR1_AWDEN                   )   /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#if defined(ADC_CCR_VLCDEN)
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)         | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CH_VLCD_REG             ((LL_ADC_CHANNEL_VLCD       & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)   /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR_HT            )     /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (            ADC_TR_LT)     /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR_HT | ADC_TR_LT)     /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 ((uint32_t)0x00000000U)                               /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_OVSE)  /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                ((uint32_t)0x00000000U)/*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define LL_ADC_OVS_RATIO_2                 ((uint32_t)0x00000000U)                                  /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              ((uint32_t)0x00000000U)                                                     /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+  
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 serie:                                                         */
+/*       - ADC calibration time: maximum delay is 83/fADC.                    */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tUP_LDO").                                                      */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t)  10U)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "TADC_BUF").                                                     */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US       ((uint32_t)  10U)  /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t)  10U)  /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U)  /*!< Delay required between ADC end of calibration and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#if defined(ADC_CCR_VLCDEN)
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                               \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                                         \
+    ? (                                                                                                           \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS                        \
+      )                                                                                                           \
+      :                                                                                                           \
+      (                                                                                                           \
+       (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) :                                        \
+        (                                                                                                         \
+         (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) :                                      \
+          (                                                                                                       \
+           (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) :                                    \
+            (                                                                                                     \
+             (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) :                                  \
+              (                                                                                                   \
+               (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) :                                \
+                (                                                                                                 \
+                 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) :                              \
+                  (                                                                                               \
+                   (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) :                            \
+                    (                                                                                             \
+                     (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) :                          \
+                      (                                                                                           \
+                       (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) :                        \
+                        (                                                                                         \
+                         (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) :                      \
+                          (                                                                                       \
+                           (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) :                 \
+                            (                                                                                     \
+                             (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) :               \
+                              (                                                                                   \
+                               (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) :             \
+                                (                                                                                 \
+                                 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) :           \
+                                  (                                                                               \
+                                   (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) :         \
+                                    (                                                                             \
+                                     (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) :       \
+                                      (                                                                           \
+                                       (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) :     \
+                                        (                                                                         \
+                                         (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) :   \
+                                          (                                                                       \
+                                           (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
+                                            (0U)                                                                   \
+                                          )                                                                       \
+                                        )                                                                         \
+                                      )                                                                           \
+                                    )                                                                             \
+                                  )                                                                               \
+                                )                                                                                 \
+                              )                                                                                   \
+                            )                                                                                     \
+                          )                                                                                       \
+                        )                                                                                         \
+                      )                                                                                           \
+                    )                                                                                             \
+                  )                                                                                               \
+                )                                                                                                 \
+              )                                                                                                   \
+            )                                                                                                     \
+          )                                                                                                       \
+        )                                                                                                         \
+      )                                                                                                           \
+  )
+#else
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                               \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                                         \
+    ? (                                                                                                           \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS                        \
+      )                                                                                                           \
+      :                                                                                                           \
+      (                                                                                                           \
+       (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) :                                        \
+        (                                                                                                         \
+         (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) :                                      \
+          (                                                                                                       \
+           (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) :                                    \
+            (                                                                                                     \
+             (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) :                                  \
+              (                                                                                                   \
+               (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) :                                \
+                (                                                                                                 \
+                 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) :                              \
+                  (                                                                                               \
+                   (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) :                            \
+                    (                                                                                             \
+                     (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) :                          \
+                      (                                                                                           \
+                       (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) :                        \
+                        (                                                                                         \
+                         (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) :                      \
+                          (                                                                                       \
+                           (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) :                 \
+                            (                                                                                     \
+                             (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) :               \
+                              (                                                                                   \
+                               (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) :             \
+                                (                                                                                 \
+                                 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) :           \
+                                  (                                                                               \
+                                   (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) :         \
+                                    (                                                                             \
+                                     (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) :       \
+                                      (                                                                           \
+                                       (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) :     \
+                                        (                                                                         \
+                                         (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) :   \
+                                          (0U)                                                                     \
+                                        )                                                                         \
+                                      )                                                                           \
+                                    )                                                                             \
+                                  )                                                                               \
+                                )                                                                                 \
+                              )                                                                                   \
+                            )                                                                                     \
+                          )                                                                                       \
+                        )                                                                                         \
+                      )                                                                                           \
+                    )                                                                                             \
+                  )                                                                                               \
+                )                                                                                                 \
+              )                                                                                                   \
+            )                                                                                                     \
+          )                                                                                                       \
+        )                                                                                                         \
+      )                                                                                                           \
+  )
+#endif
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT       (2)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR    (2)
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)(2)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (                                                                            \
+   ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \
+   (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))                                     \
+  )
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#if defined(ADC_CCR_VLCDEN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (                                                                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_VLCD)                                     \
+  )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (                                                                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
+    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                               \
+  )
+#endif
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT       (2)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR    (2)
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)(2)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
+  *         @arg @ref LL_ADC_AWD_CH_VLCD_REG             (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+  *         or @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is 
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC analog watchdog threshold high
+  *         or low from raw value containing both thresholds concatenated.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, to get analog watchdog threshold high from the register raw value:
+  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
+  (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW)                                 \
+    ? (                                                                                   \
+       (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW                                    \
+      )                                                                                   \
+      :                                                                                   \
+      (                                                                                   \
+       ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW       \
+      )                                                                                   \
+  )
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC1_COMMON)
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  LL_ADC_IsEnabled(ADC1)
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted 
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
+  (((__DATA__)                                                                 \
+    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))   \
+   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))      \
+  )
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                      \
+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+  )
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 serie, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                   \
+  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \
+                                       (__ADC_RESOLUTION__),                   \
+                                       LL_ADC_RESOLUTION_12B)                  \
+  )
+
+/* Note: On device STM32L011, calibration parameter TS_CAL1 is not available. */
+/*       Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
+/*       Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().        */
+#if !defined(STM32L011xx)
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 serie, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                  __TEMPSENSOR_ADC_DATA__,\
+                                  __ADC_RESOLUTION__)                              \
+  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+                                                    (__ADC_RESOLUTION__),          \
+                                                    LL_ADC_RESOLUTION_12B)         \
+                   * (__VREFANALOG_VOLTAGE__))                                     \
+                  / TEMPSENSOR_CAL_VREFANALOG)                                     \
+        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+   ) + TEMPSENSOR_CAL1_TEMP                                                        \
+  )
+#endif
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+  *                                       On STM32L0, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On STM32L0, refer to device datasheet parameter "V130" (corresponding to TS_CAL2).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)               \
+  ((( (                                                                        \
+       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+                 * 1000)                                                       \
+       -                                                                       \
+       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+                 * 1000)                                                       \
+      )                                                                        \
+    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
+   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  * @retval ADC register address
+  */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Retrieve address of register DR */
+  return (uint32_t)&(ADCx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      PRESC          LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
+  *
+  *         (1) ADC common clock asynchonous prescaler is applied to 
+  *             each ADC instance if the corresponding ADC instance clock  
+  *             is set to clock source asynchronous.
+  *             (refer to function @ref LL_ADC_SetClock() ).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      PRESC          LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
+  *
+  *         (1) ADC common clock asynchonous prescaler is applied to 
+  *             each ADC instance if the corresponding ADC instance clock  
+  *             is set to clock source asynchronous.
+  *             (refer to function @ref LL_ADC_SetClock() ).
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: Clock low frequency mode.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CCR      LFMEN          LL_ADC_SetCommonFrequencyMode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
+  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Resolution)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, Resolution);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock low frequency mode.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CCR      LFMEN          LL_ADC_GetCommonFrequencyMode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH
+  *         @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VLCDEN         LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VLCD (*)
+  *
+  *         (*) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+#if defined (ADC_CCR_VLCDEN)
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal);
+#else
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+#endif
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VLCDEN         LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VLCD (*)
+  *
+  *         (*) value not defined in all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+#if defined(ADC_CCR_VLCDEN)
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN));
+#else
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
+#endif
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC instance clock source and prescaler.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    CKMODE         LL_ADC_SetClock
+  * @param  ADCx ADC instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
+  *         
+  *         (1) Asynchronous clock prescaler can be configured using
+  *             function @ref LL_ADC_SetCommonClock().\n
+  *         (2) Caution: This parameter has some clock ratio constraints:
+  *             This configuration must be enabled only if PCLK has a 50%
+  *             duty clock cycle (APB prescaler configured inside the RCC
+  *             must be bypassed and the system clock must by 50% duty
+  *             cycle).
+  *             Refer to reference manual.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
+}
+
+/**
+  * @brief  Get ADC instance clock source and prescaler.
+  * @rmtoll CFGR2    CKMODE         LL_ADC_GetClock
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
+  *         
+  *         (1) Asynchronous clock prescaler can be retrieved using
+  *             function @ref LL_ADC_GetCommonClock().\n
+  *         (2) Caution: This parameter has some clock ratio constraints:
+  *             This configuration must be enabled only if PCLK has a 50%
+  *             duty clock cycle (APB prescaler configured inside the RCC
+  *             must be bypassed and the system clock must by 50% duty
+  *             cycle).
+  *             Refer to reference manual.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
+}
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular.
+  * @rmtoll CALFACT  CALFACT        LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             ADC_CALFACT_CALFACT,
+             CalibrationFactor);
+}
+
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @rmtoll CALFACT  CALFACT        LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
+}
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR1    RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR1    ALIGN          LL_ADC_GetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - Do not use with interruption or DMA since these modes
+  *             have to clear immediately the EOC flag to free the
+  *             IRQ vector sequencer.
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    WAIT           LL_ADC_SetLowPowerMode\n
+  *         CFGR1    AUTOFF         LL_ADC_SetLowPowerMode
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - Do not use with interruption or DMA since these modes
+  *             have to clear immediately the EOC flag to free the
+  *             IRQ vector sequencer.
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR1    WAIT           LL_ADC_GetLowPowerMode\n
+  *         CFGR1    AUTOFF         LL_ADC_GetLowPowerMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
+}
+
+/**
+  * @brief  Set sampling time common to a group of channels.
+  * @note   Unit: ADC clock cycles.
+  * @note   On this STM32 serie, sampling time scope is on ADC instance:
+  *         Sampling time common to all channels.
+  *         (on some other STM32 families, sampling time is channel wise)
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 serie, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SMPR     SMP            LL_ADC_SetSamplingTimeCommonChannels
+  * @param  ADCx ADC instance
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
+{
+  MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
+}
+
+/**
+  * @brief  Get sampling time common to a group of channels.
+  * @note   Unit: ADC clock cycles.
+  * @note   On this STM32 serie, sampling time scope is on ADC instance:
+  *         Sampling time common to all channels.
+  *         (on some other STM32 families, sampling time is channel wise)
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 serie.
+  * @rmtoll SMPR     SMP            LL_ADC_GetSamplingTimeCommonChannels
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 serie, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge 
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external IP (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to 
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer 
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM21_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM22_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (*)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+  register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+  
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                           */
+  register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+  
+  /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+            or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
+}
+
+
+/**
+  * @brief  Set ADC group regular sequencer scan direction.
+  * @note   On some other STM32 families, this setting is not available and
+  *         the default scan direction is forward.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_SetSequencerScanDirection
+  * @param  ADCx ADC instance
+  * @param  ScanDirection This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer scan direction.
+  * @note   On some other STM32 families, this setting is not available and
+  *         the default scan direction is forward.
+  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_GetSequencerScanDirection
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by overwriting the current sequencer
+  *           configuration.
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         not fully configurable: sequencer length and each rank
+  *         affectation to a channel are fixed by channel HW number.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChannels
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Add channel to ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by adding them to the current sequencer
+  *           configuration.
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         not fully configurable: sequencer length and each rank
+  *         affectation to a channel are fixed by channel HW number.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChAdd
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Remove channel to ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by removing them to the current sequencer
+  *           configuration.
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         not fully configurable: sequencer length and each rank
+  *         affectation to a channel are fixed by channel HW number.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChRem
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels order reading into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  * @note   On this STM32 serie, ADC group regular sequencer is
+  *         not fully configurable: sequencer length and each rank
+  *         affectation to a channel are fixed by channel HW number.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 serie, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be retrieved.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_GetSequencerChannels
+  * @param  ADCx ADC instance
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16         (1)
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref LL_ADC_CHANNEL_VLCD       (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
+{
+  register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
+  
+  return (   (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
+#if defined(ADC_CCR_VLCDEN)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
+#endif
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
+           | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
+         );
+}
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular 
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_SetDMATransfer\n
+  *         CFGR1    DMACFG         LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_GetDMATransfer\n
+  *         CFGR1    DMACFG         LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
+}
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel or all channels,
+  *         on ADC group regular.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    AWDCH          LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWDSGL         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWDEN          LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
+  *         @arg @ref LL_ADC_AWD_CH_VLCD_REG             (1)
+  *         
+  *         (1) On STM32L0, parameter not available on all devices: only on STM32L053xx, STM32L063xx, STM32L073xx, STM32L083xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+  MODIFY_REG(ADCx->CFGR1,
+             (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN),
+             (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    AWDCH          LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWDSGL         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWDEN          LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG 
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+  register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN));
+  
+  /* Note: Set variable according to channel definition including channel ID  */
+  /*       with bitfield.                                                     */
+  register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
+  register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
+  
+  return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle));
+}
+
+/**
+  * @brief  Set ADC analog watchdog thresholds value of both thresholds
+  *         high and low.
+  * @note   If value of only one threshold high or low must be set,
+  *         use function @ref LL_ADC_SetAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll TR       HT             LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR       LT             LL_ADC_ConfigAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
+{
+  MODIFY_REG(ADCx->TR,
+             ADC_TR_HT | ADC_TR_LT,
+             (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   If values of both thresholds high or low must be set,
+  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 serie, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll TR       HT             LL_ADC_SetAnalogWDThresholds\n
+  *         TR       LT             LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+  /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010"          */
+  /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold   */
+  /* high is selected, then data is shifted to LSB. Else(threshold low),      */
+  /* data is not shifted.                                                     */
+  MODIFY_REG(ADCx->TR,
+             AWDThresholdsHighLow,
+             AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   If raw data with ADC thresholds high and low is retrieved,
+  *         the data of each threshold high or low can be isolated
+  *         using helper macro:
+  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll TR       HT             LL_ADC_GetAnalogWDThresholds\n
+  *         TR       LT             LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+  /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010"          */
+  /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold   */
+  /* high is selected, then data is shifted to LSB. Else(threshold low or     */
+  /* both thresholds), data is not shifted.                                   */
+  return (uint32_t)(READ_BIT(ADCx->TR,
+                             (AWDThresholdsHighLow | ADC_TR_LT))
+                    >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U))
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    OVSE           LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope.
+  * @rmtoll CFGR2    OVSE           LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    TOVS           LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TOVS           LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC instance internal voltage regulator.
+  * @note   On this STM32 serie, there are three possibilities to enable
+  *         the voltage regulator:
+  *         - by enabling it manually
+  *           using function @ref LL_ADC_EnableInternalRegulator().
+  *         - by launching a calibration
+  *           using function @ref LL_ADC_StartCalibration().
+  *         - by enabling the ADC
+  *           using function @ref LL_ADC_Enable().
+  * @note   On this STM32 serie, after ADC internal voltage regulator enable,
+  *         a delay for ADC internal voltage regulator stabilization
+  *         is required before performing a ADC calibration or ADC enable.
+  *         Refer to device datasheet, parameter "tUP_LDO".
+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+
+/**
+  * @brief  Disable ADC internal voltage regulator.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance internal voltage regulator state.
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
+}
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 serie, after ADC enable, a delay for 
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 serie, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   In case of usage of ADC with DMA transfer:
+  *         On this STM32 serie, ADC DMA transfer request should be disabled
+  *         during calibration:
+  *         Calibration factor is available in data register
+  *         and also transfered by DMA.
+  *         To not insert ADC calibration factor among ADC conversion data
+  *         in array variable, DMA transfer must be disabled during
+  *         calibration.
+  *         (DMA transfer setting backup and disable before calibration,
+  *         DMA transfer setting restore after calibration.
+  *         Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
+  *         @ref LL_ADC_REG_SetDMATransfer() ).
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL);
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 serie, this function is relevant for both 
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 serie, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOSEQ          LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD            LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+  * @brief  Get flag ADC end of calibration.
+  * @rmtoll ISR      EOCAL          LL_ADC_IsActiveFlag_EOCAL
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL));
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOSEQ          LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD            LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC end of calibration.
+  * @rmtoll ISR      EOCAL          LL_ADC_ClearFlag_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSEQIE        LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWDIE          LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC end of calibration.
+  * @rmtoll IER      EOCALIE        LL_ADC_EnableIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSEQIE        LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWDIE          LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC end of calibration.
+  * @rmtoll IER      EOCALIE        LL_ADC_DisableIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSEQIE        LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWDIE          LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+  * @brief  Get state of interruption ADC end of calibration
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCALIE        LL_ADC_IsEnabledIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
+{
+  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
new file mode 100755
index 0000000..dada43c
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
@@ -0,0 +1,1187 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim                
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]  
+      A delay between an RCC peripheral clock enable and the effective peripheral 
+      enabling should be taken into account in order to manage the peripheral read/write 
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]  
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_BUS_H
+#define __STM32L0xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN      /*!< DMA1 clock enable */
+#define LL_AHB1_GRP1_PERIPH_MIF            RCC_AHBENR_MIFEN       /*!< MIF clock enable */
+#define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBSMENR_SRAMSMEN  /*!< Sleep Mode SRAM clock enable */
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN       /*!< CRC clock enable */
+#if defined(TSC)
+#define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHBENR_TSCEN       /*!< TSC clock enable */
+#endif /*TSC*/
+#if defined(RNG)
+#define LL_AHB1_GRP1_PERIPH_RNG            RCC_AHBENR_RNGEN       /*!< RNG clock enable */
+#endif /*RNG*/
+#if defined(AES)
+#define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_CRYPEN      /*!< CRYP clock enable */
+#endif /*AES*/
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN     /*!< TIM2 clock enable */
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN     /*!< TIM3 clock enable */
+#endif
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN     /*!< TIM6 clock enable */
+#endif
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN     /*!< TIM7 clock enable */
+#endif
+#if defined(LCD)
+#define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR_LCDEN      /*!< LCD clock enable */
+#endif /*LCD*/
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN     /*!< WWDG clock enable */
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN     /*!< SPI2 clock enable */
+#endif
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN   /*!< USART2 clock enable */
+#define LL_APB1_GRP1_PERIPH_LPUART1        RCC_APB1ENR_LPUART1EN  /*!< LPUART1 clock enable */
+#if defined(USART4)
+#define LL_APB1_GRP1_PERIPH_USART4         RCC_APB1ENR_USART4EN   /*!< USART4 clock enable */
+#endif
+#if defined(USART5)
+#define LL_APB1_GRP1_PERIPH_USART5         RCC_APB1ENR_USART5EN   /*!< USART5 clock enable */
+#endif
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN     /*!< I2C1 clock enable */
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN     /*!< I2C2 clock enable */
+#endif
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN      /*!< USB clock enable */
+#endif /*USB*/
+#if defined(CRS)
+#define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR_CRSEN      /*!< CRS clock enable */
+#endif /*CRS*/
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN      /*!< PWR clock enable */
+#if defined(DAC)
+#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN      /*!< DAC clock enable */
+#endif
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN     /*!< I2C3 clock enable */
+#endif
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN   /*!< LPTIM1 clock enable */
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN  /*!< SYSCFG clock enable */
+#define LL_APB2_GRP1_PERIPH_TIM21          RCC_APB2ENR_TIM21EN   /*!< TIM21 clock enable */
+#if defined(TIM22)
+#define LL_APB2_GRP1_PERIPH_TIM22          RCC_APB2ENR_TIM22EN   /*!< TIM22 clock enable */
+#endif
+#define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN      /*!< FireWall clock enable */
+#define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN    /*!< ADC1 clock enable */
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN    /*!< SPI1 clock enable */
+#if defined(USART1)
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN  /*!< USART1 clock enable */
+#endif
+#define LL_APB2_GRP1_PERIPH_DBGMCU         RCC_APB2ENR_DBGMCUEN  /*!< DBGMCU clock enable */
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH  IOP GRP1 PERIPH
+  * @{
+  */
+#define LL_IOP_GRP1_PERIPH_ALL             (uint32_t)0xFFFFFFFFU
+#define LL_IOP_GRP1_PERIPH_GPIOA           RCC_IOPENR_GPIOAEN    /*!< GPIO port A control */
+#define LL_IOP_GRP1_PERIPH_GPIOB           RCC_IOPENR_GPIOBEN    /*!< GPIO port B control */
+#define LL_IOP_GRP1_PERIPH_GPIOC           RCC_IOPENR_GPIOCEN    /*!< GPIO port C control */
+#if defined(GPIOD)
+#define LL_IOP_GRP1_PERIPH_GPIOD           RCC_IOPENR_GPIODEN    /*!< GPIO port D control */
+#endif /*GPIOD*/
+#if defined(GPIOE)
+#define LL_IOP_GRP1_PERIPH_GPIOE           RCC_IOPENR_GPIOEEN    /*!< GPIO port H control */
+#endif /*GPIOE*/
+#if defined(GPIOH)
+#define LL_IOP_GRP1_PERIPH_GPIOH           RCC_IOPENR_GPIOHEN    /*!< GPIO port H control */
+#endif /*GPIOH*/
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHBENR      MIFEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHBENR      CRCEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHBENR      TSCEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHBENR      RNGEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHBENR      CRYPEN       LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHBENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHBENR      MIFEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHBENR      CRCEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHBENR      TSCEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHBENR      RNGEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHBENR      CRYPEN       LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHBENR      MIFEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHBENR      CRCEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHBENR      TSCEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHBENR      RNGEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHBENR      CRYPEN       LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHBENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ForceReset\n
+  *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHBSMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHBSMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LCDEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART4EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART5EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USBEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CRSEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LCDEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART4EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART5EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USBEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CRSEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LCDEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LPUART1EN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART4EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART5EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USBEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CRSEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LCDRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART4RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART5RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USBRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CRSRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LCDRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART4RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART5RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USBRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CRSRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    USBSMEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    DACSMEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    USBSMEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    DACSMEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM21EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM22EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      ADCEN         LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      DBGEN         LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM21EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM22EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      ADCEN         LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DBGEN         LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM21EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM22EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      FWEN          LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      ADCEN         LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      DBGEN         LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_FW
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     ADCRST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DBGRST        LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     ADCRST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DBGRST        LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2SMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2SMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+/** @defgroup BUS_LL_EF_IOP IOP
+  * @{
+  */
+
+/**
+  * @brief  Enable IOP peripherals clock.
+  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_EnableClock\n
+  *         IOPENR       GPIOBEN       LL_IOP_GRP1_EnableClock\n
+  *         IOPENR       GPIOCEN       LL_IOP_GRP1_EnableClock\n
+  *         IOPENR       GPIODEN       LL_IOP_GRP1_EnableClock\n
+  *         IOPENR       GPIOEEN       LL_IOP_GRP1_EnableClock\n
+  *         IOPENR       GPIOHEN       LL_IOP_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->IOPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->IOPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if IOP peripheral clock is enabled or not
+  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_IsEnabledClock\n
+  *         IOPENR       GPIOBEN       LL_IOP_GRP1_IsEnabledClock\n
+  *         IOPENR       GPIOCEN       LL_IOP_GRP1_IsEnabledClock\n
+  *         IOPENR       GPIODEN       LL_IOP_GRP1_IsEnabledClock\n
+  *         IOPENR       GPIOEEN       LL_IOP_GRP1_IsEnabledClock\n
+  *         IOPENR       GPIOHEN       LL_IOP_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->IOPENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable IOP peripherals clock.
+  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_DisableClock\n
+  *         IOPENR       GPIOBEN       LL_IOP_GRP1_DisableClock\n
+  *         IOPENR       GPIOCEN       LL_IOP_GRP1_DisableClock\n
+  *         IOPENR       GPIODEN       LL_IOP_GRP1_DisableClock\n
+  *         IOPENR       GPIOEEN       LL_IOP_GRP1_DisableClock\n
+  *         IOPENR       GPIOHEN       LL_IOP_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->IOPENR, Periphs);
+}
+
+/**
+  * @brief  Disable IOP peripherals clock.
+  * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ForceReset\n
+  *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ForceReset\n
+  *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ForceReset\n
+  *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ForceReset\n
+  *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ForceReset\n
+  *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->IOPRSTR, Periphs);
+}
+
+/**
+  * @brief  Release IOP peripherals reset.
+  * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ReleaseReset\n
+  *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ReleaseReset\n
+  *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ReleaseReset\n
+  *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ReleaseReset\n
+  *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ReleaseReset\n
+  *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->IOPRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable IOP peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_EnableClockSleep\n
+  *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_EnableClockSleep\n
+  *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_EnableClockSleep\n
+  *         IOPSMENR     GPIODRST      LL_IOP_GRP1_EnableClockSleep\n
+  *         IOPSMENR     GPIOERST      LL_IOP_GRP1_EnableClockSleep\n
+  *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->IOPSMENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable IOP peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_DisableClockSleep\n
+  *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_DisableClockSleep\n
+  *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_DisableClockSleep\n
+  *         IOPSMENR     GPIODRST      LL_IOP_GRP1_DisableClockSleep\n
+  *         IOPSMENR     GPIOERST      LL_IOP_GRP1_DisableClockSleep\n
+  *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->IOPSMENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h
new file mode 100755
index 0000000..89fbd87
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_comp.h
@@ -0,0 +1,721 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_comp.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_COMP_H
+#define __STM32L0xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+  * @{
+  */
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1VALUE) */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of COMP instance.
+  */
+typedef struct
+{
+  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.
+                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+  uint32_t OutputPolarity;              /*!< Set comparator output polarity.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+  * @{
+  */
+#define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_COMP1WM)      /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+  * @{
+  */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER   ((uint32_t)0x00000000U)     /*!< COMP power mode to low speed (specific to COMP instance: COMP2) */
+#define LL_COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_COMP2SPEED)       /*!< COMP power mode to fast speed (specific to COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_PLUS_IO1          ((uint32_t)0x00000000U)                            /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_COMP2INPSEL_0)                           /*!< Comparator input plus connected to IO2 (pin PB4 for COMP2) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_PLUS_IO3          (COMP_CSR_COMP2INPSEL_1)                           /*!< Comparator input plus connected to IO3 (pin PA5 for COMP2) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_PLUS_IO4          (COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_1)  /*!< Comparator input plus connected to IO4 (pin PB6 for COMP2) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_PLUS_IO5          (COMP_CSR_COMP2INPSEL_2)                           /*!< Comparator input plus connected to IO5 (pin PB7 for COMP2) (specific to COMP instance: COMP2) */
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define LL_COMP_INPUT_PLUS_IO6          (COMP_CSR_COMP2INPSEL_2 | COMP_CSR_COMP2INPSEL_0)  /*!< Comparator input plus connected to IO6 (pin PA7 for COMP2) (specific to COMP instance: COMP2) (Available only on devices STM32L0 category 1) */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT  (COMP_CSR_COMP2INNSEL_2                                                  ) /*!< Comparator input minus connected to 1/4 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT  (COMP_CSR_COMP2INNSEL_2 |                          COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT  (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to 3/4 VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) (specific to COMP instance: COMP2) */
+#define LL_COMP_INPUT_MINUS_VREFINT     ((uint32_t)0x00000000U)                                                    /*!< Comparator input minus connected to VrefInt (specifity of COMP2 related to path to enable via SYSCFG: refer to comment in function @ref LL_COMP_SetInputMinus() ) */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1    (                         COMP_CSR_COMP2INNSEL_1                         ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */
+#define LL_COMP_INPUT_MINUS_DAC1_CH2    (                         COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */
+#define LL_COMP_INPUT_MINUS_IO1         (                                                  COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_COMP2INNSEL_2 | COMP_CSR_COMP2INNSEL_1 | COMP_CSR_COMP2INNSEL_0) /*!< Comparator input minus connected to IO2 (pin PB3 for COMP2) (specific to COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_SELECTION_LPTIM Comparator output - Output selection specific to LPTIM peripheral
+  * @{
+  */
+#define LL_COMP_OUTPUT_LPTIM1_IN1_COMP1         (COMP_CSR_COMP1LPTIM1IN1)                                                   /*!< COMP output connected to TIM2 input capture 4 */
+#define LL_COMP_OUTPUT_LPTIM1_IN1_COMP2         (COMP_CSR_COMP2LPTIM1IN1)                                                   /*!< COMP output connected to TIM2 input capture 4 */
+#define LL_COMP_OUTPUT_LPTIM1_IN2_COMP2         (COMP_CSR_COMP2LPTIM1IN2)                                                   /*!< COMP output connected to TIM2 input capture 4 */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+  * @{
+  */
+#define LL_COMP_OUTPUTPOL_NONINVERTED   ((uint32_t)0x00000000U)  /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_COMP1POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+  * @{
+  */
+#define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
+  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for comparator startup time.                                         */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 25U)  /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time                     */
+/* (voltage from VrefInt, delay based on VrefInt startup time).               */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "TVREFINT").                                                     */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+  * @{
+  */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+  * @{
+  */
+
+/**
+  * @brief  Write a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to select the COMP common instance
+  *         to which is belonging the selected COMP instance.
+  * @note   COMP common register instance can be used to
+  *         set parameters common to several COMP instances.
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  __COMPx__ COMP instance
+  * @retval COMP common instance or value "0" if there is no COMP common instance.
+  */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \
+  (COMP12_COMMON)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+  * @{
+  */
+
+/**
+  * @brief  Set window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll COMP1_CSR COMP1WM       LL_COMP_SetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @param  WindowMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+  MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM, WindowMode);
+}
+
+/**
+  * @brief  Get window mode of a pair of comparators instances
+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+  * @rmtoll COMP1_CSR COMP1WM       LL_COMP_GetCommonWindowMode
+  * @param  COMPxy_COMMON Comparator common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE
+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance operating mode to adjust power and speed.
+  * @rmtoll COMP2_CSR COMP2SPEED    LL_COMP_SetPowerMode
+  * @param  COMPx Comparator instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+  *         
+  *         (1) Available only on COMP instance: COMP2.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2SPEED, PowerMode);
+}
+
+/**
+  * @brief  Get comparator instance operating mode to adjust power and speed.
+  * @note  Available only on COMP instance: COMP2.
+  * @rmtoll COMP2_CSR COMP2SPEED    LL_COMP_GetPowerMode\n
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED   (1)
+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+  *         
+  *         (1) Available only on COMP instance: COMP2.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2SPEED));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+  * @{
+  */
+
+/**
+  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
+  * @note   This function shall only be used for COMP2.
+  *         For setting COMP1 input it is recommended to use LL_COMP_SetInputMinus()
+  *         Plus (non-inverting) input is not configurable on COMP1.
+  *         Using this function for COMP1 will corrupt COMP1WM register
+  * @note   On this STM32 serie, specificity if using COMP instance COMP2
+  *         with COMP input based on VrefInt (VrefInt or subdivision
+  *         of VrefInt): scaler bridge is based on VrefInt and requires
+  *         to enable path from VrefInt (refer to literal
+  *         SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP).
+  * @rmtoll COMP2_CSR COMP2INNSEL   LL_COMP_ConfigInputs\n
+  *         COMP2_CSR COMP2INPSEL   LL_COMP_ConfigInputs
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
+  *
+  *         (1) Available only on COMP instance: COMP2.
+  *         (2) Available only on devices STM32L0 category 1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_COMP2INNSEL | COMP_CSR_COMP2INPSEL,
+             InputMinus | InputPlus);
+}
+
+/**
+  * @brief  Set comparator input plus (non-inverting).
+  * @note   Only COMP2 allows to set the input plus (non-inverting).
+  *         For COMP1 it is always PA1 IO, except when Windows Mode is selected.
+  * @rmtoll COMP2_CSR COMP2INPSEL    LL_COMP_SetInputPlus
+  * @param  COMPx Comparator instance
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
+  *
+  *         (1) Available only on COMP instance: COMP2.
+  *         (2) Available only on devices STM32L0 category 1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INPSEL, InputPlus);
+}
+
+/**
+  * @brief  Get comparator input plus (non-inverting).
+  * @note   Only COMP2 allows to set the input plus (non-inverting).
+  *         For COMP1 it is always PA1 IO, except when Windows Mode is selected.
+  * @rmtoll COMP2_CSR COMP2INPSEL    LL_COMP_GetInputPlus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO3 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO4 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO5 (1)
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO6 (1)(2)
+  *
+  *         (1) Available only on COMP instance: COMP2.
+  *         (2) Available only on devices STM32L0 category 1.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INPSEL));
+}
+
+/**
+  * @brief  Set comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 serie, specificity if using COMP instance COMP2
+  *         with COMP input based on VrefInt (VrefInt or subdivision
+  *         of VrefInt): scaler bridge is based on VrefInt and requires
+  *         to enable path from VrefInt (refer to literal
+  *         SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP).
+  * @rmtoll COMP1_CSR COMP1INNSEL    LL_COMP_SetInputMinus\n
+  *         COMP2_CSR COMP2INNSEL    LL_COMP_SetInputMinus
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2        (*)
+  *         
+  *         (*) Available only on COMP instance: COMP2.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INNSEL, InputMinus);
+}
+
+/**
+  * @brief  Get comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll COMP1_CSR COMP1INNSEL   LL_COMP_GetInputMinus\n
+  *         COMP2_CSR COMP2INNSEL   LL_COMP_GetInputMinus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT (*)
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2        (*)
+  *         
+  *         (*) Available only on COMP instance: COMP2.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMP2INNSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+  * @{
+  */
+
+/**
+  * @brief  Set comparator output LPTIM.
+  * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_SetOutputLPTIM\n
+  *         COMP2_CSR COMP2LPTIMIN1 LL_COMP_SetOutputLPTIM\n
+  *         COMP2_CSR COMP2LPTIMIN2 LL_COMP_SetOutputLPTIM
+  * @param  COMPx Comparator instance
+  * @param  OutputLptim This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*)
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**)
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**)
+  *         
+  *         (*)  Available only on COMP instance: COMP1.\n
+  *         (**) Available only on COMP instance: COMP2.
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputLPTIM(COMP_TypeDef *COMPx, uint32_t OutputLptim)
+{
+  MODIFY_REG(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN2), OutputLptim);
+}
+
+/**
+  * @brief  Get comparator output LPTIM.
+  * @rmtoll COMP1_CSR COMP1LPTIMIN1 LL_COMP_GetOutputLPTIM\n
+  *         COMP2_CSR COMP2LPTIMIN1 LL_COMP_GetOutputLPTIM\n
+  *         COMP2_CSR COMP2LPTIMIN2 LL_COMP_GetOutputLPTIM
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP1 (*)
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN1_COMP2 (**)
+  *         @arg @ref LL_COMP_OUTPUT_LPTIM1_IN2_COMP2 (**)
+  *         
+  *         (*)  Available only on COMP instance: COMP1.\n
+  *         (**) Available only on COMP instance: COMP2.
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputLPTIM(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN2)));
+}
+
+/**
+  * @brief  Set comparator instance output polarity.
+  * @rmtoll COMP     COMP1POLARITY  LL_COMP_SetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @param  OutputPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOLARITY, OutputPolarity);
+}
+
+/**
+  * @brief  Get comparator instance output polarity.
+  * @rmtoll COMP     COMP1POLARITY  LL_COMP_GetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOLARITY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+  * @{
+  */
+
+/**
+  * @brief  Enable comparator instance.
+  * @note   After enable from off state, comparator requires a delay
+  *         to reach reach propagation delay specification.
+  *         Refer to device datasheet, parameter "tSTART".
+  * @rmtoll COMP1_CSR COMP1EN       LL_COMP_Enable\n
+  *         COMP2_CSR COMP2EN       LL_COMP_Enable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+  * @brief  Disable comparator instance.
+  * @rmtoll COMP1_CSR COMP1EN       LL_COMP_Disable\n
+  *         COMP2_CSR COMP2EN       LL_COMP_Disable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+  CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+  * @brief  Get comparator enable state
+  *         (0: COMP is disabled, 1: COMP is enabled)
+  * @rmtoll COMP1_CSR COMP1EN        LL_COMP_IsEnabled\n
+  *         COMP2_CSR COMP2EN        LL_COMP_IsEnabled
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN));
+}
+
+/**
+  * @brief  Lock comparator instance.
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll COMP1_CSR COMP1LOCK     LL_COMP_Lock\n
+  *         COMP2_CSR COMP2LOCK     LL_COMP_Lock
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK);
+}
+
+/**
+  * @brief  Get comparator lock state
+  *         (0: COMP is unlocked, 1: COMP is locked).
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll COMP1_CSR COMP1LOCK     LL_COMP_IsLocked\n
+  *         COMP2_CSR COMP2LOCK     LL_COMP_IsLocked
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+  return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK));
+}
+
+/**
+  * @brief  Read comparator instance output level.
+  * @note   The comparator output level depends on the selected polarity
+  *         (Refer to function @ref LL_COMP_SetOutputPolarity()).
+  *         If the comparator polarity is not inverted:
+  *          - Comparator output is low when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is high when the input plus
+  *            is at a higher voltage than the input minus
+  *         If the comparator polarity is inverted:
+  *          - Comparator output is high when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is low when the input plus
+  *            is at a higher voltage than the input minus
+  * @rmtoll COMP1_CSR COMP1VALUE    LL_COMP_ReadOutputLevel\n
+  *         COMP2_CSR COMP2VALUE    LL_COMP_ReadOutputLevel
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUTVALUE)
+                    >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h
new file mode 100755
index 0000000..1303255
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h
@@ -0,0 +1,606 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_CORTEX_H
+#define __STM32L0xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     ((uint32_t)0x00000000U)                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     ((uint32_t)0x00000000U)                            /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              ((uint32_t)0x00U) /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              ((uint32_t)0x01U) /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              ((uint32_t)0x02U) /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              ((uint32_t)0x03U) /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              ((uint32_t)0x04U) /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              ((uint32_t)0x05U) /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              ((uint32_t)0x06U) /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              ((uint32_t)0x07U) /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   ((uint32_t)0x00U) /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Architecture number 
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
+  * @retval Value should be equal to 0xC for Cortex-M0+ devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC60 for Cortex-M0+
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h
new file mode 100755
index 0000000..e57fd67
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h
@@ -0,0 +1,477 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_CRC_H
+#define __STM32L0xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+  * @{
+  */
+#define LL_CRC_POLYLENGTH_32B              (uint32_t)0x00000000U                    /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+  * @{
+  */
+#define LL_CRC_INDATA_REVERSE_NONE         (uint32_t)0x00000000U                    /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+  * @{
+  */
+#define LL_CRC_OUTDATA_REVERSE_NONE        (uint32_t)0x00000000U                     /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
+  * @brief    Normal representation of this polynomial value is
+  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC32_POLY          (uint32_t)0x04C11DB7U                     /*!< Default CRC generating polynomial value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC_INITVALUE       (uint32_t)0xFFFFFFFFU                     /*!< Default CRC computation initialization value */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC calculation unit.
+  * @note   If Programmable Initial CRC value feature
+  *         is available, also set the Data Register to the value stored in the
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
+  * @param  CRCx CRC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+  * @brief  Configure size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @param  PolySize This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+  * @brief  Return size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the input data
+  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+  * @brief  Return type of reversal for input data bit order
+  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+  * @brief  Initialize the Programmable initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to write the correct value
+  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+  * @rmtoll INIT         INIT          LL_CRC_SetInitialData
+  * @param  CRCx CRC Instance
+  * @param  InitCrc Value to be programmed in Programmable initial CRC value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+  WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+  * @brief  Return current Initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to read the correct value
+  * @rmtoll INIT         INIT          LL_CRC_GetInitialData
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable initial CRC value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+  * @brief  Initialize the Programmable polynomial value
+  *         (coefficients of the polynomial to be used for CRC calculation).
+  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+  WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+  * @brief  Return current Programmable polynomial value
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable Polynomial value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Write given 32-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData32
+  * @param  CRCx CRC Instance
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+  * @brief  Write given 16-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData16
+  * @param  CRCx CRC Instance
+  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+  *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+}
+
+/**
+  * @brief  Write given 8-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData8
+  * @param  CRCx CRC Instance
+  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
+  * @rmtoll DR           DR            LL_CRC_ReadData32
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+  */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+  * @brief  Return current CRC calculation result. 16 bits value is returned.
+  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData16
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+  */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+  return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 8 bits value is returned.
+  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData8
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 7 bits value is returned.
+  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData7
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+  * @brief  Return data stored in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
+  * @param  CRCx CRC Instance
+  * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+  */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+  * @brief  Store data in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one byte.
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
+  * @param  CRCx CRC Instance
+  * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h
new file mode 100755
index 0000000..5706e82
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h
@@ -0,0 +1,814 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_CRS_H
+#define __STM32L0xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRS_LL_Private_Constants CRS Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define CRS_POSITION_TRIM        (CRS_CR_TRIM_Pos)     /* bit position in CR reg */
+#define CRS_POSITION_FECAP       (CRS_ISR_FECAP_Pos)   /* bit position in ISR reg */
+#define CRS_POSITION_FELIM       (CRS_CFGR_FELIM_Pos)  /* bit position in CFGR reg */
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)      
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)      
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 32, which corresponds to the middle of the trimming interval. 
+  *       The trimming step is around 67 kHz between two consecutive TRIM steps. 
+  *       A higher TRIM value corresponds to a higher output frequency
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)      
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between 
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 63
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 63
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR, 
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 
+             ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last 
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+  
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_CRS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h
new file mode 100755
index 0000000..90fbb07
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dac.h
@@ -0,0 +1,1434 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_dac.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_DAC_H
+#define __STM32L0xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (DAC1)
+
+/** @defgroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+  * @{
+  */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
+/* - channel bits position into register CR                                   */
+/* - channel bits position into register SWTRIG                               */
+/* - channel register offset of data holding register DHRx                    */
+/* - channel register offset of data output register DORx                     */
+#define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+#else
+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+#else
+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_REGOFFSET_MASK_POSBIT0             0x0000000FU  /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
+
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           16U   /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20U   /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24U   /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS              28U   /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
+
+/* DAC registers bits positions */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of DAC instance.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+                                             If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+                                             @note If waveform automatic generation mode is disabled, this parameter is discarded.
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+                                             
+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+  * @brief    Flags defines which can be used with LL_DAC_ReadReg function
+  * @{
+  */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
+  * @{
+  */
+#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+  * @{
+  */
+#define LL_DAC_CHANNEL_1                   (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_CHANNEL_2                   (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+  * @{
+  */
+#define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_CH3           (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM3 CH3 event. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM21_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM21 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+  * @{
+  */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+  * @{
+  */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+  * @{
+  */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+  * @{
+  */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+  * @}
+  */
+
+
+/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
+  * @{
+  */
+#define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
+  * @{
+  */
+/* List of DAC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
+  * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup       */
+/* (transition from disable to enable).                                       */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm (min), 50pF (max)                         */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tWAKEUP").                                                      */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time.                               */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm min, 50pF max                             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSETTLING").                                                    */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get DAC channel number in decimal format
+  *         from literals LL_DAC_CHANNEL_x.
+  *         Example:
+  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+  *            will return decimal number "1".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval 1...2 (value "2" depending on DAC channel 2 availability)
+  */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
+  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+  *         from number in decimal format.
+  *         Example:
+  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+  *           will return a data equivalent to "LL_DAC_CHANNEL_1".
+  * @note  If the input parameter does not correspond to a DAC channel,
+  *        this macro returns value '0'.
+  * @param  __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (((__DECIMAL_NB__) == 1U)                                                     \
+    ? (                                                                        \
+       LL_DAC_CHANNEL_1                                                        \
+      )                                                                        \
+      :                                                                        \
+      (((__DECIMAL_NB__) == 2U)                                                 \
+        ? (                                                                    \
+           LL_DAC_CHANNEL_2                                                    \
+          )                                                                    \
+          :                                                                    \
+          (                                                                    \
+           0                                                                   \
+          )                                                                    \
+      )                                                                        \
+  )
+#else
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (((__DECIMAL_NB__) == 1U)                                                     \
+    ? (                                                                        \
+       LL_DAC_CHANNEL_1                                                        \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       0                                                                       \
+      )                                                                        \
+  )
+#endif  /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Helper macro to define the DAC conversion data full-scale digital
+  *         value corresponding to the selected DAC resolution.
+  * @note   DAC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
+  ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+  * @brief  Helper macro to calculate the DAC conversion data (unit: digital
+  *         value) corresponding to a voltage (unit: mVolt).
+  * @note   This helper macro is intended to provide input data in voltage
+  *         rather than digital value,
+  *         to be used with LL DAC functions such as
+  *         @ref LL_DAC_ConvertData12RightAligned().
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+  *                         (unit: mVolt).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval DAC conversion data (unit: digital value)
+  */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+                                      __DAC_VOLTAGE__,\
+                                      __DAC_RESOLUTION__)                      \
+  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
+   / (__VREFANALOG_VOLTAGE__)                                                  \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+  * @{
+  */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Set the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   To set conversion trigger source, DAC channel must be disabled.
+  *         Otherwise, the setting is discarded.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_SetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_GetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  WaveAutoGeneration This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  NoiseLFSRMask This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriangleAmplitude This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output buffer for the selected DAC channel.
+  * @rmtoll CR       BOFF1          LL_DAC_SetOutputBuffer\n
+  *         CR       BOFF2          LL_DAC_SetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputBuffer This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output buffer state for the selected DAC channel.
+  * @rmtoll CR       BOFF1          LL_DAC_GetOutputBuffer\n
+  *         CR       BOFF2          LL_DAC_GetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_EnableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_DisableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC DMA transfer request state of the selected channel.
+  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
+  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Function to help to configure DMA transfer to DAC: retrieve the
+  *         DAC register address from DAC instance and a list of DAC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These DAC registers are data holding registers:
+  *         when DAC conversion is requested, DAC generates a DMA transfer
+  *         request to have data available in DAC data holding registers.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+  * @retval DAC register address
+  */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
+  /* DAC channel selected.                                                    */
+  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Enable\n
+  *         CR       EN2            LL_DAC_Enable
+  * @note   After enable from off state, DAC channel requires a delay
+  *         for output voltage to reach accuracy +/- 1 LSB.
+  *         Refer to device datasheet, parameter "tWAKEUP".
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Disable\n
+  *         CR       EN2            LL_DAC_Disable
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC enable state of the selected channel.
+  *         (0: DAC channel is disabled, 1: DAC channel is enabled)
+  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
+  *         CR       EN2            LL_DAC_IsEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Enable DAC trigger of the selected channel.
+  * @note   - If DAC trigger is disabled, DAC conversion is performed
+  *           automatically once the data holding register is updated,
+  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *           @ref LL_DAC_ConvertData12RightAligned(), ...
+  *         - If DAC trigger is enabled, DAC conversion is performed
+  *           only when a hardware of software trigger event is occurring.
+  *           Select trigger source using
+  *           function @ref LL_DAC_SetTriggerSource().
+  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
+  *         CR       TEN2           LL_DAC_EnableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC trigger of the selected channel.
+  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
+  *         CR       TEN2           LL_DAC_DisableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC trigger state of the selected channel.
+  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
+  *         CR       TEN2           LL_DAC_IsTriggerEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (READ_BIT(DACx->CR,
+                   DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+          == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+  * @brief  Trig DAC conversion by software for the selected DAC channel.
+  * @note   Preliminarily, DAC trigger must be set to software trigger
+  *         using function @ref LL_DAC_SetTriggerSource()
+  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
+  *         and DAC trigger must be enabled using
+  *         function @ref LL_DAC_EnableTrigger().
+  * @note   For devices featuring DAC with 2 channels: this function
+  *         can perform a SW start of both DAC channels simultaneously.
+  *         Two channels can be selected as parameter.
+  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
+  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
+  * @param  DACx DAC instance
+  * @param  DAC_Channel  This parameter can a combination of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->SWTRIGR,
+          (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
+  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
+  
+  MODIFY_REG(*preg,
+             DAC_DHR12R1_DACC1DHR,
+             Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
+  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
+  
+  MODIFY_REG(*preg,
+             DAC_DHR12L1_DACC1DHR,
+             Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
+  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
+  
+  MODIFY_REG(*preg,
+             DAC_DHR8R1_DACC1DHR,
+             Data);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
+  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR12RD,
+             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for both DAC channels.
+  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
+  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
+  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
+  /*       the 4 LSB must be taken into account for the shift value.          */
+  MODIFY_REG(DACx->DHR12LD,
+             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
+  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR8RD,
+             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+  * @brief  Retrieve output data currently generated for the selected DAC channel.
+  * @note   Whatever alignment and resolution settings
+  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *         @ref LL_DAC_ConvertData12RightAligned(), ...),
+  *         output data format is 12 bits right aligned (LSB aligned on bit 0).
+  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
+  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
+  
+  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+/**
+  * @brief  Get DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h
new file mode 100755
index 0000000..1b42034
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h
@@ -0,0 +1,2153 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_DMA_H
+#define __STM32L0xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+#if defined(DMA1_Channel6)
+  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+#endif /*DMA1_Channel6*/
+#if defined(DMA1_Channel7)
+  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+#endif /*DMA1_Channel7*/
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS            ((Channel-1U)*4U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note: The circular buffer mode cannot be used if the memory to memory
+                                               data transfer direction is configured on the selected Channel
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMA_LL_EC_REQUEST
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
+  * @{
+  */
+#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
+#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
+#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
+#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
+#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
+#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
+#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
+#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
+#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
+#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
+#if defined(DMA1_Channel6)
+#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
+#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
+#endif
+#if defined(DMA1_Channel7)
+#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
+#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
+#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
+  * @{
+  */
+#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
+#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
+#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
+#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
+#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
+#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
+#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
+#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
+#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
+#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
+#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
+#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
+#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
+#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
+#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
+#if defined(DMA1_Channel6)
+#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
+#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
+#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
+#endif
+#if defined(DMA1_Channel7)
+#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
+#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
+#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
+  * @{
+  */
+#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
+#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_1                  ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2                  ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3                  ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4                  ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5                  ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
+#if defined(DMA1_Channel6)
+#define LL_DMA_CHANNEL_6                  ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
+#endif
+#if defined(DMA1_Channel7)
+#define LL_DMA_CHANNEL_7                  ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
+#endif
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL                ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                ((uint32_t)0x00000000U) /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+  * @{
+  */
+#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+  * @{
+  */
+#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
+#define LL_DMA_MEMORY_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               ((uint32_t)0x00000000U) /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
+  * @{
+  */
+#define LL_DMA_REQUEST_0                  ((uint32_t)0x00000000U) /*!< DMA peripheral request 0  */
+#define LL_DMA_REQUEST_1                  ((uint32_t)0x00000001U) /*!< DMA peripheral request 1  */
+#define LL_DMA_REQUEST_2                  ((uint32_t)0x00000002U) /*!< DMA peripheral request 2  */
+#define LL_DMA_REQUEST_3                  ((uint32_t)0x00000003U) /*!< DMA peripheral request 3  */
+#define LL_DMA_REQUEST_4                  ((uint32_t)0x00000004U) /*!< DMA peripheral request 4  */
+#define LL_DMA_REQUEST_5                  ((uint32_t)0x00000005U) /*!< DMA peripheral request 5  */
+#define LL_DMA_REQUEST_6                  ((uint32_t)0x00000006U) /*!< DMA peripheral request 6  */
+#define LL_DMA_REQUEST_7                  ((uint32_t)0x00000007U) /*!< DMA peripheral request 7  */
+#define LL_DMA_REQUEST_8                  ((uint32_t)0x00000008U) /*!< DMA peripheral request 8  */
+#define LL_DMA_REQUEST_9                  ((uint32_t)0x00000009U) /*!< DMA peripheral request 9  */
+#define LL_DMA_REQUEST_10                 ((uint32_t)0x0000000AU) /*!< DMA peripheral request 10 */
+#define LL_DMA_REQUEST_11                 ((uint32_t)0x0000000BU) /*!< DMA peripheral request 11 */
+#define LL_DMA_REQUEST_12                 ((uint32_t)0x0000000CU) /*!< DMA peripheral request 12 */
+#define LL_DMA_REQUEST_13                 ((uint32_t)0x0000000DU) /*!< DMA peripheral request 13 */
+#define LL_DMA_REQUEST_14                 ((uint32_t)0x0000000EU) /*!< DMA peripheral request 14 */
+#define LL_DMA_REQUEST_15                 ((uint32_t)0x0000000FU) /*!< DMA peripheral request 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Channely into DMAx
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
+
+/**
+  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
+  * @retval LL_DMA_CHANNEL_y
+  */
+#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#elif defined (DMA1_Channel6)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ LL_DMA_CHANNEL_6)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ LL_DMA_CHANNEL_5)
+#endif /* DMA1_Channel6 && DMA1_Channel7 */
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
+  * @retval DMAx_Channely
+  */
+#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#elif defined (DMA1_Channel6)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ DMA1_Channel6)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ DMA1_Channel5)
+#endif /* DMA1_Channel6 && DMA1_Channel7 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_EnableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Disable DMA channel.
+  * @rmtoll CCR          EN            LL_DMA_DisableChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief  Check if DMA channel is enabled or disabled.
+  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+  * @brief  Configure all parameters link to DMA transfer.
+  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
+  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
+  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CCR          PINC          LL_DMA_ConfigTransfer\n
+  *         CCR          MINC          LL_DMA_ConfigTransfer\n
+  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CCR          PL            LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+             Configuration);
+}
+
+/**
+  * @brief  Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+  * @brief  Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
+  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+  * @brief  Set DMA mode circular or normal.
+  * @note The circular buffer mode cannot be used if the memory-to-memory
+  * data transfer is configured on the selected Channel.
+  * @rmtoll CCR          CIRC          LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+             Mode);
+}
+
+/**
+  * @brief  Get DMA mode circular or normal.
+  * @rmtoll CCR          CIRC          LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_CIRC));
+}
+
+/**
+  * @brief  Set Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+             PeriphOrM2MSrcIncMode);
+}
+
+/**
+  * @brief  Get Peripheral increment mode.
+  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PINC));
+}
+
+/**
+  * @brief  Set Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+             MemoryOrM2MDstIncMode);
+}
+
+/**
+  * @brief  Get Memory increment mode.
+  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_MINC));
+}
+
+/**
+  * @brief  Set Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+             PeriphOrM2MSrcDataSize);
+}
+
+/**
+  * @brief  Get Peripheral size.
+  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PSIZE));
+}
+
+/**
+  * @brief  Set Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+             MemoryOrM2MDstDataSize);
+}
+
+/**
+  * @brief  Get Memory size.
+  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_MSIZE));
+}
+
+/**
+  * @brief  Set Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+             Priority);
+}
+
+/**
+  * @brief  Get Channel priority level.
+  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_PL));
+}
+
+/**
+  * @brief  Set Number of data to transfer.
+  * @note   This action has no effect if
+  *         channel is enabled.
+  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+             DMA_CNDTR_NDT, NbData);
+}
+
+/**
+  * @brief  Get Number of data to transfer.
+  * @note   Once the channel is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+                   DMA_CNDTR_NDT));
+}
+
+/**
+  * @brief  Configure the Source and Destination addresses.
+  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
+  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
+  *         CMAR         MA            LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+                                            uint32_t DstAddress, uint32_t Direction)
+{
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+               SrcAddress);
+    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+               DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+               SrcAddress);
+    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+               DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+             MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+             PeriphAddress);
+}
+
+/**
+  * @brief  Get Memory address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
+                   DMA_CMAR_MA));
+}
+
+/**
+  * @brief  Get Peripheral address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
+                   DMA_CPAR_PA));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+             MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+             MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
+                   DMA_CPAR_PA));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
+                   DMA_CMAR_MA));
+}
+
+/**
+  * @brief  Set DMA request for DMA instance on Channel x.
+  * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
+  * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_SetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  PeriphRequest This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_REQUEST_0
+  *         @arg @ref LL_DMA_REQUEST_1
+  *         @arg @ref LL_DMA_REQUEST_2
+  *         @arg @ref LL_DMA_REQUEST_3
+  *         @arg @ref LL_DMA_REQUEST_4
+  *         @arg @ref LL_DMA_REQUEST_5
+  *         @arg @ref LL_DMA_REQUEST_6
+  *         @arg @ref LL_DMA_REQUEST_7
+  *         @arg @ref LL_DMA_REQUEST_8
+  *         @arg @ref LL_DMA_REQUEST_9
+  *         @arg @ref LL_DMA_REQUEST_10
+  *         @arg @ref LL_DMA_REQUEST_11
+  *         @arg @ref LL_DMA_REQUEST_12
+  *         @arg @ref LL_DMA_REQUEST_13
+  *         @arg @ref LL_DMA_REQUEST_14
+  *         @arg @ref LL_DMA_REQUEST_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
+{
+  MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+             DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
+}
+
+/**
+  * @brief  Get DMA request for DMA instance on Channel x.
+  * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C2S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C3S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C4S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C5S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C6S           LL_DMA_GetPeriphRequest\n
+  *         CSELR        C7S           LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_REQUEST_0
+  *         @arg @ref LL_DMA_REQUEST_1
+  *         @arg @ref LL_DMA_REQUEST_2
+  *         @arg @ref LL_DMA_REQUEST_3
+  *         @arg @ref LL_DMA_REQUEST_4
+  *         @arg @ref LL_DMA_REQUEST_5
+  *         @arg @ref LL_DMA_REQUEST_6
+  *         @arg @ref LL_DMA_REQUEST_7
+  *         @arg @ref LL_DMA_REQUEST_8
+  *         @arg @ref LL_DMA_REQUEST_9
+  *         @arg @ref LL_DMA_REQUEST_10
+  *         @arg @ref LL_DMA_REQUEST_11
+  *         @arg @ref LL_DMA_REQUEST_12
+  *         @arg @ref LL_DMA_REQUEST_13
+  *         @arg @ref LL_DMA_REQUEST_14
+  *         @arg @ref LL_DMA_REQUEST_15
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+                   DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Channel 1 global interrupt flag.
+  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+  * @brief  Get Channel 2 global interrupt flag.
+  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+  * @brief  Get Channel 3 global interrupt flag.
+  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+  * @brief  Get Channel 4 global interrupt flag.
+  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+  * @brief  Get Channel 5 global interrupt flag.
+  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Get Channel 6 global interrupt flag.
+  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 global interrupt flag.
+  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+#endif
+
+/**
+  * @brief  Get Channel 1 transfer complete flag.
+  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+  * @brief  Get Channel 2 transfer complete flag.
+  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+  * @brief  Get Channel 3 transfer complete flag.
+  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+  * @brief  Get Channel 4 transfer complete flag.
+  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+  * @brief  Get Channel 5 transfer complete flag.
+  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Get Channel 6 transfer complete flag.
+  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 transfer complete flag.
+  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+#endif
+
+/**
+  * @brief  Get Channel 1 half transfer flag.
+  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+  * @brief  Get Channel 2 half transfer flag.
+  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+  * @brief  Get Channel 3 half transfer flag.
+  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+  * @brief  Get Channel 4 half transfer flag.
+  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+  * @brief  Get Channel 5 half transfer flag.
+  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Get Channel 6 half transfer flag.
+  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 half transfer flag.
+  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+#endif
+
+/**
+  * @brief  Get Channel 1 transfer error flag.
+  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+  * @brief  Get Channel 2 transfer error flag.
+  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+  * @brief  Get Channel 3 transfer error flag.
+  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+  * @brief  Get Channel 4 transfer error flag.
+  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+  * @brief  Get Channel 5 transfer error flag.
+  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Get Channel 6 transfer error flag.
+  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Get Channel 7 transfer error flag.
+  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+#endif
+
+/**
+  * @brief  Clear Channel 1 global interrupt flag.
+  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 global interrupt flag.
+  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 global interrupt flag.
+  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 global interrupt flag.
+  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 global interrupt flag.
+  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Clear Channel 6 global interrupt flag.
+  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7 global interrupt flag.
+  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+#endif
+
+/**
+  * @brief  Clear Channel 1  transfer complete flag.
+  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  transfer complete flag.
+  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  transfer complete flag.
+  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  transfer complete flag.
+  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  transfer complete flag.
+  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Clear Channel 6  transfer complete flag.
+  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7  transfer complete flag.
+  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+#endif
+
+/**
+  * @brief  Clear Channel 1  half transfer flag.
+  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+  * @brief  Clear Channel 2  half transfer flag.
+  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+  * @brief  Clear Channel 3  half transfer flag.
+  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+  * @brief  Clear Channel 4  half transfer flag.
+  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+  * @brief  Clear Channel 5  half transfer flag.
+  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Clear Channel 6  half transfer flag.
+  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7  half transfer flag.
+  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+#endif
+
+/**
+  * @brief  Clear Channel 1 transfer error flag.
+  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+  * @brief  Clear Channel 2 transfer error flag.
+  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+  * @brief  Clear Channel 3 transfer error flag.
+  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+  * @brief  Clear Channel 4 transfer error flag.
+  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+  * @brief  Clear Channel 5 transfer error flag.
+  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+#if defined(DMA1_Channel6)
+/**
+  * @brief  Clear Channel 6 transfer error flag.
+  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+#endif
+
+#if defined(DMA1_Channel7)
+/**
+  * @brief  Clear Channel 7 transfer error flag.
+  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Enable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Enable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Disable Transfer complete interrupt.
+  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief  Disable Half transfer interrupt.
+  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief  Disable Transfer error interrupt.
+  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+  * @brief  Check if Transfer complete Interrupt is enabled.
+  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+  * @brief  Check if Half transfer Interrupt is enabled.
+  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+  * @brief  Check if Transfer error Interrupt is enabled.
+  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+                   DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h
new file mode 100755
index 0000000..e6a6e70
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h
@@ -0,0 +1,1032 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_EXTI_H
+#define __STM32L0xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
new file mode 100755
index 0000000..dca7307
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
@@ -0,0 +1,959 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_GPIO_H
+#define __STM32L0xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
+                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
+                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
+                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+                                           GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 ((uint32_t)0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             ((uint32_t)0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    ((uint32_t)0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       ((uint32_t)0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       ((uint32_t)0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       ((uint32_t)0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       ((uint32_t)0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       ((uint32_t)0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       ((uint32_t)0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       ((uint32_t)0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       ((uint32_t)0x0000007U) /*!< Select alternate function 7 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF7 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0),
+             ((((Pin * Pin) * Pin) * Pin) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFRL0)) / (((Pin * Pin) * Pin) * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF7 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0),
+             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF7 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFRH0)) / ((((Pin >> 8U) *
+                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h
new file mode 100755
index 0000000..ad6e466
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h
@@ -0,0 +1,2244 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_I2C_H
+#define __STM32L0xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+                                     This parameter must be set by referring to the STM32CubeMX Tool and
+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+                                     This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
+  * @{
+  */
+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+  * @{
+  */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+  * @{
+  */
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+  * @{
+  */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+  * @{
+  */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+  * @{
+  */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+  * @{
+  */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                                /*!< Don't Generate Stop and Start condition.                */
+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)                                     /*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Start for write request.                       */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+  * @{
+  */
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
+  * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+  * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+  * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
+        ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @note   When PE = 0, the I2C SCL and SDA lines are released.
+  *         Internal state machines and status bits are put back to their reset value.
+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
+  *         CR1          DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+}
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TXDR register */
+    data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+  }
+  else
+  {
+    /* return address of RXDR register */
+    data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+  * @brief  Enable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Disable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+}
+
+/**
+  * @brief  Enable Wakeup from STOP.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when Digital Filter is disabled.
+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Disable Wakeup from STOP.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Check if Wakeup from STOP is enabled or disabled.
+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+}
+
+/**
+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
+  * @note   Changing this bit is not allowed, when the START bit is set.
+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @param  AddressingMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+  * @brief  Get the Master addressing mode.
+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Disable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+  * @param  OwnAddrMask This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+}
+
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
+  * @param  I2Cx I2C Instance.
+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+  WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+  * @brief  Get the Timing Prescaler setting.
+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+  * @brief  Get the SCL low period setting.
+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+  * @brief  Get the SCL high period setting.
+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+  * @brief  Get the SDA hold time.
+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+  * @brief  Get the SDA setup time.
+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
+  *         CR1          SMBDEN        LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
+  *         CR1          SMBDEN        LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+}
+
+/**
+  * @brief  Configure the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @param  TimeoutB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+    uint32_t TimeoutB)
+{
+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA setting.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+  * @brief  Set the SMBus Clock TimeoutA mode.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA mode.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutB is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Enable the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Disable the SMBus Clock Timeout.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Disable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Check if the TXIS Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+}
+
+/**
+  * @brief  Enable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Disable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Check if Address match interrupt is enabled or disabled.
+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+}
+
+/**
+  * @brief  Enable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Disable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+}
+
+/**
+  * @brief  Enable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Disable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Check if STOP detection interrupt is enabled or disabled.
+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+}
+
+/**
+  * @brief  Enable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+}
+
+/**
+  * @brief  Indicate the status of Transmit interrupt flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+}
+
+/**
+  * @brief  Indicate the status of Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the received slave address matched with one of the enabled slave address.
+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+}
+
+/**
+  * @brief  Indicate the status of Not Acknowledge received flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a NACK is received after a byte transmission.
+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=1 and NBYTES date have been transferred.
+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When the received PEC does not match with the PEC register content.
+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When a timeout or extended clock timeout occurs.
+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When SMBus host configuration, SMBus alert enabled and
+  *              a falling edge event occurs on SMBA pin.
+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+  * @brief  Clear Not Acknowledge flag.
+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+  * @brief  Clear Transmit data register empty flag (TXE).
+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable automatic STOP condition generation (master mode).
+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+  *         This bit has no effect in slave mode or when RELOAD bit is set.
+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Disable automatic STOP condition generation (master mode).
+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Check if automatic STOP condition is enabled or disabled.
+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+}
+
+/**
+  * @brief  Enable reload mode (master mode).
+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Disable reload mode (master mode).
+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Check if reload mode is enabled or disabled.
+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+}
+
+/**
+  * @brief  Configure the number of bytes for transfer.
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Get the number of bytes configured for transfer.
+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+  * @note   Usage in Slave mode only.
+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master sends the complete 10bit slave address read sequence :
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+}
+
+/**
+  * @brief  Configure the transfer direction (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @param  TransferRequest This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+  * @brief  Get the transfer direction requested (master mode).
+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+  * @brief  Configure the slave address for transfer (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+  * @brief  Get the slave address programmed for transfer.
+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
+  *         CR2          ADD10         LL_I2C_HandleTransfer\n
+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
+  *         CR2          START         LL_I2C_HandleTransfer\n
+  *         CR2          STOP          LL_I2C_HandleTransfer\n
+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
+  *         CR2          HEAD10R       LL_I2C_HandleTransfer
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr Specifies the slave address to be programmed.
+  * @param  SlaveAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_RELOAD
+  *         @arg @ref LL_I2C_MODE_AUTOEND
+  *         @arg @ref LL_I2C_MODE_SOFTEND
+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+  *         @arg @ref LL_I2C_GENERATE_STOP
+  *         @arg @ref LL_I2C_GENERATE_START_READ
+  *         @arg @ref LL_I2C_GENERATE_START_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+                                                          uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+             SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+}
+
+/**
+  * @brief  Indicate the value of transfer direction (slave mode).
+  * @note   RESET: Write transfer, Slave enters in receiver mode.
+  *         SET: Read transfer, Slave enters in transmitter mode.
+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+  * @brief  Return the slave matched address.
+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+  *         This bit has no effect when RELOAD bit is set.
+  *         This bit has no effect in device mode when SBC bit is not set.
+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   Macro @ref IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+*/
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h
new file mode 100755
index 0000000..0870b60
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_iwdg.h
@@ -0,0 +1,361 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_iwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of IWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_IWDG_H
+#define __STM32L0xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+#define LL_IWDG_KEY_RELOAD                 ((uint32_t)0x0000AAAAU)               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 ((uint32_t)0x0000CCCCU)               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       ((uint32_t)0x00005555U)               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      ((uint32_t)0x00000000U)               /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
+  * @{
+  */
+#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
+  * @{
+  */
+#define LL_IWDG_PRESCALER_4                ((uint32_t)0x00000000U)               /*!< Divider by 4   */
+#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
+#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
+#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
+#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
+#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+  * @{
+  */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Start the Independent Watchdog
+  * @note   Except if the hardware watchdog option is selected
+  * @rmtoll KR           KEY           LL_IWDG_Enable
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+  * @brief  Select the prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+  * @brief  Get the selected prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+  * @brief  Specify the IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+  * @brief  Get the specified IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+/**
+  * @brief  Specify high limit of the window value to be compared to the down-counter.
+  * @rmtoll WINR         WIN           LL_IWDG_SetWindow
+  * @param  IWDGx IWDG Instance
+  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+  * @brief  Get the high limit of the window value specified.
+  * @rmtoll WINR         WIN           LL_IWDG_GetWindow
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+  return (uint32_t)(READ_REG(IWDGx->WINR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if flag Prescaler Value Update is set or not
+  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+  * @brief  Check if flag Reload Value Update is set or not
+  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+/**
+  * @brief  Check if flag Window Value Update is set or not
+  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+}
+
+/**
+  * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
+  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
+  *         SR           WVU           LL_IWDG_IsReady\n
+  *         SR           RVU           LL_IWDG_IsReady
+  * @param  IWDGx IWDG Instance
+  * @retval State of bits (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* IWDG) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h
new file mode 100755
index 0000000..9e9eca3
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lptim.h
@@ -0,0 +1,1380 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_lptim.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPTIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_LPTIM_H
+#define __STM32L0xx_LL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+#if defined (LPTIM1) 
+	
+/** @defgroup LPTIM_LL LPTIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  LPTIM Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
+                                This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+
+  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
+                                This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
+
+                                This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+
+  uint32_t Waveform;       /*!< Specifies the waveform shape.
+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+
+  uint32_t Polarity;       /*!< Specifies waveform polarity.
+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
+
+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+} LL_LPTIM_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
+  * @{
+  */
+#define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */
+#define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
+#define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
+#define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */
+#define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
+#define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
+#define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
+  * @{
+  */
+#define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */
+#define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */
+#define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */
+#define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */
+#define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */
+#define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */
+#define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
+  * @{
+  */
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT       /*!<LP Timer starts in continuous mode*/
+#define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT       /*!<LP Tilmer starts in single mode*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
+  * @{
+  */
+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE        ((uint32_t)0x00000000U) /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD      /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
+  * @{
+  */
+#define LL_LPTIM_COUNTER_MODE_INTERNAL        ((uint32_t)0x00000000U) /*!<The counter is incremented following each internal clock pulse*/
+#define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE    /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM          ((uint32_t)0x00000000U) /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE         /*!<LPTIM  generates a Set Once waveform*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR      ((uint32_t) 0x00000000U) /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL        /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
+  * @{
+  */
+#define LL_LPTIM_PRESCALER_DIV1               ((uint32_t)0x000000U)                     /*!<Prescaler division factor is set to 1*/
+#define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
+#define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
+#define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
+#define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
+#define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
+#define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
+#define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
+  * @{
+  */
+#define LL_LPTIM_TRIG_SOURCE_GPIO             ((uint32_t)0x00000000U)                       /*!<External input trigger is connected to TIMx_ETR input*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                          /*!<External input trigger is connected to RTC Alarm A*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                          /*!<External input trigger is connected to RTC Alarm B*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                          /*!<External input trigger is connected to RTC Tamper 2*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
+#define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
+#define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                            /*!<External input trigger is connected to COMP2 output*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
+  * @{
+  */
+#define LL_LPTIM_TRIG_FILTER_NONE             ((uint32_t)0x00000000U) /*!<Any trigger active level change is considered as a valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0     /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1     /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT       /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
+  * @{
+  */
+#define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0    /*!<LPTIM counter starts when a rising edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1    /*!<LPTIM counter starts when a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN      /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
+  * @{
+  */
+#define LL_LPTIM_CLK_SOURCE_INTERNAL          ((uint32_t)0x00000000U) /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL        /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
+  * @{
+  */
+#define LL_LPTIM_CLK_FILTER_NONE              ((uint32_t)0x00000000U) /*!<Any external clock signal level change is considered as a valid transition*/
+#define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0      /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1      /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT        /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_LPTIM_CLK_POLARITY_RISING          ((uint32_t)0x00000000U) /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
+  * @{
+  */
+#define LL_LPTIM_ENCODER_MODE_RISING          ((uint32_t)0x00000000U) /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0      /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1      /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the LPTIM instance
+  * @note After setting the ENABLE bit, a delay of two counter clock is needed
+  *       before the LPTIM instance is actually enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_Enable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Disable the LPTIM instance
+  * @rmtoll CR           ENABLE        LL_LPTIM_Disable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM instance is enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
+}
+
+/**
+  * @brief  Starts the LPTIM counter in the desired mode.
+  * @note LPTIM instance must be enabled before starting the counter.
+  * @note It is possible to change on the fly from One Shot mode to
+  *       Continuous mode.
+  * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
+  *         CR           SNGSTRT       LL_LPTIM_StartCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  OperatingMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
+{
+  MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
+}
+
+/**
+  * @brief  Set the LPTIM registers update mode (enable/disable register preload)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  UpdateMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
+}
+
+/**
+  * @brief  Get the LPTIM registers update mode
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
+}
+
+/**
+  * @brief  Set the auto reload value
+  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+  * @note After a write to the LPTIMx_ARR register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before  the ARROK flag be set, will
+  *       lead to unpredictable results.
+  * @note autoreload value be strictly greater than the compare value.
+  * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
+{
+  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
+}
+
+/**
+  * @brief  Get actual auto reload value
+  * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
+}
+
+/**
+  * @brief  Set the compare value
+  * @note After a write to the LPTIMx_CMP register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before the CMPOK flag be set, will
+  *       lead to unpredictable results.
+  * @rmtoll CMP          CMP           LL_LPTIM_SetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value
+  * @rmtoll CMP          CMP           LL_LPTIM_GetCompare
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
+}
+
+/**
+  * @brief  Get actual counter value
+  * @note When the LPTIM instance is running with an asynchronous clock, reading
+  *       the LPTIMx_CNT register may return unreliable values. So in this case
+  *       it is necessary to perform two consecutive read accesses and verify
+  *       that the two returned values are identical.
+  * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Counter value
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
+}
+
+/**
+  * @brief  Set the counter mode (selection of the LPTIM counter clock source).
+  * @note The counter mode can be set only when the LPTIM instance is disabled.
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
+}
+
+/**
+  * @brief  Get the counter mode
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
+}
+
+/**
+  * @brief  Configure the LPTIM instance output (LPTIMx_OUT)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note Regarding the LPTIM output polarity the change takes effect
+  *       immediately, so the output default value will change immediately after
+  *       the polarity is re-configured, even before the timer is enabled.
+  * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n
+  *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
+}
+
+/**
+  * @brief  Set  waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
+}
+
+/**
+  * @brief  Get actual waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
+}
+
+/**
+  * @brief  Set  output polarity
+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
+}
+
+/**
+  * @brief  Get actual output polarity
+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
+}
+
+/**
+  * @brief  Set actual prescaler division ratio.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When the LPTIM is configured to be clocked by an internal clock source
+  *       and the LPTIM counter is configured to be updated by active edges
+  *       detected on the LPTIM external Input1, the internal clock provided to
+  *       the LPTIM must be not be prescaled.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
+}
+
+/**
+  * @brief  Get actual prescaler division ratio.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note The first trigger event will start the timer, any successive trigger
+  *       event will reset the counter and the timer will restart.
+  * @note The timeout value corresponds to the compare value; if no trigger
+  *       occurs within the expected time frame, the MCU is waked-up by the
+  *       compare match event.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Disable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note A trigger event arriving when the timer is already started will be
+  *       ignored.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Indicate whether the timeout function is enabled.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
+}
+
+/**
+  * @brief  Start the LPTIM counter
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
+}
+
+/**
+  * @brief  Configure the external trigger used as a trigger event for the LPTIM.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for the trigger.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
+}
+
+/**
+  * @brief  Get actual external trigger source.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
+}
+
+/**
+  * @brief  Get actual external trigger filter.
+  * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
+}
+
+/**
+  * @brief  Get actual external trigger polarity.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set the source of the clock used by the LPTIM instance.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
+}
+
+/**
+  * @brief  Get actual LPTIM instance clock source.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
+}
+
+/**
+  * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When both external clock signal edges are considered active ones,
+  *       the LPTIM must also be clocked by an internal clock source with a
+  *       frequency equal to at least four times the external clock frequency.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for external clock.
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
+  *         CFGR         CKPOL         LL_LPTIM_ConfigClock
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockFilter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+  * @brief  Get actual clock polarity
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Get actual clock digital filter
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
+  * @{
+  */
+
+/**
+  * @brief  Configure the encoder mode.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
+}
+
+/**
+  * @brief  Get actual encoder mode.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Enable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note In this mode the LPTIM instance must be clocked by an internal clock
+  *       source. Also, the prescaler division ratio must be equal to 1.
+  * @note LPTIM instance must be configured in continuous mode prior enabling
+  *       the encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Disable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM operates in encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear the compare match flag (CMPMCF)
+  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
+}
+
+/**
+  * @brief  Inform application whether a compare match interrupt has occurred.
+  * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
+}
+
+/**
+  * @brief  Clear the autoreload match flag (ARRMCF)
+  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
+}
+
+/**
+  * @brief  Inform application whether a autoreload match interrupt has occured.
+  * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
+}
+
+/**
+  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
+  * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
+}
+
+/**
+  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
+  * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
+}
+
+/**
+  * @brief  Clear the compare register update interrupt flag (CMPOKCF).
+  * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
+  * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
+}
+
+/**
+  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
+  * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
+  * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
+}
+
+/**
+  * @brief  Clear the counter direction change to up interrupt flag (UPCF).
+  * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
+}
+
+/**
+  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
+  * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+  * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+  * @brief  Disable compare match interrupt (CMPMIE).
+  * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
+}
+
+/**
+  * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.
+  * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
+}
+
+/**
+  * @brief  Enable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+  * @brief  Disable autoreload match interrupt (ARRMIE).
+  * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+  * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
+}
+
+/**
+  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
+}
+
+/**
+  * @brief  Enable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+  * @brief  Disable compare register write completed interrupt (CMPOKIE).
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
+}
+
+/**
+  * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
+  * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
+}
+
+/**
+  * @brief  Enable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+  * @brief  Disable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+  * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
+}
+
+/**
+  * @brief  Enable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+  * @brief  Disable direction change to up interrupt (UPIE).
+  * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
+  * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
+}
+
+/**
+  * @brief  Enable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+  * @brief  Disable direction change to down interrupt (DOWNIE).
+  * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+  * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_LPTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h
new file mode 100755
index 0000000..d9306ed
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h
@@ -0,0 +1,2153 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_LPUART_H
+#define __STM32L0xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define LPUART_POSITION_CR1_DEDT      (uint32_t)16U
+#define LPUART_POSITION_CR1_DEAT      (uint32_t)21U
+#define LPUART_POSITION_CR2_ADD       (uint32_t)24U
+
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     (uint32_t)(256U)
+#define LPUART_BRR_MASK               (uint32_t)(0x000FFFFFU)
+#define LPUART_BRR_MIN_VALUE          (uint32_t)(0x00000300U)
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise detected flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */
+#define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */
+#define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE                 USART_ISR_RXNE                /*!< Read data register not empty flag */
+#define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE                  USART_ISR_TXE                 /*!< Transmit data register empty flag */
+#define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */
+#define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */
+#define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE               USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE                USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */
+#define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE           (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE              (uint32_t)0x00000000U              /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE          (uint32_t)0x00000000U              /*!<  LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B             (uint32_t)0x00000000U              /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1               (uint32_t)0x00000000U              /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD            (uint32_t)0x00000000U              /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD     (uint32_t)0x00000000U              /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE    (uint32_t)0x00000000U              /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST        (uint32_t)0x00000000U              /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B        (uint32_t)0x00000000U              /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE           (uint32_t)0x00000000U              /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS        (uint32_t)0x00000000U                   /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         (uint32_t)0x00000000U              /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    (uint32_t)0U                       /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     (uint32_t)1U                       /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << LPUART_POSITION_CR2_ADD)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> LPUART_POSITION_CR2_ADD);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
+{
+  LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
+{
+  register uint32_t lpuartdiv = 0x0U;
+  register uint32_t brrresult = 0x0U;
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << LPUART_POSITION_CR1_DEDT);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> LPUART_POSITION_CR1_DEDT);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << LPUART_POSITION_CR1_DEAT);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> LPUART_POSITION_CR1_DEAT);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+  * @brief  Check if the LPUART Noise detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+  * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not
+  * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data flush
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_LPUART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
new file mode 100755
index 0000000..280438e
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
@@ -0,0 +1,759 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_PWR_H
+#define __STM32L0xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
+#if defined(PWR_PVD_SUPPORT)
+#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
+#endif /* PWR_PVD_SUPPORT */
+#if defined(PWR_CSR_VREFINTRDYF)
+#define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
+#endif /* PWR_CSR_VREFINTRDYF */
+#define LL_PWR_CSR_VOS                     PWR_CSR_VOSF           /*!< Voltage scaling select flag */
+#define LL_PWR_CSR_REGLPF                  PWR_CSR_REGLPF         /*!< Regulator low power flag */
+#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
+#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0)                   /*!< 1.8V (range 1) */
+#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)                   /*!< 1.5V (range 2) */
+#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0 | PWR_CR_VOS_1)    /*!< 1.2V (range 3) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+  * @{
+  */
+#define LL_PWR_MODE_STOP                      0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES  Regulator Mode In Low Power Modes
+  * @{
+  */
+#define LL_PWR_REGU_LPMODES_MAIN           0x00000000U        /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
+#define LL_PWR_REGU_LPMODES_LOW_POWER      (PWR_CR_LPSDSR)    /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
+/**
+  * @}
+  */
+#if defined(PWR_CR_LPDS)
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */
+/**
+  * @}
+  */
+#endif /* PWR_CR_LPDS */
+
+#if defined(PWR_PVD_SUPPORT)
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 1.9 V */
+#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.1 V */
+#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.9 V */
+#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 3.1 V */
+#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< External input analog voltage   (Compare internally to VREFINT) */
+/**
+  * @}
+  */
+#endif /* PWR_PVD_SUPPORT */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
+#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Switch the regulator from main mode to low-power mode
+  * @rmtoll CR    LPRUN       LL_PWR_EnableLowPowerRunMode
+  * @note   Remind to set the regulator to low power before enabling
+  *         LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPRUN);
+}
+
+/**
+  * @brief  Switch the regulator from low-power mode to main mode
+  * @rmtoll CR    LPRUN       LL_PWR_DisableLowPowerRunMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);
+}
+
+/**
+  * @brief  Check if the regulator is in low-power mode
+  * @rmtoll CR    LPRUN       LL_PWR_IsEnabledLowPowerRunMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN));
+}
+
+/**
+  * @brief  Set voltage regulator to low-power and switch from 
+  *         run main mode to run low-power mode.
+  * @rmtoll CR    LPSDSR       LL_PWR_EnterLowPowerRunMode\n
+  *         CR    LPRUN        LL_PWR_EnterLowPowerRunMode
+  * @note   This "high level" function is introduced to provide functional
+  *         compatibility with other families. Notice that the two registers
+  *         have to be written sequentially, so this function is not atomic.
+  *         To assure atomicity you can call separately the following functions:
+  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER);
+  *         - @ref LL_PWR_EnableLowPowerRunMode();
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */
+  SET_BIT(PWR->CR, PWR_CR_LPRUN);  /* => LL_PWR_EnableLowPowerRunMode() */
+}
+
+/**
+  * @brief  Set voltage regulator to main and switch from 
+  *         run main mode to low-power mode.
+  * @rmtoll CR    LPSDSR       LL_PWR_ExitLowPowerRunMode\n
+  *         CR    LPRUN        LL_PWR_ExitLowPowerRunMode
+  * @note   This "high level" function is introduced to provide functional   
+  *         compatibility with other families. Notice that the two registers 
+  *         have to be written sequentially, so this function is not atomic.
+  *         To assure atomicity you can call separately the following functions:
+  *         - @ref LL_PWR_DisableLowPowerRunMode();
+  *         - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN);
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);   /* => LL_PWR_DisableLowPowerRunMode() */
+  CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);  /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
+}
+/**
+  * @brief  Set the main internal regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+
+/**
+  * @brief  Set voltage regulator mode during low power modes
+  * @rmtoll CR    LPSDSR       LL_PWR_SetRegulModeLP
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
+  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode);
+}
+
+/**
+  * @brief  Get voltage regulator mode during low power modes
+  * @rmtoll CR    LPSDSR       LL_PWR_GetRegulModeLP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
+  *         @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR));
+}
+
+#if defined(PWR_CR_LPDS)
+/**
+  * @brief  Set voltage regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get voltage regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+#endif /* PWR_CR_LPDS */
+
+/**
+  * @brief  Set power down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  * @note   Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)  
+  *         before setting MODE_STOP. If the regulator remains in "main mode",   
+  *         it consumes more power without providing any additional feature. 
+  *         In MODE_STANDBY the regulator is automatically off.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode);
+}
+
+/**
+  * @brief  Get power down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+/**
+  * @brief  Enable ultra low-power mode by enabling VREFINT switch off in low-power modes
+  * @rmtoll CR    ULP       LL_PWR_EnableUltraLowPower
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUltraLowPower(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_ULP);
+}
+
+/**
+  * @brief  Disable ultra low-power mode by disabling VREFINT switch off in low-power modes
+  * @rmtoll CR    ULP       LL_PWR_DisableUltraLowPower
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUltraLowPower(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_ULP);
+}
+
+/**
+  * @brief  Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled
+  * @rmtoll CR    ULP       LL_PWR_IsEnabledUltraLowPower
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP));
+}
+
+/**
+  * @brief  Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode
+  * @rmtoll CR    FWU       LL_PWR_EnableFastWakeUp
+  * @note   Works in conjunction with ultra low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFastWakeUp(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FWU);
+}
+
+/**
+  * @brief  Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode
+  * @rmtoll CR    FWU       LL_PWR_DisableFastWakeUp
+  * @note   Works in conjunction with ultra low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFastWakeUp(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FWU);
+}
+
+/**
+  * @brief  Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored
+  * @rmtoll CR    FWU       LL_PWR_IsEnabledFastWakeUp
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
+}
+
+/**
+  * @brief  Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
+  * @rmtoll CR    DS_EE_KOFF       LL_PWR_EnableNVMKeptOff
+  * @note   When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register
+  *         is also set, the Flash memory will not be woken up when exiting from deepsleep mode.
+  *         When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set)
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_DSEEKOFF);
+}
+
+/**
+  * @brief  Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode
+  * @rmtoll CR    DS_EE_KOFF       LL_PWR_DisableNVMKeptOff
+  * @note   When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF);
+}
+
+/**
+  * @brief  Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled
+  * @rmtoll CR    DS_EE_KOFF       LL_PWR_IsEnabledNVMKeptOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Wake-up Flag
+  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+  * @brief  Get Standby Flag
+  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+#if defined(PWR_CSR_VREFINTRDYF)
+/**
+  * @brief  Get Internal Reference VrefInt Flag
+  * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
+}
+#endif /* PWR_CSR_VREFINTRDYF */
+/**
+  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll CSR   VOSF       LL_PWR_IsActiveFlag_VOSF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void)
+{
+  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
+}
+/**
+  * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
+  * @rmtoll CSR   REGLPF       LL_PWR_IsActiveFlag_REGLPF
+  * @note Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
+}
+/**
+  * @brief  Clear Standby Flag
+  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flags
+  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h
new file mode 100755
index 0000000..7add2fb
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h
@@ -0,0 +1,2514 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_RCC_H
+#define __STM32L0xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+  * @{
+  */
+/* Defines used for the bit position in the register and perform offsets*/
+#define RCC_POSITION_HPRE       (uint32_t)4U  /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE1      (uint32_t)8U  /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE2      (uint32_t)11U /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PLLDIV     (uint32_t)22U /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PLLMUL     (uint32_t)18U /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_HSICAL     (uint32_t)0U  /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_HSITRIM    (uint32_t)8U  /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_MSIRANGE   (uint32_t)13U /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_MSICAL     (uint32_t)16U /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_MSITRIM    (uint32_t)24U /*!< field position in register RCC_ICSCR */
+#if defined(RCC_HSI48_SUPPORT)
+#define RCC_POSITION_HSI48CAL   (uint32_t)8U  /*!< field position in register RCC_CRRCR */
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000U)  /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    ((uint32_t)32768U)    /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    ((uint32_t)37000U)    /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+#if defined(RCC_HSI48_SUPPORT)
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+#endif /* RCC_HSI48_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC  /*!< HSI48 Ready Interrupt Clear */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
+#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF  /*!< HSI48 Ready Interrupt flag */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF    /*!< LSE Clock Security System Interrupt flag */
+#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF       /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_FWRSTF                 RCC_CSR_FWRSTF          /*!< Firewall reset flag */
+#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        /*!< Low-Power reset flag */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */
+#if defined(RCC_HSI48_SUPPORT)
+#define LL_RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE   /*!< HSI48 Ready Interrupt Enable */
+#endif /* RCC_HSI48_SUPPORT */
+#define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH               RCC_CSR_LSEDRV   /*!< Xtal mode higher driving capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
+  * @{
+  */
+#define LL_RCC_RTC_HSE_DIV_2               (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC clock  */
+#define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
+#define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
+#define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
+  * @{
+  */
+#define LL_RCC_MSIRANGE_0                  RCC_ICSCR_MSIRANGE_0  /*!< MSI = 65.536 KHz */
+#define LL_RCC_MSIRANGE_1                  RCC_ICSCR_MSIRANGE_1  /*!< MSI = 131.072 KHz*/
+#define LL_RCC_MSIRANGE_2                  RCC_ICSCR_MSIRANGE_2  /*!< MSI = 262.144 KHz */
+#define LL_RCC_MSIRANGE_3                  RCC_ICSCR_MSIRANGE_3  /*!< MSI = 524.288 KHz */
+#define LL_RCC_MSIRANGE_4                  RCC_ICSCR_MSIRANGE_4  /*!< MSI = 1.048 MHz */
+#define LL_RCC_MSIRANGE_5                  RCC_ICSCR_MSIRANGE_5  /*!< MSI = 2.097 MHz */
+#define LL_RCC_MSIRANGE_6                  RCC_ICSCR_MSIRANGE_6  /*!< MSI = 4.194 MHz */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
+  * @{
+  */
+#define LL_RCC_STOP_WAKEUPCLOCK_MSI        ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */
+#define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_MSI          /*!< MSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          /*!< LSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          /*!< LSE selection as MCO source */
+#if defined(RCC_CFGR_MCOSEL_HSI48)
+#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_HSI48        /*!< HSI48 selection as MCO source */
+#endif /* RCC_CFGR_MCOSEL_HSI48 */
+#define LL_RCC_MCO1SOURCE_PLLCLK           RCC_CFGR_MCOSEL_PLL          /*!< PLLCLK selection as MCO source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1  /*!< MCO Clock divided by 1  */
+#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2  /*!< MCO Clock divided by 2  */
+#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4  /*!< MCO Clock divided by 4  */
+#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8  /*!< MCO Clock divided by 8  */
+#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         (uint32_t)0x00000000U      /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         (uint32_t)0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#if defined(RCC_CCIPR_USART1SEL)
+#define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)             /*!< PCLK2 selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)   /*!< SYSCLK selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)   /*!< HSI selected as USART1 clock */
+#define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)     /*!< LSE selected as USART1 clock*/
+#endif /* RCC_CCIPR_USART1SEL */
+#define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)             /*!< PCLK1 selected as USART2 clock */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)   /*!< SYSCLK selected as USART2 clock */
+#define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)   /*!< HSI selected as USART2 clock */
+#define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)     /*!< LSE selected as USART2 clock*/
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     (uint32_t)0x00000000U   /*!< PCLK1 selected as LPUART1 clock */
+#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0  /*!< SYSCLK selected as LPUART1 clock */
+#define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1  /*!< HSI selected as LPUART1 clock */
+#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL    /*!< LSE selected as LPUART1 clock*/
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4U))           /*!< PCLK1 selected as I2C1 clock */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_0 >> 4U))  /*!< SYSCLK selected as I2C1 clock */
+#define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_1 >> 4U))  /*!< HSI selected as I2C1 clock */
+#if defined(RCC_CCIPR_I2C3SEL)
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4U))           /*!< PCLK1 selected as I2C3 clock */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_0 >> 4U))  /*!< SYSCLK selected as I2C3 clock */
+#define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_1 >> 4U))  /*!< HSI selected as I2C3 clock */
+#endif /*RCC_CCIPR_I2C3SEL*/
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (uint32_t)(0x00000000U)          /*!< PCLK1 selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI        (uint32_t)RCC_CCIPR_LPTIM1SEL_0  /*!< LSI selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI        (uint32_t)RCC_CCIPR_LPTIM1SEL_1  /*!< HSI selected as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE        (uint32_t)RCC_CCIPR_LPTIM1SEL    /*!< LSE selected as LPTIM1 clock*/
+/**
+  * @}
+  */
+
+#if defined(RCC_CCIPR_HSI48SEL)
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE_PLL           (uint32_t)(0x00000000U)          /*!< PLL selected as RNG clock */
+#define LL_RCC_RNG_CLKSOURCE_HSI48         (uint32_t)(RCC_CCIPR_HSI48SEL)   /*!< HSI48 selected as RNG clock*/
+/**
+  * @}
+  */
+#endif /* RNG */
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE_PLL           (uint32_t)(0x00000000U)          /*!< PLL selected as USB clock */
+#define LL_RCC_USB_CLKSOURCE_HSI48         (uint32_t)(RCC_CCIPR_HSI48SEL)   /*!< HSI48 selected as USB clock*/
+/**
+  * @}
+  */
+
+#endif /* USB */
+#endif /* RCC_CCIPR_HSI48SEL */
+
+
+/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
+  * @{
+  */
+#if defined(RCC_CCIPR_USART1SEL)
+#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL    /*!< USART1 clock source selection bits */
+#endif /* RCC_CCIPR_USART1SEL */
+#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL    /*!< USART2 clock source selection bits */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL   /*!< LPUART1 clock source selection bits */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL   /*!< I2C1 clock source selection bits */
+#if defined(RCC_CCIPR_I2C3SEL)
+#define LL_RCC_I2C3_CLKSOURCE              RCC_CCIPR_I2C3SEL   /*!< I2C3 clock source selection bits */
+#endif /*RCC_CCIPR_I2C3SEL*/
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL  /*!< LPTIM1 clock source selection bits */
+/**
+  * @}
+  */
+
+#if defined(RCC_CCIPR_HSI48SEL)
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_HSI48SEL   /*!< HSI48 RC clock source selection bit for RNG*/
+/**
+  * @}
+  */
+#endif /* RNG */
+
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_HSI48SEL  /*!< HSI48 RC clock source selection bit for USB*/
+/**
+  * @}
+  */
+
+#endif /* USB */
+#endif /* RCC_CCIPR_HSI48SEL */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)0x00000000U         /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler 
+                                                                             (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
+  * @{
+  */
+#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  /*!< PLL input clock * 3  */
+#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  /*!< PLL input clock * 4  */
+#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  /*!< PLL input clock * 6  */
+#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  /*!< PLL input clock * 8  */
+#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */
+#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */
+#define LL_RCC_PLL_MUL_24                  RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */
+#define LL_RCC_PLL_MUL_32                  RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */
+#define LL_RCC_PLL_MUL_48                  RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor
+  * @{
+  */
+#define LL_RCC_PLL_DIV_2                   RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */
+#define LL_RCC_PLL_DIV_3                   RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */
+#define LL_RCC_PLL_DIV_4                   RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI                           /*!< HSI clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE                           /*!< HSE clock selected as PLL entry clock source */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,
+  *                                      @ref LL_RCC_PLL_GetMultiplicator (),
+  *                                      @ref LL_RCC_PLL_GetDivider ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
+  * @param  __PLLMUL__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_MUL_3
+  *         @arg @ref LL_RCC_PLL_MUL_4
+  *         @arg @ref LL_RCC_PLL_MUL_6
+  *         @arg @ref LL_RCC_PLL_MUL_8
+  *         @arg @ref LL_RCC_PLL_MUL_12
+  *         @arg @ref LL_RCC_PLL_MUL_16
+  *         @arg @ref LL_RCC_PLL_MUL_24
+  *         @arg @ref LL_RCC_PLL_MUL_32
+  *         @arg @ref LL_RCC_PLL_MUL_48
+  * @param  __PLLDIV__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_DIV_2
+  *         @arg @ref LL_RCC_PLL_DIV_3
+  *         @arg @ref LL_RCC_PLL_DIV_4
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__,  __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U))
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
+  *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__: This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE])
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
+  *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__: This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_POSITION_PPRE1])
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
+  *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__: This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_POSITION_PPRE2])
+
+/**
+  * @brief  Helper macro to calculate the MSI frequency (in Hz)
+  * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange
+  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange())
+  * @param  __MSIRANGE__: This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  * @retval MSI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U))))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+#if defined(RCC_HSECSS_SUPPORT)
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+#endif /* RCC_HSECSS_SUPPORT */
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+  * @brief  Configure the RTC prescaler (divider)
+  * @rmtoll CR           RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Div This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div);
+}
+
+/**
+  * @brief  Get the RTC divider (prescaler)
+  * @rmtoll CR           RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+  * @brief  Enable HSI even in stop mode
+  * @note HSI oscillator is forced ON even in Stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI in stop mode
+  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Enable HSI Divider (it divides by 4)
+  * @rmtoll CR           HSIDIVEN       LL_RCC_HSI_EnableDivider
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableDivider(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIDIVEN);
+}
+
+/**
+  * @brief  Disable HSI Divider (it divides by 4)
+  * @rmtoll CR           HSIDIVEN       LL_RCC_HSI_DisableDivider
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableDivider(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN);
+}
+
+
+
+#if defined(RCC_CR_HSIOUTEN)
+/**
+  * @brief  Enable HSI Output
+  * @rmtoll CR           HSIOUTEN       LL_RCC_HSI_EnableOutput
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableOutput(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
+}
+
+/**
+  * @brief  Disable HSI Output
+  * @rmtoll CR           HSIOUTEN       LL_RCC_HSI_DisableOutput
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableOutput(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN);
+}
+#endif /* RCC_CR_HSIOUTEN */
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_HSI48_SUPPORT)
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48
+  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 oscillator Ready
+  * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL);
+}
+
+#if defined(RCC_CRRCR_HSI48DIV6OUTEN)
+/**
+  * @brief  Enable HSI48 Divider (it divides by 6)
+  * @rmtoll CRRCR           HSI48DIV6OUTEN       LL_RCC_HSI48_EnableDivider
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void)
+{
+  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
+}
+
+/**
+  * @brief  Disable HSI48 Divider (it divides by 6)
+  * @rmtoll CRRCR           HSI48DIV6OUTEN       LL_RCC_HSI48_DisableDivider
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void)
+{
+  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN);
+}
+
+/**
+  * @brief  Check if HSI48 Divider is enabled (it divides by 6)
+  * @rmtoll CRRCR        HSI48DIV6OUTEN        LL_RCC_HSI48_IsDivided
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void)
+{
+  return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == (RCC_CRRCR_HSI48DIV6OUTEN));
+}
+
+#endif /*RCC_CRRCR_HSI48DIV6OUTEN*/
+
+/**
+  * @}
+  */
+
+#endif /* RCC_HSI48_SUPPORT */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll CSR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll CSR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll CSR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);
+}
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll CSR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll CSR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV));
+}
+
+/**
+  * @brief  Enable Clock security system on LSE.
+  * @rmtoll CSR         LSECSSON      LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSECSSON);
+}
+
+/**
+  * @brief  Disable Clock security system on LSE.
+  * @note   Clock security system can be disabled only after a LSE
+  *         failure detection. In that case it MUST be disabled by software.
+  * @rmtoll CSR          LSECSSON      LL_RCC_LSE_DisableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll CSR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY));
+}
+
+/**
+  * @brief  Check if CSS on LSE failure Detection
+  * @rmtoll CSR         LSECSSD       LL_RCC_LSE_IsCSSDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MSI MSI
+  * @{
+  */
+
+/**
+  * @brief  Enable MSI oscillator
+  * @rmtoll CR           MSION         LL_RCC_MSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+  * @brief  Disable MSI oscillator
+  * @rmtoll CR           MSION         LL_RCC_MSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_MSION);
+}
+
+/**
+  * @brief  Check if MSI oscillator Ready
+  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
+}
+
+/**
+  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
+  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_SetRange
+  * @param  Range This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
+}
+
+/**
+  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
+  * @rmtoll ICSCR           MSIRANGE      LL_RCC_MSI_GetRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_MSIRANGE_0
+  *         @arg @ref LL_RCC_MSIRANGE_1
+  *         @arg @ref LL_RCC_MSIRANGE_2
+  *         @arg @ref LL_RCC_MSIRANGE_3
+  *         @arg @ref LL_RCC_MSIRANGE_4
+  *         @arg @ref LL_RCC_MSIRANGE_5
+  *         @arg @ref LL_RCC_MSIRANGE_6
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
+}
+
+/**
+  * @brief  Get MSI Calibration value
+  * @note When MSITRIM is written, MSICAL is updated with the sum of
+  *       MSITRIM and the factory trim value
+  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
+}
+
+/**
+  * @brief  Set MSI Calibration trimming
+  * @note user-programmable trimming value that is added to the MSICAL
+  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
+  * @param  Value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
+}
+
+/**
+  * @brief  Get MSI Calibration trimming
+  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @brief  Set Clock After Wake-Up From Stop mode
+  * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
+  * @param  Clock This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
+}
+
+/**
+  * @brief  Get Clock After Wake-Up From Stop mode
+  * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
+  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
+  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
+}
+
+/**
+  * @brief  Configure LPUART1x clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+  MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
+}
+
+#if defined(RCC_CCIPR_HSI48SEL)
+#if defined(RNG)
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll CCIPR        HSI48SEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource);
+}
+#endif /* RNG */
+
+#if defined(USB)
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll CCIPR        HSI48SEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource);
+}
+#endif /* USB */
+
+#endif /* RCC_CCIPR_HSI48SEL */
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
+  * @param  USARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*)
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*)
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
+}
+
+
+
+/**
+  * @brief  Get LPUARTx clock source
+  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
+  * @param  LPUARTx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
+  * @param  I2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1  (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK  (*)
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI   (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+  return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U));
+}
+
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
+}
+
+#if defined(RCC_CCIPR_HSI48SEL)
+#if defined(RNG)
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
+}
+#endif /* RNG */
+
+#if defined(USB)
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
+}
+#endif /* USB */
+
+#endif /* RCC_CCIPR_HSI48SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed any more unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The RTCRST bit can be used to reset them.
+  * @rmtoll CSR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll CSR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll CSR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll CSR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll CSR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN));
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll CSR         RTCRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RTCRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll CSR         RTCRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         CFGR         PLLMUL        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         CFGR         PLLDIV        LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLMul This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_MUL_3
+  *         @arg @ref LL_RCC_PLL_MUL_4
+  *         @arg @ref LL_RCC_PLL_MUL_6
+  *         @arg @ref LL_RCC_PLL_MUL_8
+  *         @arg @ref LL_RCC_PLL_MUL_12
+  *         @arg @ref LL_RCC_PLL_MUL_16
+  *         @arg @ref LL_RCC_PLL_MUL_24
+  *         @arg @ref LL_RCC_PLL_MUL_32
+  *         @arg @ref LL_RCC_PLL_MUL_48
+  * @param  PLLDiv This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_DIV_2
+  *         @arg @ref LL_RCC_PLL_DIV_3
+  *         @arg @ref LL_RCC_PLL_DIV_4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get PLL multiplication Factor
+  * @rmtoll CFGR         PLLMUL        LL_RCC_PLL_GetMultiplicator
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_MUL_3
+  *         @arg @ref LL_RCC_PLL_MUL_4
+  *         @arg @ref LL_RCC_PLL_MUL_6
+  *         @arg @ref LL_RCC_PLL_MUL_8
+  *         @arg @ref LL_RCC_PLL_MUL_12
+  *         @arg @ref LL_RCC_PLL_MUL_16
+  *         @arg @ref LL_RCC_PLL_MUL_24
+  *         @arg @ref LL_RCC_PLL_MUL_32
+  *         @arg @ref LL_RCC_PLL_MUL_48
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
+}
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll CFGR         PLLDIV        LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLL_DIV_2
+  *         @arg @ref LL_RCC_PLL_DIV_3
+  *         @arg @ref LL_RCC_PLL_DIV_4
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear MSI ready interrupt flag
+  * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_HSECSS_SUPPORT)
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
+}
+#endif /* RCC_HSECSS_SUPPORT */
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
+}
+
+/**
+  * @brief  Check if MSI ready interrupt occurred or not
+  * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIFR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+#if defined(RCC_HSECSS_SUPPORT)
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
+}
+#endif /* RCC_HSECSS_SUPPORT */
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
+}
+
+/**
+  * @brief  Check if HSI Divider is enabled (it divides by 4)
+  * @rmtoll CR        HSIDIVF        LL_RCC_IsActiveFlag_HSIDIV
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF));
+}
+
+#if defined(RCC_CSR_FWRSTF)
+/**
+  * @brief  Check if RCC flag FW reset is set or not.
+  * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
+}
+#endif /* RCC_CSR_FWRSTF */
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag is set or not.
+  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Enable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Disable LSE clock security system interrupt
+  * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
+}
+
+/**
+  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
+}
+
+#if defined(RCC_HSI48_SUPPORT)
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
+}
+#endif /* RCC_HSI48_SUPPORT */
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
+{
+  return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RCC */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h
new file mode 100755
index 0000000..e80c51f
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h
@@ -0,0 +1,353 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rng.h
+  * @author  MCD Application Team
+  * @brief   Header file of RNG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_RNG_H
+#define __STM32L0xx_LL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RNG)
+
+/** @defgroup RNG_LL RNG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RNG_ReadReg function
+  * @{
+  */
+#define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
+#define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
+#define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
+#define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
+#define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
+  * @{
+  */
+#define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
+  * @{
+  */
+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Enable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Disable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Disable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Check if Random Number Generator is enabled
+  * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate if the RNG Data ready Flag is set or not
+  * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
+}
+
+/**
+  * @brief  Indicate if the Clock Error Current Status Flag is set or not
+  * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
+}
+
+/**
+  * @brief  Indicate if the Seed Error Current Status Flag is set or not
+  * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
+}
+
+/**
+  * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
+  * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
+}
+
+/**
+  * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
+  * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
+}
+
+/**
+  * @brief  Clear Clock Error interrupt Status (CEIS) Flag
+  * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
+}
+
+/**
+  * @brief  Clear Seed Error interrupt Status (SEIS) Flag
+  * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_EnableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Disable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_DisableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Check if Random Number Generator Interrupt is enabled
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_IsEnabledIT
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+{
+  return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_Data_Management Data Management
+  * @{
+  */
+
+/**
+  * @brief  Return32-bit Random Number value
+  * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
+  * @param  RNGx RNG Instance
+  * @retval Generated 32-bit random value
+  */
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_REG(RNGx->DR));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RNG) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h
new file mode 100755
index 0000000..f5b9b74
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h
@@ -0,0 +1,3860 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rtc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RTC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_RTC_H
+#define __STM32L0xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_INIT_MASK                 ((uint32_t)0xFFFFFFFFU)
+#define RTC_RSF_MASK                  ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
+#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
+#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define RTC_POSITION_TR_HT            (uint32_t)20U
+#define RTC_POSITION_TR_HU            (uint32_t)16U
+#define RTC_POSITION_TR_MT            (uint32_t)12U
+#define RTC_POSITION_TR_MU            (uint32_t)8U
+#define RTC_POSITION_TR_ST            (uint32_t)4U
+#define RTC_POSITION_TR_SU            (uint32_t)0U
+#define RTC_POSITION_DR_YT            (uint32_t)20U
+#define RTC_POSITION_DR_YU            (uint32_t)16U
+#define RTC_POSITION_DR_MT            (uint32_t)12U
+#define RTC_POSITION_DR_MU            (uint32_t)8U
+#define RTC_POSITION_DR_DT            (uint32_t)4U
+#define RTC_POSITION_DR_DU            (uint32_t)0U
+#define RTC_POSITION_DR_WDU           (uint32_t)13U
+#define RTC_POSITION_ALMA_DT          (uint32_t)28U
+#define RTC_POSITION_ALMA_DU          (uint32_t)24U
+#define RTC_POSITION_ALMA_HT          (uint32_t)20U
+#define RTC_POSITION_ALMA_HU          (uint32_t)16U
+#define RTC_POSITION_ALMA_MT          (uint32_t)12U
+#define RTC_POSITION_ALMA_MU          (uint32_t)8U
+#define RTC_POSITION_ALMA_SU          (uint32_t)0U
+#define RTC_POSITION_ALMA_ST          (uint32_t)4U
+#define RTC_POSITION_ALMB_DT          (uint32_t)28U
+#define RTC_POSITION_ALMB_DU          (uint32_t)24U
+#define RTC_POSITION_ALMB_HT          (uint32_t)20U
+#define RTC_POSITION_ALMB_HU          (uint32_t)16U
+#define RTC_POSITION_ALMB_MT          (uint32_t)12U
+#define RTC_POSITION_ALMB_MU          (uint32_t)8U
+#define RTC_POSITION_ALMB_SU          (uint32_t)0U
+#define RTC_POSITION_ALMB_ST          (uint32_t)4U
+#define RTC_POSITION_PRER_PREDIV_A    (uint32_t)16U
+#define RTC_POSITION_ALMA_MASKSS      (uint32_t)24U
+#define RTC_POSITION_ALMB_MASKSS      (uint32_t)24U
+#define RTC_POSITION_TS_HU            (uint32_t)16U
+#define RTC_POSITION_TS_MNU           (uint32_t)8U
+#define RTC_POSITION_TS_WDU           (uint32_t)13U
+#define RTC_POSITION_TS_MU            (uint32_t)8U
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY            (uint32_t)24U
+#define RTC_OFFSET_DAY                (uint32_t)16U
+#define RTC_OFFSET_MONTH              (uint32_t)8U
+#define RTC_OFFSET_HOUR               (uint32_t)16U
+#define RTC_OFFSET_MINUTE             (uint32_t)8U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  RTC Init structures definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
+                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetHourFormat(). */
+
+  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetAsynchPrescaler(). */
+
+  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+                              
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
+
+  uint8_t Hours;       /*!< Specifies the RTC Time Hours.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
+
+  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
+
+  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month.
+                         This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
+
+  uint8_t Day;      /*!< Specifies the RTC Date Day.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A 
+                                      or @ref LL_RTC_ALMB_SetMask() for ALARM B
+                                 */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+                                      for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+                                 */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
+                                      If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+                                      for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
+
+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+                                      for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+                                 */
+} LL_RTC_AlarmTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+  * @{
+  */
+#define LL_RTC_FORMAT_BIN                  ((uint32_t)0x000000000U) /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD                  ((uint32_t)0x000000001U) /*!< BCD data format */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RTC_ReadReg function
+  * @{
+  */
+#define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
+#define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
+#define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F
+#define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F
+#define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF
+#define LL_RTC_ISR_TSF                     RTC_ISR_TSF
+#define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF
+#define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF
+#define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF
+#define LL_RTC_ISR_INITF                   RTC_ISR_INITF
+#define LL_RTC_ISR_RSF                     RTC_ISR_RSF
+#define LL_RTC_ISR_INITS                   RTC_ISR_INITS
+#define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF
+#define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
+#define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
+#define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
+  * @{
+  */
+#define LL_RTC_CR_TSIE                     RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
+#define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
+#define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
+#define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
+#define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
+  * @{
+  */
+#define LL_RTC_WEEKDAY_MONDAY              ((uint8_t)0x01U) /*!< Monday    */
+#define LL_RTC_WEEKDAY_TUESDAY             ((uint8_t)0x02U) /*!< Tuesday   */
+#define LL_RTC_WEEKDAY_WEDNESDAY           ((uint8_t)0x03U) /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY            ((uint8_t)0x04U) /*!< Thrusday  */
+#define LL_RTC_WEEKDAY_FRIDAY              ((uint8_t)0x05U) /*!< Friday    */
+#define LL_RTC_WEEKDAY_SATURDAY            ((uint8_t)0x06U) /*!< Saturday  */
+#define LL_RTC_WEEKDAY_SUNDAY              ((uint8_t)0x07U) /*!< Sunday    */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_MONTH  MONTH
+  * @{
+  */
+#define LL_RTC_MONTH_JANUARY               ((uint8_t)0x01U)  /*!< January   */
+#define LL_RTC_MONTH_FEBRUARY              ((uint8_t)0x02U)  /*!< February  */
+#define LL_RTC_MONTH_MARCH                 ((uint8_t)0x03U)  /*!< March     */
+#define LL_RTC_MONTH_APRIL                 ((uint8_t)0x04U)  /*!< April     */
+#define LL_RTC_MONTH_MAY                   ((uint8_t)0x05U)  /*!< May       */
+#define LL_RTC_MONTH_JUNE                  ((uint8_t)0x06U)  /*!< June      */
+#define LL_RTC_MONTH_JULY                  ((uint8_t)0x07U)  /*!< July      */
+#define LL_RTC_MONTH_AUGUST                ((uint8_t)0x08U)  /*!< August    */
+#define LL_RTC_MONTH_SEPTEMBER             ((uint8_t)0x09U)  /*!< September */
+#define LL_RTC_MONTH_OCTOBER               ((uint8_t)0x10U)  /*!< October   */
+#define LL_RTC_MONTH_NOVEMBER              ((uint8_t)0x11U)  /*!< November  */
+#define LL_RTC_MONTH_DECEMBER              ((uint8_t)0x12U)  /*!< December  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
+  * @{
+  */
+#define LL_RTC_HOURFORMAT_24HOUR           (uint32_t)0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
+  * @{
+  */
+#define LL_RTC_ALARMOUT_DISABLE            ((uint32_t)0x00000000U) /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
+  * @{
+  */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  (uint32_t)0x00000000U  /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
+  * @{
+  */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TIME_FORMAT_AM_OR_24        (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
+  * @{
+  */
+#define LL_RTC_SHIFT_SECOND_DELAY          (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
+  * @{
+  */
+#define LL_RTC_ALMA_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMA_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
+  * @{
+  */
+#define LL_RTC_ALMB_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMB_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
+  * @{
+  */
+#define LL_RTC_TIMESTAMP_EDGE_RISING       (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TS_TIME_FORMAT_AM           (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER  TAMPER
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+#if defined(RTC_TAMPCR_TAMPPRCH)
+/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
+  * @{
+  */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK     ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPPRCH */
+
+#if defined(RTC_TAMPCR_TAMPFLT)
+/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
+  * @{
+  */
+#define LL_RTC_TAMPER_FILTER_DISABLE       ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPFLT */
+
+#if defined(RTC_TAMPCR_TAMPFREQ)
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
+  * @{
+  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   ((uint32_t)0x00000000U)                          /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */
+/**
+  * @}
+  */
+#endif /* RTC_TAMPCR_TAMPFREQ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
+  * @{
+  */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
+  * @{
+  */
+#define LL_RTC_WAKEUPCLOCK_DIV_16          ((uint32_t)0x00000000U)               /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE          (RTC_CR_WUCKSEL_2)                    /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+  * @}
+  */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EC_BKP  BACKUP
+  * @{
+  */
+#define LL_RTC_BKP_DR0                     ((uint32_t)0x00000000U)
+#define LL_RTC_BKP_DR1                     ((uint32_t)0x00000001U)
+#define LL_RTC_BKP_DR2                     ((uint32_t)0x00000002U)
+#define LL_RTC_BKP_DR3                     ((uint32_t)0x00000003U)
+#define LL_RTC_BKP_DR4                     ((uint32_t)0x00000004U)
+/**
+  * @}
+  */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
+  * @{
+  */
+#define LL_RTC_CALIB_OUTPUT_NONE           (uint32_t)0x00000000U       /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion 
+  * @{
+  */
+#define LL_RTC_CALIB_INSERTPULSE_NONE      (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
+  * @{
+  */
+#define LL_RTC_CALIB_PERIOD_32SEC          (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
+  * @param  __VALUE__ Byte to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
+  * @param  __VALUE__ BCD value to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve weekday.
+  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Year in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Year in BCD format (0x00 . . . 0x99)
+  */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Month in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Day in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Day in BCD format (0x01 . . . 0x31)
+  */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve hour in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+  */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve minute in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Minutes in BCD format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve second in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Seconds in  format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+  * @{
+  */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set Hours format (24 hour/day or AM/PM hour format)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           FMT           LL_RTC_SetHourFormat
+  * @param  RTCx RTC Instance
+  * @param  HourFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+  * @brief  Get Hours format (24 hour/day or AM/PM hour format)
+  * @rmtoll CR           FMT           LL_RTC_GetHourFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+  * @brief  Select the flag to be routed to RTC_ALARM output
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           OSEL          LL_RTC_SetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @param  AlarmOutput This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+  * @brief  Get the flag to be routed to RTC_ALARM output
+  * @rmtoll CR           OSEL          LL_RTC_GetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @note   Used only when RTC_ALARM is mapped on PC13
+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+  MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
+}
+
+/**
+  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @note   used only when RTC_ALARM is mapped on PC13
+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
+}
+
+/**
+  * @brief  Enable initialization mode
+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+  *         and prescaler register (RTC_PRER).
+  *         Counters are stopped and start counting from the new value when INIT is reset.
+  * @rmtoll ISR          INIT          LL_RTC_EnableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Set the Initialization mode */
+  WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
+}
+
+/**
+  * @brief  Disable initialization mode (Free running mode)
+  * @rmtoll ISR          INIT          LL_RTC_DisableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Exit Initialization mode */
+  WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
+}
+
+/**
+  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           POL           LL_RTC_SetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+  * @brief  Get Output polarity
+  * @rmtoll CR           POL           LL_RTC_GetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+  * @brief  Enable Bypass the shadow registers
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Disable Bypass the shadow registers
+  * @rmtoll CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Check if Shadow registers bypass is enabled or not.
+  * @rmtoll CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+}
+
+/**
+  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           REFCKON       LL_RTC_EnableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll CR           REFCKON       LL_RTC_DisableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Set Asynchronous prescaler factor
+  * @rmtoll PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A);
+}
+
+/**
+  * @brief  Set Synchronous prescaler factor
+  * @rmtoll PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+  * @brief  Get Asynchronous prescaler factor
+  * @rmtoll PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A);
+}
+
+/**
+  * @brief  Get Synchronous prescaler factor
+  * @rmtoll PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @rmtoll WPR          KEY           LL_RTC_EnableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @rmtoll WPR          KEY           LL_RTC_DisableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+  * @brief  Enable RTC_OUT remap
+  * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
+}
+
+/**
+  * @brief  Disable RTC_OUT remap
+  * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Time Time
+  * @{
+  */
+
+/**
+  * @brief  Set time format (AM/24-hour or PM notation)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll TR           PM            LL_RTC_TIME_SetFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get time format (AM or PM notation)
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @rmtoll TR           PM            LL_RTC_TIME_GetFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+  * @brief  Set Hours in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+  * @rmtoll TR           HT            LL_RTC_TIME_SetHour\n
+  *         TR           HU            LL_RTC_TIME_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+             (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)));
+}
+
+/**
+  * @brief  Get Hours in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+  *       Binary format
+  * @rmtoll TR           HT            LL_RTC_TIME_GetHour\n
+  *         TR           HU            LL_RTC_TIME_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
+  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU));
+}
+
+/**
+  * @brief  Set Minutes in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll TR           MNT           LL_RTC_TIME_SetMinute\n
+  *         TR           MNU           LL_RTC_TIME_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+             (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)));
+}
+
+/**
+  * @brief  Get Minutes in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+  *       to Binary format
+  * @rmtoll TR           MNT           LL_RTC_TIME_GetMinute\n
+  *         TR           MNU           LL_RTC_TIME_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
+  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU));
+}
+
+/**
+  * @brief  Set Seconds in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll TR           ST            LL_RTC_TIME_SetSecond\n
+  *         TR           SU            LL_RTC_TIME_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+             (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)));
+}
+
+/**
+  * @brief  Get Seconds in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+  *       to Binary format
+  * @rmtoll TR           ST            LL_RTC_TIME_GetSecond\n
+  *         TR           SU            LL_RTC_TIME_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
+  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU));
+}
+
+/**
+  * @brief  Set time (hour, minute and second) in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note TimeFormat and Hours should follow the same format
+  * @rmtoll TR           PM            LL_RTC_TIME_Config\n
+  *         TR           HT            LL_RTC_TIME_Config\n
+  *         TR           HU            LL_RTC_TIME_Config\n
+  *         TR           MNT           LL_RTC_TIME_Config\n
+  *         TR           MNU           LL_RTC_TIME_Config\n
+  *         TR           ST            LL_RTC_TIME_Config\n
+  *         TR           SU            LL_RTC_TIME_Config
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24                                                                                    | \
+         (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))     | \
+         (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \
+         (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU));
+  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+  * @brief  Get time (hour, minute and second) in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  *       are available to get independently each parameter.
+  * @rmtoll TR           HT            LL_RTC_TIME_Get\n
+  *         TR           HU            LL_RTC_TIME_Get\n
+  *         TR           MNT           LL_RTC_TIME_Get\n
+  *         TR           MNU           LL_RTC_TIME_Get\n
+  *         TR           ST            LL_RTC_TIME_Get\n
+  *         TR           SU            LL_RTC_TIME_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Memorize whether the daylight saving time change has been performed
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BCK           LL_RTC_TIME_EnableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BCK);
+}
+
+/**
+  * @brief  Disable memorization whether the daylight saving time change has been performed.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           BCK           LL_RTC_TIME_DisableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BCK);
+}
+
+/**
+  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
+  * @rmtoll CR           BCK           LL_RTC_TIME_IsDayLightStoreEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK));
+}
+
+/**
+  * @brief  Subtract 1 hour (winter time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           SUB1H         LL_RTC_TIME_DecHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+  * @brief  Add 1 hour (summer time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ADD1H         LL_RTC_TIME_IncHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+  * @brief  Get Sub second value in the synchronous prescaler counter.
+  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
+  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+  *        SubSeconds value in second fraction ratio with time unit following
+  *        generic formula:
+  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+  *        This conversion can be performed only if no shift operation is pending
+  *        (ie. SHFP=0) when PREDIV_S >= SS.
+  * @rmtoll SSR          SS            LL_RTC_TIME_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Sub second value (number between 0 and 65535)
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+  * @brief  Synchronize to a remote clock with a high degree of precision.
+  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   When REFCKON is set, firmware must not write to Shift control register.
+  * @rmtoll SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
+  *         SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
+  * @param  RTCx RTC Instance
+  * @param  ShiftSecond This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Date Date
+  * @{
+  */
+
+/**
+  * @brief  Set Year in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+  * @rmtoll DR           YT            LL_RTC_DATE_SetYear\n
+  *         DR           YU            LL_RTC_DATE_SetYear
+  * @param  RTCx RTC Instance
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+             (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)));
+}
+
+/**
+  * @brief  Get Year in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+  * @rmtoll DR           YT            LL_RTC_DATE_GetYear\n
+  *         DR           YU            LL_RTC_DATE_GetYear
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x99
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU));
+}
+
+/**
+  * @brief  Set Week day
+  * @rmtoll DR           WDU           LL_RTC_DATE_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU);
+}
+
+/**
+  * @brief  Get Week day
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @rmtoll DR           WDU           LL_RTC_DATE_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU);
+}
+
+/**
+  * @brief  Set Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+  * @rmtoll DR           MT            LL_RTC_DATE_SetMonth\n
+  *         DR           MU            LL_RTC_DATE_SetMonth
+  * @param  RTCx RTC Instance
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+             (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)));
+}
+
+/**
+  * @brief  Get Month in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll DR           MT            LL_RTC_DATE_GetMonth\n
+  *         DR           MU            LL_RTC_DATE_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
+  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU));
+}
+
+/**
+  * @brief  Set Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll DR           DT            LL_RTC_DATE_SetDay\n
+  *         DR           DU            LL_RTC_DATE_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+             (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)));
+}
+
+/**
+  * @brief  Get Day in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll DR           DT            LL_RTC_DATE_GetDay\n
+  *         DR           DU            LL_RTC_DATE_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
+  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU));
+}
+
+/**
+  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
+  * @rmtoll DR           WDU           LL_RTC_DATE_Config\n
+  *         DR           MT            LL_RTC_DATE_Config\n
+  *         DR           MU            LL_RTC_DATE_Config\n
+  *         DR           DT            LL_RTC_DATE_Config\n
+  *         DR           DU            LL_RTC_DATE_Config\n
+  *         DR           YT            LL_RTC_DATE_Config\n
+  *         DR           YU            LL_RTC_DATE_Config
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
+{
+  register uint32_t temp = 0U;
+
+  temp = (WeekDay << RTC_POSITION_DR_WDU)                                                        | \
+         (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))   | \
+         (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \
+         (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU));
+
+  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll DR           WDU           LL_RTC_DATE_Get\n
+  *         DR           MT            LL_RTC_DATE_Get\n
+  *         DR           MU            LL_RTC_DATE_Get\n
+  *         DR           DT            LL_RTC_DATE_Get\n
+  *         DR           DU            LL_RTC_DATE_Get\n
+  *         DR           YT            LL_RTC_DATE_Get\n
+  *         DR           YU            LL_RTC_DATE_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Disable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAE         LL_RTC_ALMA_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Specify the Alarm A masks.
+  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
+  *         ALRMAR       MSK1          LL_RTC_ALMA_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm A masks.
+  * @rmtoll ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
+  *         ALRMAR       MSK1          LL_RTC_ALMA_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
+  * @rmtoll ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_SetDay\n
+  *         ALRMAR       DU            LL_RTC_ALMA_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+             (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU)));
+}
+
+/**
+  * @brief  Get ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll ALRMAR       DT            LL_RTC_ALMA_GetDay\n
+  *         ALRMAR       DU            LL_RTC_ALMA_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
+  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU));
+}
+
+/**
+  * @brief  Set ALARM A Weekday
+  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU);
+}
+
+/**
+  * @brief  Get ALARM A Weekday
+  * @rmtoll ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU);
+}
+
+/**
+  * @brief  Set Alarm A time format (AM/24-hour or PM notation)
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get Alarm A time format (AM or PM notation)
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+  * @brief  Set ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_SetHour\n
+  *         ALRMAR       HU            LL_RTC_ALMA_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+             (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)));
+}
+
+/**
+  * @brief  Get ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetHour\n
+  *         ALRMAR       HU            LL_RTC_ALMA_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
+  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU));
+}
+
+/**
+  * @brief  Set ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+             (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)));
+}
+
+/**
+  * @brief  Get ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
+  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU));
+}
+
+/**
+  * @brief  Set ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
+  *         ALRMAR       SU            LL_RTC_ALMA_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+             (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)));
+}
+
+/**
+  * @brief  Get ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
+  *         ALRMAR       SU            LL_RTC_ALMA_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU));
+}
+
+/**
+  * @brief  Set Alarm A Time (hour, minute and second) in BCD format
+  * @rmtoll ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
+  *         ALRMAR       SU            LL_RTC_ALMA_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))    | \
+         (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \
+         (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU));
+
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll ALRMAR       HT            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       HU            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       ST            LL_RTC_ALMA_GetTime\n
+  *         ALRMAR       SU            LL_RTC_ALMA_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm A Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRAE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS);
+}
+
+/**
+  * @brief  Get Alarm A Mask the most-significant bits starting at this bit
+  * @rmtoll ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS);
+}
+
+/**
+  * @brief  Set Alarm A Sub seconds value
+  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm A Sub seconds value
+  * @rmtoll ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Disable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBE         LL_RTC_ALMB_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Specify the Alarm B masks.
+  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
+  *         ALRMBR       MSK1          LL_RTC_ALMB_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm B masks.
+  * @rmtoll ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
+  *         ALRMBR       MSK1          LL_RTC_ALMB_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
+  * @rmtoll ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_SetDay\n
+  *         ALRMBR       DU            LL_RTC_ALMB_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+             (((Day & 0xF0U) << (RTC_POSITION_ALMB_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMB_DU)));
+}
+
+/**
+  * @brief  Get ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll ALRMBR       DT            LL_RTC_ALMB_GetDay\n
+  *         ALRMBR       DU            LL_RTC_ALMB_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
+  return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_POSITION_ALMB_DT) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU));
+}
+
+/**
+  * @brief  Set ALARM B Weekday
+  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_POSITION_ALMB_DU);
+}
+
+/**
+  * @brief  Get ALARM B Weekday
+  * @rmtoll ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU);
+}
+
+/**
+  * @brief  Set ALARM B time format (AM/24-hour or PM notation)
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get ALARM B time format (AM or PM notation)
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+  * @brief  Set ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_SetHour\n
+  *         ALRMBR       HU            LL_RTC_ALMB_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+             (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU)));
+}
+
+/**
+  * @brief  Get ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetHour\n
+  *         ALRMBR       HU            LL_RTC_ALMB_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
+  return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_POSITION_ALMB_HT) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_POSITION_ALMB_HU));
+}
+
+/**
+  * @brief  Set ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+             (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)));
+}
+
+/**
+  * @brief  Get ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
+  return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_POSITION_ALMB_MT) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_POSITION_ALMB_MU));
+}
+
+/**
+  * @brief  Set ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
+  *         ALRMBR       SU            LL_RTC_ALMB_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+             (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU)));
+}
+
+/**
+  * @brief  Get ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
+  *         ALRMBR       SU            LL_RTC_ALMB_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+  register uint32_t temp = 0U;
+
+  temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
+  return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_POSITION_ALMB_ST) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_POSITION_ALMB_SU));
+}
+
+/**
+  * @brief  Set Alarm B Time (hour, minute and second) in BCD format
+  * @rmtoll ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
+  *         ALRMBR       SU            LL_RTC_ALMB_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+  register uint32_t temp = 0U;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU))    | \
+         (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)) | \
+         (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU));
+
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll ALRMBR       HT            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       HU            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       ST            LL_RTC_ALMB_GetTime\n
+  *         ALRMBR       SU            LL_RTC_ALMB_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm B Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRBE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_POSITION_ALMB_MASKSS);
+}
+
+/**
+  * @brief  Get Alarm B Mask the most-significant bits starting at this bit
+  * @rmtoll ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_POSITION_ALMB_MASKSS);
+}
+
+/**
+  * @brief  Set Alarm B Sub seconds value
+  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm B Sub seconds value
+  * @rmtoll ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+  * @{
+  */
+
+/**
+  * @brief  Enable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSE           LL_RTC_TS_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Disable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSE           LL_RTC_TS_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Set Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+  * @rmtoll CR           TSEDGE        LL_RTC_TS_SetActiveEdge
+  * @param  RTCx RTC Instance
+  * @param  Edge This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+  * @brief  Get Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSEDGE        LL_RTC_TS_GetActiveEdge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
+  * @rmtoll TSTR         PM            LL_RTC_TS_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+  * @brief  Get Timestamp Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll TSTR         HT            LL_RTC_TS_GetHour\n
+  *         TSTR         HU            LL_RTC_TS_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU);
+}
+
+/**
+  * @brief  Get Timestamp Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll TSTR         MNT           LL_RTC_TS_GetMinute\n
+  *         TSTR         MNU           LL_RTC_TS_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU);
+}
+
+/**
+  * @brief  Get Timestamp Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll TSTR         ST            LL_RTC_TS_GetSecond\n
+  *         TSTR         SU            LL_RTC_TS_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll TSTR         HT            LL_RTC_TS_GetTime\n
+  *         TSTR         HU            LL_RTC_TS_GetTime\n
+  *         TSTR         MNT           LL_RTC_TS_GetTime\n
+  *         TSTR         MNU           LL_RTC_TS_GetTime\n
+  *         TSTR         ST            LL_RTC_TS_GetTime\n
+  *         TSTR         SU            LL_RTC_TS_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR,
+                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp Week day
+  * @rmtoll TSDR         WDU           LL_RTC_TS_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU);
+}
+
+/**
+  * @brief  Get Timestamp Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll TSDR         MT            LL_RTC_TS_GetMonth\n
+  *         TSDR         MU            LL_RTC_TS_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU);
+}
+
+/**
+  * @brief  Get Timestamp Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll TSDR         DT            LL_RTC_TS_GetDay\n
+  *         TSDR         DU            LL_RTC_TS_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll TSDR         WDU           LL_RTC_TS_GetDate\n
+  *         TSDR         MT            LL_RTC_TS_GetDate\n
+  *         TSDR         MU            LL_RTC_TS_GetDate\n
+  *         TSDR         DT            LL_RTC_TS_GetDate\n
+  *         TSDR         DU            LL_RTC_TS_GetDate
+  * @param  RTCx RTC Instance
+  * @retval Combination of Weekday, Day and Month
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get time-stamp sub second value
+  * @rmtoll TSSSR        SS            LL_RTC_TS_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+#if defined(RTC_TAMPCR_TAMPTS)
+/**
+  * @brief  Activate timestamp on tamper detection event
+  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_EnableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
+}
+
+/**
+  * @brief  Disable timestamp on tamper detection event
+  * @rmtoll TAMPCR       TAMPTS        LL_RTC_TS_DisableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
+}
+#endif /* RTC_TAMPCR_TAMPTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+  * @{
+  */
+
+/**
+  * @brief  Enable RTC_TAMPx input detection
+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable\n
+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable\n
+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_1 (*)
+  *         @arg @ref LL_RTC_TAMPER_2 
+  *         @arg @ref LL_RTC_TAMPER_3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Clear RTC_TAMPx input detection
+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable\n
+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable\n
+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_1 (*)
+  *         @arg @ref LL_RTC_TAMPER_2 
+  *         @arg @ref LL_RTC_TAMPER_3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Enable Tamper mask flag
+  * @note Associated Tamper IT must not enabled when tamper mask is set.
+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask\n
+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*)
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  SET_BIT(RTCx->TAMPCR, Mask);
+}
+
+/**
+  * @brief  Disable Tamper mask flag
+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask\n
+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 (*)
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Mask);
+}
+
+/**
+  * @brief  Enable backup register erase after Tamper event detection
+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP\n
+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Disable backup register erase after Tamper event detection
+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP\n
+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 (*)
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 
+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+#if defined(RTC_TAMPCR_TAMPPUDIS)
+/**
+  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
+}
+
+/**
+  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
+}
+#endif /* RTC_TAMPCR_TAMPPUDIS */
+
+#if defined(RTC_TAMPCR_TAMPPRCH)
+/**
+  * @brief  Set RTC_TAMPx precharge duration
+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
+  * @param  RTCx RTC Instance
+  * @param  Duration This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
+}
+
+/**
+  * @brief  Get RTC_TAMPx precharge duration
+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
+}
+#endif /* RTC_TAMPCR_TAMPPRCH */
+
+#if defined(RTC_TAMPCR_TAMPFLT)
+/**
+  * @brief  Set RTC_TAMPx filter count
+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
+  * @param  RTCx RTC Instance
+  * @param  FilterCount This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
+}
+
+/**
+  * @brief  Get RTC_TAMPx filter count
+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
+}
+#endif /* RTC_TAMPCR_TAMPFLT */
+
+#if defined(RTC_TAMPCR_TAMPFREQ)
+/**
+  * @brief  Set Tamper sampling frequency
+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @param  SamplingFreq This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+  * @brief  Get Tamper sampling frequency
+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
+}
+#endif /* RTC_TAMPCR_TAMPFREQ */
+
+/**
+  * @brief  Enable Active level for Tamper input
+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 (*)
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  SET_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @brief  Disable Active level for Tamper input
+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 (*)
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 
+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  CLEAR_BIT(RTCx->TAMPCR, Tamper);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+  * @{
+  */
+
+/**
+  * @brief  Enable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Disable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Check if Wakeup timer is enabled or not
+  * @rmtoll CR           WUTE          LL_RTC_WAKEUP_IsEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+}
+
+/**
+  * @brief  Select Wakeup clock
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
+  * @param  RTCx RTC Instance
+  * @param  WakeupClock This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+  * @brief  Get Wakeup clock
+  * @rmtoll CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+  * @brief  Set Wakeup auto-reload value
+  * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
+  * @param  RTCx RTC Instance
+  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+  * @brief  Get Wakeup auto-reload value
+  * @rmtoll WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+  * @}
+  */
+#endif /* RTC_WAKEUP_SUPPORT */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+  register uint32_t tmp = 0U;
+
+  tmp = (uint32_t)(&(RTCx->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+  register uint32_t tmp = 0U;
+
+  tmp = (uint32_t)(&(RTCx->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+  * @{
+  */
+
+/**
+  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
+  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           COE           LL_RTC_CAL_SetOutputFreq\n
+  *         CR           COSEL         LL_RTC_CAL_SetOutputFreq
+  * @param  RTCx RTC Instance
+  * @param  Frequency This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
+  * @rmtoll CR           COE           LL_RTC_CAL_GetOutputFreq\n
+  *         CR           COSEL         LL_RTC_CAL_GetOutputFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALP          LL_RTC_CAL_SetPulse
+  * @param  RTCx RTC Instance
+  * @param  Pulse This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @rmtoll CALR         CALP          LL_RTC_CAL_IsPulseInserted
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+}
+
+/**
+  * @brief  Set the calibration cycle period
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALW8         LL_RTC_CAL_SetPeriod\n
+  *         CALR         CALW16        LL_RTC_CAL_SetPeriod
+  * @param  RTCx RTC Instance
+  * @param  Period This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+  * @brief  Get the calibration cycle period
+  * @rmtoll CALR         CALW8         LL_RTC_CAL_GetPeriod\n
+  *         CALR         CALW16        LL_RTC_CAL_GetPeriod
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+  * @brief  Set Calibration minus
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR
+  * @rmtoll CALR         CALM          LL_RTC_CAL_SetMinus
+  * @param  RTCx RTC Instance
+  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+  * @brief  Get Calibration minus
+  * @rmtoll CALR         CALM          LL_RTC_CAL_GetMinus
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Recalibration pending Flag
+  * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP3 detection flag
+  * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP2 detection flag
+  * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Get RTC_TAMP1 detection flag
+  * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Get Time-stamp overflow flag
+  * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+}
+
+/**
+  * @brief  Get Time-stamp flag
+  * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Get Wakeup timer flag
+  * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Get Alarm B flag
+  * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+}
+
+/**
+  * @brief  Get Alarm A flag
+  * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP3 detection flag
+  * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP2 detection flag
+  * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Clear RTC_TAMP1 detection flag
+  * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Clear Time-stamp overflow flag
+  * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Clear Time-stamp flag
+  * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Clear Wakeup timer flag
+  * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Clear Alarm B flag
+  * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Clear Alarm A flag
+  * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Get Initialization flag
+  * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+}
+
+/**
+  * @brief  Get Registers synchronization flag
+  * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+}
+
+/**
+  * @brief  Clear Registers synchronization flag
+  * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+  * @brief  Get Initialization status flag
+  * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+}
+
+/**
+  * @brief  Get Shift operation pending flag
+  * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Get Wakeup timer write flag
+  * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Get Alarm B write flag
+  * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+}
+
+/**
+  * @brief  Get Alarm A write flag
+  * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSIE          LL_RTC_EnableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+  * @brief  Disable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           TSIE          LL_RTC_DisableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Enable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTIE         LL_RTC_EnableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+  * @brief  Disable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           WUTIE         LL_RTC_DisableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Enable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBIE        LL_RTC_EnableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Disable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRBIE        LL_RTC_DisableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Enable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAIE        LL_RTC_EnableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+  * @brief  Disable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll CR           ALRAIE        LL_RTC_DisableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Enable Tamper 3 interrupt
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
+}
+
+/**
+  * @brief  Disable Tamper 3 interrupt
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Enable Tamper 2 interrupt
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
+}
+
+/**
+  * @brief  Disable Tamper 2 interrupt
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Enable Tamper 1 interrupt
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
+}
+
+/**
+  * @brief  Disable Tamper 1 interrupt
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Enable all Tamper Interrupt
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
+}
+
+/**
+  * @brief  Disable all Tamper Interrupt
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
+}
+
+/**
+  * @brief  Check if  Time-stamp interrupt is enabled or not
+  * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+  * @brief  Check if  Wakeup timer interrupt is enabled or not
+  * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+  * @brief  Check if  Alarm B interrupt is enabled or not
+  * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+}
+
+/**
+  * @brief  Check if  Alarm A interrupt is enabled or not
+  * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+  * @brief  Check if  Tamper 3 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+  * @brief  Check if  Tamper 2 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE));
+#endif /* RTC_TAMPER2_SUPPORT */
+}
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+  * @brief  Check if  Tamper 1 interrupt is enabled or not
+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+  * @brief  Check if all the TAMPER interrupts are enabled or not
+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
+{
+  return (READ_BIT(RTCx->TAMPCR,
+                   RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h
new file mode 100755
index 0000000..f4c79a3
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h
@@ -0,0 +1,2036 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_spi.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_SPI_H
+#define __STM32L0xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2)
+
+/** @defgroup SPI_LL SPI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structures definition
+  */
+typedef struct
+{
+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+  uint32_t DataWidth;               /*!< Specifies the SPI data width.
+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+  * @{
+  */
+#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
+#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
+#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
+#define LL_SPI_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
+#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
+#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
+#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
+#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
+#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
+#define LL_SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)         /*!< Slave configuration   */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+  * @{
+  */
+#define LL_SPI_PROTOCOL_MOTOROLA           ((uint32_t)0x00000000U)   /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)   /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_SPI_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+  * @{
+  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      ((uint32_t)0x00000000U)                        /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+  * @{
+  */
+#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST                   ((uint32_t)0x00000000U)   /*!< Data is transmitted/received with the MSB first */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_SPI_FULL_DUPLEX                 ((uint32_t)0x00000000U)              /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
+#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
+#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+  * @{
+  */
+#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
+#define LL_SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)           /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_SPI_DATAWIDTH_8BIT              ((uint32_t)0x00000000U)           /*!< Data length for SPI transfer:  8 bits */
+#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+  * @{
+  */
+#define LL_SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)           /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)                   /*!< CRC calculation enabled  */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable SPI peripheral
+  * @rmtoll CR1          SPE           LL_SPI_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable SPI peripheral
+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+  * @rmtoll CR1          SPE           LL_SPI_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Check if SPI peripheral is enabled
+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+  * @brief  Set SPI operation mode to Master or Slave
+  * @note   This bit should not be changed when communication is ongoing.
+  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
+  *         CR1          SSI           LL_SPI_SetMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+  * @brief  Get SPI operation mode (Master or Slave)
+  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
+  *         CR1          SSI           LL_SPI_GetMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+  * @brief  Set serial protocol used
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR2          FRF           LL_SPI_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+  * @brief  Get serial protocol used
+  * @rmtoll CR2          FRF           LL_SPI_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+  * @brief  Set clock phase
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
+  * @param  SPIx SPI Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Get clock phase
+  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+  * @brief  Set clock polarity
+  * @note   This bit should not be changed when communication is ongoing.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get clock polarity
+  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+  * @brief  Set baud rate prescaler
+  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @param  BaudRate This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+  * @brief  Get baud rate prescaler
+  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+  * @brief  Set transfer bit order
+  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Get transfer bit order
+  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+  * @brief  Set transfer direction mode
+  * @note   For Half-Duplex mode, Rx Direction is set by default.
+  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
+  * @param  SPIx SPI Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+  * @brief  Get transfer direction mode
+  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
+  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+  * @brief  Set frame data width
+  * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
+  * @param  SPIx SPI Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
+}
+
+/**
+  * @brief  Get frame data width
+  * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+  * @{
+  */
+
+/**
+  * @brief  Enable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Disable CRC
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+  * @brief  Check if CRC is enabled
+  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+  * @brief  Set CRCNext to transfer CRC on the line
+  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
+  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+  * @brief  Set polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+  * @brief  Get polynomial for CRC calculation
+  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+  * @brief  Get Rx CRC
+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+  * @brief  Get Tx CRC
+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+  * @param  SPIx SPI Instance
+  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+  * @{
+  */
+
+/**
+  * @brief  Set NSS mode
+  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
+  * @param  SPIx SPI Instance
+  * @param  NSS This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
+  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+  * @brief  Get NSS mode
+  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
+  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+  register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+  register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
+  return (Ssm | Ssoe);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+  * @brief  Get CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+  * @brief  Get mode fault error flag
+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+  * @brief  Get busy flag
+  * @note   The BSY flag is cleared under any one of the following conditions:
+  * -When the SPI is correctly disabled
+  * -When a fault is detected in Master mode (MODF bit set to 1)
+  * -In Master mode, when it finishes a data transmission and no new data is ready to be
+  * sent
+  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+  * each data transfer.
+  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+}
+
+/**
+  * @brief  Clear CRC error flag
+  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+  * @brief  Clear mode fault error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_SR
+  *         register followed by a write access to the SPIx_CR1 register
+  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+  tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @note   Clearing this flag is done by a read access to the SPIx_DR
+  *         register followed by a read access to the SPIx_SR register
+  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->DR;
+  (void) tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @note   Clearing this flag is done by reading SPIx_SR register
+  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void) tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Enable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Disable error interrupt
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty interrupt
+  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+  * @brief  Disable Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+  * @brief  Check if error interrupt is enabled
+  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+  * @brief  Check if Rx buffer not empty interrupt is enabled
+  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+  * @brief  Check if Tx buffer empty interrupt
+  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+  return (uint32_t) & (SPIx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData8
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+  return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Read 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+  * @brief  Write 8-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData8
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+  *((__IO uint8_t *)&SPIx->DR) = TxData;
+}
+
+/**
+  * @brief  Write 16-Bits in the data register
+  * @rmtoll DR           DR            LL_SPI_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+  *((__IO uint16_t *)&SPIx->DR) = TxData;
+}
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  I2S Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
+                                         This parameter can be a value of @ref I2S_LL_EC_MODE
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
+                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+  * @{
+  */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2S_ReadReg function
+  * @{
+  */
+#define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
+#define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
+#define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
+#define LL_I2S_SR_UDR                      LL_SPI_SR_UDR             /*!< Underrun flag                    */
+#define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
+#define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
+#define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+  * @{
+  */
+#define LL_I2S_DATAFORMAT_16B              ((uint32_t)0x00000000U)                       /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_I2S_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock steady state is low level  */
+#define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+  * @{
+  */
+#define LL_I2S_STANDARD_PHILIPS            ((uint32_t)0x00000000U)                                             /*!< I2S standard philips                      */
+#define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
+#define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
+#define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_I2S_MODE_SLAVE_TX               ((uint32_t)0x00000000U)                       /*!< Slave Tx configuration  */
+#define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
+#define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+  * @{
+  */
+#define LL_I2S_PRESCALER_PARITY_EVEN       ((uint32_t)0x00000000U)   /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+  * @{
+  */
+#define LL_I2S_MCLK_OUTPUT_DISABLE         ((uint32_t)0x00000000U)   /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+  * @{
+  */
+
+#define LL_I2S_AUDIOFREQ_192K              ((uint32_t)192000)        /*!< Audio Frequency configuration 192000 Hz       */
+#define LL_I2S_AUDIOFREQ_96K               ((uint32_t) 96000)        /*!< Audio Frequency configuration  96000 Hz       */
+#define LL_I2S_AUDIOFREQ_48K               ((uint32_t) 48000)        /*!< Audio Frequency configuration  48000 Hz       */
+#define LL_I2S_AUDIOFREQ_44K               ((uint32_t) 44100)        /*!< Audio Frequency configuration  44100 Hz       */
+#define LL_I2S_AUDIOFREQ_32K               ((uint32_t) 32000)        /*!< Audio Frequency configuration  32000 Hz       */
+#define LL_I2S_AUDIOFREQ_22K               ((uint32_t) 22050)        /*!< Audio Frequency configuration  22050 Hz       */
+#define LL_I2S_AUDIOFREQ_16K               ((uint32_t) 16000)        /*!< Audio Frequency configuration  16000 Hz       */
+#define LL_I2S_AUDIOFREQ_11K               ((uint32_t) 11025)        /*!< Audio Frequency configuration  11025 Hz       */
+#define LL_I2S_AUDIOFREQ_8K                ((uint32_t)  8000)        /*!< Audio Frequency configuration   8000 Hz       */
+#define LL_I2S_AUDIOFREQ_DEFAULT           ((uint32_t)     2)        /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+  * @{
+  */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+  * @{
+  */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Select I2S mode and Enable I2S peripheral
+  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
+  *         I2SCFGR      I2SE          LL_I2S_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+  * @brief  Disable I2S peripheral
+  * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+  * @brief  Check if I2S peripheral is enabled
+  * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+}
+
+/**
+  * @brief  Set I2S data frame length
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
+  * @param  SPIx SPI Instance
+  * @param  DataFormat This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+  * @brief  Get I2S data frame length
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+  * @brief  Set I2S clock polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+  * @brief  Get I2S clock polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+  * @brief  Set I2S standard protocol
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+  * @brief  Get I2S standard protocol
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+  * @brief  Set I2S transfer mode
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+  * @brief  Get I2S transfer mode
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+  * @brief  Set I2S linear prescaler
+  * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+  * @brief  Get I2S linear prescaler
+  * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+  * @brief  Set I2S parity prescaler
+  * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+  * @brief  Get I2S parity prescaler
+  * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+  * @brief  Enable the master clock ouput (Pin MCK)
+  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+  * @brief  Disable the master clock ouput (Pin MCK)
+  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+  * @brief  Check if the master clock ouput (Pin MCK) is enabled
+  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+}
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+/**
+  * @brief  Enable asynchronous start
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+  * @brief  Disable  asynchronous start
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+  * @brief  Check if asynchronous start is enabled
+  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
+}
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if Rx buffer is not empty
+  * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+  * @brief  Check if Tx buffer is empty
+  * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+  * @brief  Get busy flag
+  * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+  * @brief  Get overrun error flag
+  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Get underrun error flag
+  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+}
+
+/**
+  * @brief  Get frame format error flag
+  * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+  * @brief  Get channel side flag.
+  * @note   0: Channel Left has to be transmitted or has been received\n
+  *         1: Channel Right has to be transmitted or has been received\n
+  *         It has no significance in PCM mode.
+  * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+  return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+}
+
+/**
+  * @brief  Clear overrun error flag
+  * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Clear underrun error flag
+  * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = SPIx->SR;
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Clear frame format error flag
+  * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable error IT
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+  * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Enable Rx buffer not empty IT
+  * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Enable Tx buffer empty IT
+  * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+  * @brief  Disable error IT
+  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+  * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Disable Rx buffer not empty IT
+  * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Disable Tx buffer empty IT
+  * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+  * @brief  Check if ERR IT is enabled
+  * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+  * @brief  Check if RXNE IT is enabled
+  * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+  * @brief  Check if TXE IT is enabled
+  * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+  * @{
+  */
+
+/**
+  * @brief  Read 16-Bits in data register
+  * @rmtoll DR           DR            LL_I2S_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+  * @brief  Write 16-Bits in data register
+  * @rmtoll DR           DR            LL_I2S_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+  LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h
new file mode 100755
index 0000000..f9a0205
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h
@@ -0,0 +1,1108 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_SYSTEM_H
+#define __STM32L0xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/* Defines used for position in the register */
+#define DBGMCU_REVID_POSITION         (uint32_t)16U
+
+/**
+ * @brief Power-down in Run mode Flash key
+ */
+#define FLASH_PDKEY1                  ((uint32_t)0x04152637U) /*!< Flash power down key1 */
+#define FLASH_PDKEY2                  ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                                   to unlock the RUN_PD bit in FLASH_ACR */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Memory Remap
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000U                                 /*!< Main Flash memory mapped at 0x00000000              */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0                               /*!< System Flash memory mapped at 0x00000000            */
+#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)   /*!< SRAM mapped at 0x00000000                           */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_CFGR1_UFB)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG Bank Mode
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1           (uint32_t)0x00000000U     /*!< Flash Bank1 mapped at 0x08000000 (and aliased at 0x00000000),
+                                                                          Flash Bank2 mapped at 0x08018000 (and aliased at 0x00018000),
+                                                                          Data EEPROM Bank1 mapped at 0x08080000 (and aliased at 0x00080000),
+                                                                          Data EEPROM Bank2 mapped at 0x08080C00 (and aliased at 0x00080C00) */
+#define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_CFGR1_UFB          /*!< Flash Bank2 mapped at 0x08000000 (and aliased at 0x00000000),
+                                                                          Flash Bank1 mapped at 0x08018000 (and aliased at 0x00018000),
+                                                                          Data EEPROM Bank2 mapped at 0x08080000 (and aliased at 0x00080000),
+                                                                          Data EEPROM Bank1 mapped at 0x08080C00 (and aliased at 0x00080C00) */
+/**
+  * @}
+  */
+
+#endif /* SYSCFG_CFGR1_UFB */
+
+/** @defgroup SYSTEM_LL_EC_BOOTMODE SYSCFG Boot Mode
+* @{
+*/
+#define LL_SYSCFG_BOOTMODE_FLASH           (uint32_t)0x00000000U                                 /*!< Main Flash memory boot mode              */
+#define LL_SYSCFG_BOOTMODE_SYSTEMFLASH     SYSCFG_CFGR1_BOOT_MODE_0                              /*!< System Flash memory boot mode            */
+#define LL_SYSCFG_BOOTMODE_SRAM            (SYSCFG_CFGR1_BOOT_MODE_1 | SYSCFG_CFGR1_BOOT_MODE_0) /*!< SRAM boot mode                           */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_CFGR2_CAPA)
+/** @defgroup SYSTEM_LL_EC_CFGR2 SYSCFG VLCD Rail Connection
+  * @{
+  */
+
+#define LL_SYSCFG_CAPA_VLCD2_PB2           SYSCFG_CFGR2_CAPA_0       /*!< Connect PB2  pin to LCD_VLCD2 rails supply voltage  */
+#define LL_SYSCFG_CAPA_VLCD1_PB12          SYSCFG_CFGR2_CAPA_1       /*!< Connect PB12 pin to LCD_VLCD1 rails supply voltage  */
+#define LL_SYSCFG_CAPA_VLCD3_PB0           SYSCFG_CFGR2_CAPA_2       /*!< Connect PB0  pin to LCD_VLCD3 rails supply voltage  */
+#if defined (SYSCFG_CFGR2_CAPA_3)
+#define LL_SYSCFG_CAPA_VLCD1_PE11          SYSCFG_CFGR2_CAPA_3       /*!< Connect PE11 pin to LCD_VLCD1 rails supply voltage  */
+#endif /* SYSCFG_CFGR2_CAPA_3 */
+#if defined (SYSCFG_CFGR2_CAPA_4)
+#define LL_SYSCFG_CAPA_VLCD3_PE12          SYSCFG_CFGR2_CAPA_4       /*!< Connect PE12 pin to LCD_VLCD3 rails supply voltage  */
+#endif /* SYSCFG_CFGR2_CAPA_4 */
+/**
+  * @}
+  */
+#endif /* SYSCFG_CFGR2_CAPA */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR2_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR2_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR2_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR2_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR2_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(SYSCFG_CFGR2_I2C2_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR2_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* SYSCFG_CFGR2_I2C2_FMP */
+#if defined(SYSCFG_CFGR2_I2C3_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR2_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
+#endif /* SYSCFG_CFGR2_I2C3_FMP */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_VREFINT_CONTROL SYSCFG VREFINT Control
+  * @{
+  */
+#define LL_SYSCFG_VREFINT_CONNECT_NONE        (uint32_t)0x00000000U             /*!< No pad connected to VREFINT_ADC */
+#define LL_SYSCFG_VREFINT_CONNECT_IO1         SYSCFG_CFGR3_VREF_OUT_0           /*!< PB0 connected to VREFINT_ADC */
+#define LL_SYSCFG_VREFINT_CONNECT_IO2         SYSCFG_CFGR3_VREF_OUT_1           /*!< PB1 connected to VREFINT_ADC */
+#define LL_SYSCFG_VREFINT_CONNECT_IO1_IO2     (SYSCFG_CFGR3_VREF_OUT_0 | SYSCFG_CFGR3_VREF_OUT_1)   /*!< PB0 and PB1 connected to VREFINT_ADC */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI Port
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0U              /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1U              /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2U              /*!< EXTI PORT C */
+#if defined(GPIOD_BASE)
+#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3U              /*!< EXTI PORT D */
+#endif /*GPIOD_BASE*/
+#if defined(GPIOE_BASE)
+#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4U              /*!< EXTI PORT E */
+#endif /*GPIOE_BASE*/
+#if defined(GPIOH_BASE)
+#define LL_SYSCFG_EXTI_PORTH               (uint32_t)5U              /*!< EXTI PORT H */
+#endif /*GPIOH_BASE*/
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI Line
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0U  << 16U | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(4U  << 16U | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(8U  << 16U | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(12U << 16U | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0U  << 16U | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(4U  << 16U | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(8U  << 16U | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(12U << 16U | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0U  << 16U | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(4U  << 16U | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(8U  << 16U | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(12U << 16U | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0U  << 16U | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(4U  << 16U | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(8U  << 16U | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(12U << 16U | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP    /*!< TIM2 counter stopped when core is halted */
+#if defined(TIM3)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP    /*!< TIM3 counter stopped when core is halted */
+#endif /*TIM3*/
+#if defined(TIM6)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP    /*!< TIM6 counter stopped when core is halted */
+#endif /*TIM6*/
+#if defined(TIM7)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP    /*!< TIM7 counter stopped when core is halted */
+#endif /*TIM7*/
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP     /*!< RTC Calendar frozen when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP    /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP    /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_STOP    /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#if defined(I2C2)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_STOP    /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#endif /*I2C2*/
+#if defined(I2C3)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_STOP    /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /*I2C3*/
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#if defined(TIM22)
+#define LL_DBGMCU_APB2_GRP1_TIM22_STOP     DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */
+#endif /*TIM22*/
+#define LL_DBGMCU_APB2_GRP1_TIM21_STOP     DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+/**
+  * @brief  Set memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_SetRemapMemory
+  * @param  Memory This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
+}
+
+/**
+  * @brief  Get memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_GetRemapMemory
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
+}
+
+#if defined(SYSCFG_CFGR1_UFB)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_CFGR1 UFB           LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{
+  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_CFGR1 UFB           LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB));
+}
+#endif /* SYSCFG_CFGR1_UFB */
+
+/**
+  * @brief  Get Boot mode selected by the boot pins status bits
+  * @note   It indicates the boot mode selected by the boot pins. Bit 9
+  *         corresponds to the complement of nBOOT1 bit in the FLASH_OPTR register.
+  *         Its value is defined in the option bytes. Bit 8 corresponds to the
+  *         value sampled on the BOOT0 pin.
+  * @rmtoll SYSCFG_CFGR1 BOOT_MODE      LL_SYSCFG_GetBootMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BOOTMODE_FLASH
+  *         @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_BOOTMODE_SRAM
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE));
+}
+
+/**
+  * @brief  Firewall protection enabled
+  * @rmtoll SYSCFG_CFGR2 FWDIS         LL_SYSCFG_EnableFirewall
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);
+}
+
+/**
+  * @brief  Check if Firewall protection is enabled or not
+  * @rmtoll SYSCFG_CFGR2 FWDIS         LL_SYSCFG_IsEnabledFirewall
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
+{
+  return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN);
+}
+
+#if defined(SYSCFG_CFGR2_CAPA)
+/**
+  * @brief  Set VLCD rail connection to optional external capacitor
+  * @note   One to three external capacitors can be connected to pads to do
+  *         VLCD biasing.
+  *         - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
+  *         - LCD_VLCD2 rail can be connected to PB2,
+  *         - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
+  * @rmtoll SYSCFG_CFGR2 CAPA      LL_SYSCFG_SetVLCDRailConnection
+  * @param  IoPinConnect This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect)
+{
+  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect);
+}
+
+
+/**
+  * @brief  Get VLCD rail connection configuration
+  * @note   One to three external capacitors can be connected to pads to do
+  *         VLCD biasing.
+  *         - LCD_VLCD1 rail can be connected to PB12 or PE11(*),
+  *         - LCD_VLCD2 rail can be connected to PB2,
+  *         - LCD_VLCD3 rail can be connected to PB0 or PE12(*)
+  * @rmtoll SYSCFG_CFGR2 CAPA      LL_SYSCFG_GetVLCDRailConnection
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*)
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0
+  *         @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*)
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetVLCDRailConnection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA));
+}
+#endif
+
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_CFGR2 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_CFGR2 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Select which pad is connected to VREFINT_ADC
+  * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT  LL_SYSCFG_VREFINT_SetConnection
+  * @param  IoPinConnect This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect)
+{
+  MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT, IoPinConnect);
+}
+
+/**
+  * @brief  Get pad connection to VREFINT_ADC
+  * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT  LL_SYSCFG_VREFINT_GetConnection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2
+  *         @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_GetConnection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT));
+}
+
+/**
+  * @brief  Buffer used to generate VREFINT reference for ADC enable
+  * @note   The VrefInit buffer to ADC through internal path is also
+  *         enabled using function LL_ADC_SetCommonPathInternalCh()
+  *         with parameter LL_ADC_PATH_INTERNAL_VREFINT
+  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC   LL_SYSCFG_VREFINT_EnableADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableADC(void)
+{
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
+}
+
+/**
+  * @brief  Buffer used to generate VREFINT reference for ADC disable
+  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC   LL_SYSCFG_VREFINT_DisableADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableADC(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
+}
+
+/**
+  * @brief  Buffer used to generate temperature sensor reference for ADC enable
+  * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC    LL_SYSCFG_TEMPSENSOR_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Enable(void)
+{
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
+}
+
+/**
+  * @brief  Buffer used to generate temperature sensor reference for ADC disable
+  * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC    LL_SYSCFG_TEMPSENSOR_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Disable(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
+}
+
+/**
+  * @brief  Buffer used to generate VREFINT reference for comparator enable
+  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP  LL_SYSCFG_VREFINT_EnableCOMP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableCOMP(void)
+{
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
+}
+
+/**
+  * @brief  Buffer used to generate VREFINT reference for comparator disable
+  * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP  LL_SYSCFG_VREFINT_DisableCOMP
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableCOMP(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
+}
+
+#if defined (RCC_HSI48_SUPPORT)
+/**
+  * @brief  Buffer used to generate VREFINT reference for HSI48 oscillator enable
+  * @rmtoll SYSCFG_CFGR3 ENREF_HSI48         LL_SYSCFG_VREFINT_EnableHSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableHSI48(void)
+{
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
+}
+
+/**
+  * @brief  Buffer used to generate VREFINT reference for HSI48 oscillator disable
+  * @rmtoll SYSCFG_CFGR3 ENREF_HSI48         LL_SYSCFG_VREFINT_DisableHSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableHSI48(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48);
+}
+#endif
+
+/**
+  * @brief  Check if VREFINT is ready or not
+  * @note   When set, it indicates that VREFINT is available for BOR, PVD and LCD
+  * @rmtoll SYSCFG_CFGR3 VREFINT_RDYF        LL_SYSCFG_VREFINT_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsReady(void)
+{
+  return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF) == SYSCFG_CFGR3_VREFINT_RDYF);
+}
+
+/**
+  * @brief  Lock the whole content of SYSCFG_CFGR3 register
+  * @note   After SYSCFG_CFGR3 register lock, only read access available.
+  *         Only system hardware reset unlocks SYSCFG_CFGR3 register.
+  * @rmtoll SYSCFG_CFGR3 REF_LOCK            LL_SYSCFG_VREFINT_Lock
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VREFINT_Lock(void)
+{
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK);
+}
+
+/**
+  * @brief  Check if SYSCFG_CFGR3 register is locked (only read access) or not
+  * @note   When set, it indicates that SYSCFG_CFGR3 register is locked, only read access available
+  * @rmtoll SYSCFG_CFGR3 REF_LOCK              LL_SYSCFG_VREFINT_IsLocked
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsLocked(void)
+{
+  return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK) == SYSCFG_CFGR3_REF_LOCK);
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], SYSCFG_EXTICR1_EXTI0 << (Line >> 16U), Port << (Line >> 16U));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTI0         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI1         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI2         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR1 EXTI3         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI4         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI5         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI6         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTI7         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI8         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI9         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI10        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTI11        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI12        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI13        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI14        LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTI15        LL_SYSCFG_SetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+  *
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16U))) >> (Line >> 16U));
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0x7FF (ex: L053 -> 0x417, L073 -> 0x447)
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll APB1FZ      DBG_TIM2_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_TIM3_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_TIM6_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_TIM7_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_RTC_STOP      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_WWDG_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_IWDG_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_I2C1_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_I2C2_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_I2C3_STOP     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         APB1FZ      DBG_LPTIMER_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll APB1FZ      DBG_TIM2_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_TIM3_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_TIM6_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_TIM7_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_RTC_STOP      LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_WWDG_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_IWDG_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_I2C1_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_I2C2_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_I2C3_STOP     LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         APB1FZ      DBG_LPTIMER_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll APB2FZ      DBG_TIM22_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         APB2FZ      DBG_TIM21_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll APB2FZ      DBG_TIM22_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         APB2FZ      DBG_TIM21_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+
+/**
+  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
+  * @note Flash memory can be put in power-down mode only when the code is executed
+  *       from RAM
+  * @note Flash must not be accessed when power down is enabled
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
+  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
+  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
+{
+  /* Following values must be written consecutively to unlock the RUN_PD bit in
+     FLASH_ACR */
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
+  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
+}
+
+/**
+  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @note Flash must not be put in power-down while a program or an erase operation
+  *       is on-going
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
+  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
+}
+
+/**
+  * @brief  Enable buffers used as a cache during read access
+  * @rmtoll FLASH_ACR    DISAB_BUF     LL_FLASH_EnableBuffers
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableBuffers(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
+}
+
+/**
+  * @brief  Disable buffers used as a cache during read access
+  * @note   When disabled, every read will access the NVM even for
+  *         an address already read (for example, the previous address).
+  * @rmtoll FLASH_ACR    DISAB_BUF     LL_FLASH_DisableBuffers
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableBuffers(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF);
+}
+
+/**
+  * @brief  Enable pre-read
+  * @note   When enabled, the memory interface stores the last address
+  *         read as data and tries to read the next one when no other
+  *         read or write or prefetch operation is ongoing.
+  *         It is automatically disabled every time the buffers are disabled.
+  * @rmtoll FLASH_ACR    PRE_READ      LL_FLASH_EnablePreRead
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePreRead(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
+}
+
+/**
+  * @brief  Disable pre-read
+  * @rmtoll FLASH_ACR    PRE_READ      LL_FLASH_DisablePreRead
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePreRead(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRE_READ);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
new file mode 100755
index 0000000..d33ab77
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
@@ -0,0 +1,3340 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_TIM_H
+#define __STM32L0xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: NA */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: NA */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x00U,   /* 5: NA */
+  0x04U    /* 6: TIMx_CH4  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U             /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U             /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  0U,            /* 1: NA */
+  4U,            /* 2: CC2P */
+  0U,            /* 3: NA */
+  8U,            /* 4: CC3P */
+  0U,            /* 5: NA */
+  12U            /* 6: CC4P */
+};
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+
+/* Remap mask definitions */
+#define TIMx_OR_RMP_SHIFT  ((uint32_t)16U)
+#define TIMx_OR_RMP_MASK   ((uint32_t)0x0000FFFFU)
+#define TIM2_OR_RMP_MASK   ((uint32_t)((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT))
+#define TIM21_OR_RMP_MASK  ((uint32_t)((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << TIMx_OR_RMP_SHIFT))
+#define TIM22_OR_RMP_MASK  ((uint32_t)((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT))
+#if defined(TIM3)
+#define TIM3_OR_RMP_MASK   ((uint32_t)((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP) << TIMx_OR_RMP_SHIFT))
+#endif /* TIM3 */
+
+
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;       /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS            /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM            /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR             /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0           /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1           /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS             /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0           /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1           /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             ((uint32_t)0x00000000U) /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR             /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS            /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 ((uint32_t)0x00000000U) /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   ((uint32_t)0x00000000U)                                  /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)                                       /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 ((uint32_t)0x00000000U)     /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (uint32_t)(TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (uint32_t)(TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 ((uint32_t)0x00000000U)                                         /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (uint32_t)(TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              ((uint32_t)0x00000000U)          /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            ((uint32_t)0x00000000U)                              /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                        /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      ((uint32_t)0x00000000U)                         /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              ((uint32_t)0x00000000U)             /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         ((uint32_t)0x00000000U)                          /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                ((uint32_t)0x00000000U)                              /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )                   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_0)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_1)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+
+
+
+
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           ((uint32_t)0x00000000U)                                          /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_OR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR3           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_OR3 register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       ((uint32_t)0x00000000U)                                         /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_TIM2_ETR_RMP  TIM2 External Trigger Remap
+* @{
+*/
+#define LL_TIM_TIM2_ETR_RMP_GPIO     ((uint32_t)0x00000000U | TIM2_OR_RMP_MASK)                   /*!< TIM2_ETR is connected to Ored GPIO */
+#if defined(TIM_TIM2_REMAP_HSI_SUPPORT)
+#define LL_TIM_TIM2_ETR_RMP_HSI      (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to HSI */
+#endif /* defined(TIM_TIM2_REMAP_HSI_SUPPORT) */
+#if defined(TIM_TIM2_REMAP_HSI48_SUPPORT)
+#define LL_TIM_TIM2_ETR_RMP_HSI48    (TIM2_OR_ETR_RMP_2 | TIM2_OR_RMP_MASK)                       /*!< TIM2_ETR is connected to HSI48 */
+#endif /* defined(TIM_TIM2_REMAP_HSI48_SUPPORT) */
+#define LL_TIM_TIM2_ETR_RMP_LSE      (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to LSE */
+#define LL_TIM_TIM2_ETR_RMP_COMP2    (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1 | TIM2_OR_RMP_MASK)   /*!< TIM2_ETR is connected to COMP2_OUT */
+#define LL_TIM_TIM2_ETR_RMP_COMP1    (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK)                         /*!< TIM2_ETR is connected to COMP1_OUT */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
+* @{
+*/
+#define LL_TIM_TIM2_TI4_RMP_GPIO      ((uint32_t)0x00000000U | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP2     (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK)     /*!< TIM2 input capture 4 is connected to COMP2_OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP1     (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK)     /*!< TIM2 input capture 4 is connected to COMP1_OUT */
+/**
+  * @}
+  */
+
+#if defined(TIM3_OR_ETR_RMP)
+/** @defgroup TIM_LL_EC_TIM3_ETR_RMP  TIM3 External Trigger Remap
+* @{
+*/
+#define LL_TIM_TIM3_ETR_RMP_GPIO         ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK)     /*!< TIM3_ETR is connected to GPIO */
+#define LL_TIM_TIM3_ETR_RMP_HSI48DIV6    (TIM3_OR_ETR_RMP_1 | TIM3_OR_RMP_MASK)         /*!< TIM3_ETR is connected to HSI48 divided by 6 */
+/**
+  * @}
+  */
+#endif /* defined(TIM3_OR_ETR_RMP) */
+
+#if defined(TIM3_OR_TI1_RMP) || defined(TIM3_OR_TI2_RMP) || defined(TIM3_OR_TI4_RMP)
+/** @defgroup TIM_LL_EC_TIM3_TI_RMP  TIM3 External Inputs Remap
+* @{
+*/
+#define LL_TIM_TIM3_TI_RMP_TI1_USB_SOF      ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< TIM3_TI1 input is connected to USB_SOF */
+#define LL_TIM_TIM3_TI_RMP_TI1_GPIO         (TIM3_OR_TI1_RMP | TIM3_OR_RMP_MASK)       /*!< TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 */
+
+#define LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF     ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< Mapping PB5 to TIM22_CH2 */
+#define LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4   (TIM3_OR_TI2_RMP | TIM3_OR_RMP_MASK)       /*!< Mapping PB5 to TIM3_CH2 */
+
+#define LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF     ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< Mapping PC9 to USB_OE */
+#define LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2   (TIM3_OR_TI4_RMP | TIM3_OR_RMP_MASK)       /*!< Mapping PC9 to TIM3_CH4 */
+/**
+  * @}
+  */
+#endif /*defined(TIM3_OR_TI1_RMP) or defined(TIM3_OR_TI2_RMP) or defined(TIM3_OR_TI4_RMP)*/
+
+/** @defgroup TIM_LL_EC_TIM21_ETR_RMP  TIM21 External Trigger Remap
+* @{
+*/
+#define LL_TIM_TIM21_ETR_RMP_GPIO  ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to Ored GPIO1 */
+#define LL_TIM_TIM21_ETR_RMP_COMP2 (TIM21_OR_ETR_RMP_0 | TIM21_OR_RMP_MASK)    /*!< TIM21_ETR is connected to COMP2_OUT */
+#define LL_TIM_TIM21_ETR_RMP_COMP1 (TIM21_OR_ETR_RMP_1 | TIM21_OR_RMP_MASK)    /*!< TIM21_ETR is connected to COMP1_OUT */
+#define LL_TIM_TIM21_ETR_RMP_LSE   (TIM21_OR_ETR_RMP | TIM21_OR_RMP_MASK)      /*!< TIM21_ETR is connected to LSE */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM21_TI1_RMP  TIM21 External Input Ch1 Remap
+* @{
+*/
+#define LL_TIM_TIM21_TI1_RMP_GPIO    ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK)    /*!< TIM21_TI1 is connected to Ored GPIO1 */
+#define LL_TIM_TIM21_TI1_RMP_RTC_WK  (TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)       /*!< TIM21_TI1 is connected to RTC_WAKEUP */
+#define LL_TIM_TIM21_TI1_RMP_HSE_RTC (TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK)       /*!< TIM21_TI1 is connected to HSE_RTC */
+#define LL_TIM_TIM21_TI1_RMP_MSI     (TIM21_OR_TI1_RMP_1 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to MSI */
+#define LL_TIM_TIM21_TI1_RMP_LSE     (TIM21_OR_TI1_RMP_2 | TIM21_OR_RMP_MASK)                       /*!< TIM21_TI1 is connected to LSE */
+#define LL_TIM_TIM21_TI1_RMP_LSI     (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to LSI */
+#define LL_TIM_TIM21_TI1_RMP_COMP1   (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK)  /*!< TIM21_TI1 is connected to COMP1_OUT */
+#define LL_TIM_TIM21_TI1_RMP_MCO     (TIM21_OR_TI1_RMP | TIM21_OR_RMP_MASK)                         /*!< TIM21_TI1 is connected to MCO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM21_TI2_RMP  TIM21 External Input Ch2 Remap
+* @{
+*/
+#define LL_TIM_TIM21_TI2_RMP_GPIO    ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK)  /*!< TIM21_TI2 is connected to Ored GPIO1 */
+#define LL_TIM_TIM21_TI2_RMP_COMP2   (TIM21_OR_TI2_RMP | TIM21_OR_RMP_MASK)       /*!< TIM21_TI2 is connected to COMP2_OUT */
+/**
+  * @}
+  */
+
+#if defined(TIM22_OR_ETR_RMP)
+
+/** @defgroup TIM_LL_EC_TIM22_ETR_RMP  TIM22 External Trigger Remap
+* @{
+*/
+#define LL_TIM_TIM22_ETR_RMP_GPIO  ((uint32_t)0x00000000U | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to GPIO */
+#define LL_TIM_TIM22_ETR_RMP_COMP2 (TIM22_OR_ETR_RMP_0 | TIM22_OR_RMP_MASK)    /*!< TIM22_ETR is connected to COMP2_OUT */
+#define LL_TIM_TIM22_ETR_RMP_COMP1 (TIM22_OR_ETR_RMP_1 | TIM22_OR_RMP_MASK)    /*!< TIM22_ETR is connected to COMP1_OUT */
+#define LL_TIM_TIM22_ETR_RMP_LSE   (TIM22_OR_ETR_RMP | TIM22_OR_RMP_MASK)      /*!< TIM22_ETR is connected to LSE */
+/**
+  * @}
+  */
+#endif /* defined(TIM22_OR_ETR_RMP) */
+
+#if defined(TIM22_OR_TI1_RMP)
+/** @defgroup TIM_LL_EC_TIM22_TI1_RMP  TIM22 External Input Ch1 Remap
+* @{
+*/
+#define LL_TIM_TIM22_TI1_RMP_GPIO1  ((uint32_t)0x00000000U | TIM22_OR_RMP_MASK)  /*!< TIM22_TI1 is connected to GPIO1 */
+#define LL_TIM_TIM22_TI1_RMP_COMP2  (TIM22_OR_TI1_RMP_0 | TIM22_OR_RMP_MASK)     /*!< TIM22_TI1 is connected to COMP2_OUT */
+#define LL_TIM_TIM22_TI1_RMP_COMP1  (TIM22_OR_TI1_RMP_1 | TIM22_OR_RMP_MASK)     /*!< TIM22_TI1 is connected to COMP1_OUT */
+#define LL_TIM_TIM22_TI1_RMP_GPIO2  (TIM22_OR_TI1_RMP | TIM22_OR_RMP_MASK)       /*!< TIM22_TI1 is connected to GPIO2 */
+/**
+  * @}
+  */
+#endif /* defined(TIM22_OR_TI1_RMP) */
+
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+  * @{
+  */
+#define LL_TIM_OCREF_CLR_INT_NC     ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is not connected */
+#define LL_TIM_OCREF_CLR_INT_ETR    TIM_SMCR_OCCS            /*!< OCREF_CLR_INT is connected to ETRF */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+   ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+     (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+          / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+           + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+   ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM2_OR     ETR_RMP      LL_TIM_SetRemap\n
+  *         TIM2_OR     TI4_RMP      LL_TIM_SetRemap\n
+  *         TIM21_OR    ETR_RMP      LL_TIM_SetRemap\n
+  *         TIM21_OR    TI1_RMP      LL_TIM_SetRemap\n
+  *         TIM21_OR    TI2_RMP      LL_TIM_SetRemap\n
+  *         TIM22_OR    ETR_RMP      LL_TIM_SetRemap\n
+  *         TIM22_OR    TI1_RMP      LL_TIM_SetRemap\n
+  *         TIM3_OR     ETR_RMP      LL_TIM_SetRemap\n
+  *         TIM3_OR     TI1_RMP      LL_TIM_SetRemap\n
+  *         TIM3_OR     TI2_RMP      LL_TIM_SetRemap\n
+  *         TIM3_OR     TI4_RMP      LL_TIM_SetRemap
+  * @param  TIMx Timer instance
+  * @param  Remap Remap params depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of OR registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM2: any combination of ETR_RMP, TI4_RMP where
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_HSI   (*)
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*)
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1
+  *
+  *            . . TI4_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
+  *
+  *         TIM3: any combination of the following values        (**)
+  *
+  *            . . ETR_RMP can be one of the following values    (**)
+  *            @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6
+  *
+  *            . . TI_RMP_TI1 can be one of the following values (**)
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO
+  *
+  *            . . TI_RMP_TI2 can be one of the following values (**)
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4
+  *
+  *            . . TI_RMP_TI4 can be one of the following values (**)
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF
+  *            @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2
+  *
+  *         TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM21_ETR_RMP_LSE
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_MSI
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_LSI
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM21_TI1_RMP_MCO
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2
+  *
+  *         TIM22: any combination of ETR_RMP, TI1_RMP where  (**)
+  *
+  *            . . ETR_RMP can be one of the following values (**)
+  *            @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM22_ETR_RMP_LSE
+  *
+  *            . . TI1_RMP can be one of the following values (**)
+  *            @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1
+  *            @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2
+  *            @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1
+  *            @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2
+  *
+  *         (*) Value not defined in all devices. \n
+  *         (*) Register not available in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+  * @{
+  */
+/**
+  * @brief  Set the OCREF clear input source
+  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+  * @note This function can only be used in Output compare and PWM modes.
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
+  * @param  TIMx Timer instance
+  * @param  OCRefClearInputSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_NC
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
new file mode 100755
index 0000000..460dce2
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
@@ -0,0 +1,3720 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_USART_H
+#define __STM32L0xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define USART_POSITION_CR1_DEDT                 (uint32_t)16
+#define USART_POSITION_CR1_DEAT                 (uint32_t)21
+#define USART_POSITION_CR2_ADD                  (uint32_t)24
+#define USART_POSITION_CR3_SCARCNT              (uint32_t)17
+#define USART_POSITION_RTOR_BLEN                (uint32_t)24
+#define USART_POSITION_GTPR_GT                  (uint32_t)8
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
+#define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise detected flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
+#endif
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#if defined(USART_TCBGT_SUPPORT)
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    (uint32_t)0x00000000U                /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                (uint32_t)0x00000000U /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   (uint32_t)0x00000000U   /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                (uint32_t)0x00000000U  /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  (uint32_t)0x00000000U  /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     (uint32_t)0x00000000U                      /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    (uint32_t)0x00000000U                       /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              (uint32_t)0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 (uint32_t)0x00000000U                /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              (uint32_t)0x00000000U                   /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              (uint32_t)0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            (uint32_t)0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               (uint32_t)0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          (uint32_t)0U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           (uint32_t)1U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  register uint32_t usartdiv = 0x0U;
+  register uint32_t brrtemp = 0x0U;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+  register uint32_t usartdiv = 0x0U;
+  register uint32_t brrresult = 0x0U;
+
+  usartdiv = USARTx->BRR;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    if ((usartdiv & 0xFFF7U) != 0U)
+    {
+      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+      brrresult = (PeriphClk * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = PeriphClk / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NF            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+  * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT));
+}
+#endif
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+#endif
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+#endif
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+#if defined(USART_TCBGT_SUPPORT)
+/* Function available only on devices supporting Transmit Complete before Guard Time feature */
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE));
+}
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr = 0U;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data flush
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data flush
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART4 || USART5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h
new file mode 100755
index 0000000..398e876
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h
@@ -0,0 +1,284 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_UTILS_H
+#define __STM32L0xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLMul;   /*!< Multiplication factor for PLL VCO input clock.
+                          This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
+
+                          This feature can be modified afterwards using unitary function
+                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLDiv;   /*!< Division factor for PLL VCO output clock.
+                          This parameter can be a value of @ref RCC_LL_EC_PLL_DIV 
+  
+                          This feature can be modified afterwards using unitary function
+                          @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h
new file mode 100755
index 0000000..3e60ad5
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_wwdg.h
@@ -0,0 +1,340 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_wwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of WWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_LL_WWDG_H
+#define __STM32L0xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
+  * @{
+  */
+#define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1                (uint32_t)0x00000000U                                   /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
+  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
+  *         then it cannot be disabled again except by a reset.
+  *         This bit is set by software and only cleared by hardware after a reset.
+  *         When WDGA = 1, the watchdog can generate a reset.
+  * @rmtoll CR           WDGA          LL_WWDG_Enable
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+  * @brief  Checks if Window Watchdog is enabled
+  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
+  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+  * @rmtoll CR           T             LL_WWDG_SetCounter
+  * @param  WWDGx WWDG Instance
+  * @param  Counter 0..0x7F (7 bit counter value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+  * @brief  Return current Watchdog Counter Value (7 bits counter value)
+  * @rmtoll CR           T             LL_WWDG_GetCounter
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Counter value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+  * @brief  Set the time base of the prescaler (WDGTB).
+  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+  *         is decremented every (4096 x 2expWDGTB) PCLK cycles
+  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+  * @brief  Return current Watchdog Prescaler Value
+  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+  * @note   This window value defines when write in the WWDG_CR register
+  *         to program Watchdog counter is allowed.
+  *         Watchdog counter value update must occur only when the counter value
+  *         is lower than the Watchdog window register value.
+  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+  *         (in the control register) is refreshed before the downcounter has reached
+  *         the watchdog window register value.
+  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
+  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+  * @rmtoll CFR          W             LL_WWDG_SetWindow
+  * @param  WWDGx WWDG Instance
+  * @param  Window 0x00..0x7F (7 bit Window value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+  * @brief  Return current Watchdog Window Value (7 bits value)
+  * @rmtoll CFR          W             LL_WWDG_GetWindow
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Window value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+  return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+/**
+  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+  * @note   This bit is set by hardware when the counter has reached the value 0x40.
+  *         It must be cleared by software by writing 0.
+  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable the Early Wakeup Interrupt.
+  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
+  *         This interrupt is only cleared by hardware after a reset
+  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+  * @brief  Check if Early Wakeup Interrupt is enabled
+  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* WWDG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c
new file mode 100755
index 0000000..da7990a
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c
@@ -0,0 +1,2196 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *             ++ Initialization and Configuration of ADC
+  *           + Operation functions
+  *             ++ Start, stop, get result of conversions of regular
+  *                group, using 3 possible modes: polling, interruption or DMA.
+  *           + Control functions
+  *             ++ Channels configuration on regular group
+  *             ++ Analog Watchdog configuration
+  *           + State functions
+  *             ++ ADC state machine management
+  *             ++ Interrupts and flags management
+  *          Other functions (extended functions) are available in file 
+  *          "stm32l0xx_hal_adc_ex.c".
+  *
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of 
+      analog watchdog or overrun events.
+  
+  (+) Single and continuous conversion modes.
+  
+  (+) Scan mode for conversion of several channels sequentially.
+  
+  (+) Data alignment with in-built data coherency.
+  
+  (+) Programmable sampling time (common for all channels)
+  
+  (+) External trigger (timer or EXTI) with configurable polarity
+  
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) ADC calibration
+  
+  (+) ADC conversion of regular group.
+  
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+  
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+             Caution: On STM32L0, ADC clock frequency max is 16MHz (refer
+                      to device datasheet).
+                      Therefore, ADC clock prescaler must be configured in 
+                      function of ADC clock source frequency to remain below
+                      this maximum frequency.
+
+        (++) Two clock settings are mandatory: 
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from APB clock
+                   or asynchronous clock derived from ADC dedicated HSI RC oscillator
+                   16MHz.
+                   If asynchronous clock is selected, parameter "HSIState" must be set either:
+                   - to "...HSIState = RCC_HSI_ON" to maintain the HSI16 oscillator
+                     always enabled: can be used to supply the main system clock.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC1_CLK_ENABLE();                 (mandatory)
+
+               HSI enable                                         (optional: if asynchronous clock selected)
+               (+++) RCC_OscInitTypeDef   RCC_OscInitStructure;
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+               (+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
+               (+++) RCC_OscInitStructure.PLL...   (optional if used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding ADC interruption vector 
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
+              into the function of corresponding DMA interruption vector 
+              DMAx_Channelx_IRQHandler().
+
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number, 
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+
+    (#) When device is in mode low-power (low-power run, low-power sleep or stop mode), 
+        function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init().
+        In case of internal temperature sensor to be measured:
+        function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion 
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption: 
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results 
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral 
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+  
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Delay for ADC stabilization time.                                          */
+/* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_STAB_DELAY_US       ((uint32_t) 1U)
+
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) 
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc);
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+static void ADC_DelayMicroSecond(uint32_t microSecond);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC. 
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to  
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         depending on possible clock sources: APB clock of HSI clock.
+  *         See commented example code below that can be copied and uncommented
+  *         into HAL_ADC_MspInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef  
+  *         structure on the fly, without modifying MSP configuration. If ADC  
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire 
+  *         ADC and scope of regular group. For parameters details, see comments 
+  *         of structure "ADC_InitTypeDef".
+  * @note   When device is in mode low-power (low-power run, low-power sleep or stop mode), 
+  *         function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init() 
+  *         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first).
+  *         In case of internal temperature sensor to be measured:
+  *         function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly.  
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ 
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+  assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
+  /* at RCC top level depending on both possible clock sources:               */
+  /* APB clock or HSI clock.                                                  */
+  /* Refer to header of this file for more details on clock enabling procedure*/
+  
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  /* - ADC voltage regulator enable                                           */
+  if(hadc->State == HAL_ADC_STATE_RESET)
+  {
+    /* Initialize ADC error code */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Allocate lock resource and initialize it */
+    hadc->Lock = HAL_UNLOCKED;
+    
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+  }
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  /* and if there is no conversion on going on regular group (ADC can be      */
+  /* enabled anyway, in case of call of this function to update a parameter   */
+  /* on the fly).                                                             */
+  if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) ||
+     (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)  )
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+    return HAL_ERROR;
+  }
+
+  /* Set ADC state */
+  ADC_STATE_CLR_SET(hadc->State,
+                    HAL_ADC_STATE_REG_BUSY,
+                    HAL_ADC_STATE_BUSY_INTERNAL);
+
+  /* Parameters update conditioned to ADC state:                            */
+  /* Parameters that can be updated only when ADC is disabled:              */
+  /*  - ADC clock mode                                                      */
+  /*  - ADC clock prescaler                                                 */
+  /*  - ADC Resolution                                                      */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Some parameters of this register are not reset, since they are set   */
+    /* by other functions and must be kept in case of usage of this         */
+    /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+    /* without needing to reconfigure all other ADC groups/channels         */
+    /* parameters):                                                         */
+    /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+    /*     (set into HAL_ADC_ConfigChannel() )                              */
+   
+    /* Configuration of ADC clock: clock source PCLK or asynchronous with 
+    selectable prescaler */
+    __HAL_ADC_CLOCK_PRESCALER(hadc);
+    
+    /* Configuration of ADC:                                                */
+    /*  - Resolution                                                        */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_RES);
+    hadc->Instance->CFGR1 |= hadc->Init.Resolution;    
+  }
+  
+  /* Set the Low Frequency mode */
+  ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN;
+  ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode);  
+   
+  /* Enable voltage regulator (if disabled at this step) */
+  if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+  {
+    /* Set ADVREGEN bit */
+    hadc->Instance->CR |= ADC_CR_ADVREGEN;
+  }
+  
+  /* Configuration of ADC:                                                    */
+  /*  - Resolution                                                            */
+  /*  - Data alignment                                                        */
+  /*  - Scan direction                                                        */
+  /*  - External trigger to start conversion                                  */
+  /*  - External trigger polarity                                             */
+  /*  - Continuous conversion mode                                            */
+  /*  - DMA continuous request                                                */
+  /*  - Overrun                                                               */
+  /*  - AutoDelay feature                                                     */
+  /*  - Discontinuous mode                                                    */
+  hadc->Instance->CFGR1 &= ~(ADC_CFGR1_ALIGN   |
+                             ADC_CFGR1_SCANDIR |
+                             ADC_CFGR1_EXTSEL  |
+                             ADC_CFGR1_EXTEN   |
+                             ADC_CFGR1_CONT    |
+                             ADC_CFGR1_DMACFG  |
+                             ADC_CFGR1_OVRMOD  |
+                             ADC_CFGR1_AUTDLY  |
+                             ADC_CFGR1_AUTOFF  |
+                             ADC_CFGR1_DISCEN   );
+  
+  hadc->Instance->CFGR1 |= (hadc->Init.DataAlign                             |
+                            ADC_SCANDIR(hadc->Init.ScanConvMode)             |
+                            ADC_CONTINUOUS(hadc->Init.ContinuousConvMode)    |
+                            ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
+                            hadc->Init.Overrun                               |
+                            __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) |
+                            __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff));
+  
+  /* Enable external trigger if trigger selection is different of software  */
+  /* start.                                                                 */
+  /* Note: This configuration keeps the hardware feature of parameter       */
+  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+  /*       software start.                                                  */
+  if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+  {
+    hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv |
+                             hadc->Init.ExternalTrigConvEdge;
+  }
+  
+  /* Enable discontinuous mode only if continuous mode is disabled */
+  if (hadc->Init.DiscontinuousConvMode == ENABLE)
+  {
+    if (hadc->Init.ContinuousConvMode == DISABLE)
+    {
+      /* Enable the selected ADC group regular discontinuous mode */
+      hadc->Instance->CFGR1 |= (ADC_CFGR1_DISCEN);
+    }
+    else
+    {
+      /* ADC regular group discontinuous was intended to be enabled,        */
+      /* but ADC regular group modes continuous and sequencer discontinuous */
+      /* cannot be enabled simultaneously.                                  */
+      
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+    }
+  }
+  
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversample.Ratio));
+    assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversample.RightBitShift));
+    assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversample.TriggeredMode));
+
+    /* Configuration of Oversampler:                                          */
+    /*  - Oversampling Ratio                                                  */
+    /*  - Right bit shift                                                     */
+    /*  - Triggered mode                                                      */
+    
+    hadc->Instance->CFGR2 &= ~( ADC_CFGR2_OVSR |
+                                ADC_CFGR2_OVSS |
+                                ADC_CFGR2_TOVS );
+    
+    hadc->Instance->CFGR2 |= ( hadc->Init.Oversample.Ratio         |
+                               hadc->Init.Oversample.RightBitShift             |
+                               hadc->Init.Oversample.TriggeredMode );
+    
+    /* Enable OverSampling mode */
+     hadc->Instance->CFGR2 |= ADC_CFGR2_OVSE;
+  }
+  else
+  {
+    if(HAL_IS_BIT_SET(hadc->Instance->CFGR2, ADC_CFGR2_OVSE))
+    {
+      /* Disable OverSampling mode if needed */
+      hadc->Instance->CFGR2 &= ~ADC_CFGR2_OVSE;
+    }
+  }    
+  
+  /* Clear the old sampling time */
+  hadc->Instance->SMPR &= (uint32_t)(~ADC_SMPR_SMPR);
+  
+  /* Set the new sample time */
+  hadc->Instance->SMPR |= hadc->Init.SamplingTime;
+  
+  /* Clear ADC error code */
+  ADC_CLEAR_ERRORCODE(hadc);
+
+  /* Set the ADC state */
+  ADC_STATE_CLR_SET(hadc->State,
+                    HAL_ADC_STATE_BUSY_INTERNAL,
+                    HAL_ADC_STATE_READY);
+
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done 
+  *         only if all ADCs sharing the same common group are disabled.
+  *         If this is not the case, reset of these common parameters reset is  
+  *         bypassed without error reporting: it can be the intended behavior in
+  *         case of reset of a single ADC while the other ADCs sharing the same 
+  *         common group is still running.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check ADC handle */
+  if(hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+  
+  /* Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {   
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status != HAL_ERROR)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+  }
+  
+  
+  /* Configuration of ADC parameters if previous preliminary actions are      */ 
+  /* correctly completed.                                                     */
+  if (tmp_hal_status != HAL_ERROR)
+  {
+    
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | ADC_IT_EOCAL | ADC_IT_EOS |  \
+                                ADC_IT_EOC | ADC_IT_RDY | ADC_IT_EOSMP ));
+  
+        
+    /* Reset register ISR */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_EOCAL | ADC_FLAG_OVR | ADC_FLAG_EOS |  \
+                                ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+  
+    
+    /* Reset register CR */
+    /* Disable voltage regulator */
+    /* Note: Regulator disable useful for power saving */
+    /* Reset ADVREGEN bit */
+    hadc->Instance->CR &= ~ADC_CR_ADVREGEN;
+    
+    /* Bits ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode "read-set": no direct reset applicable */
+    /* No action */
+    
+    /* Reset register CFGR1 */
+    hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH  | ADC_CFGR1_AWDEN  | ADC_CFGR1_AWDSGL | \
+                               ADC_CFGR1_DISCEN | ADC_CFGR1_AUTOFF | ADC_CFGR1_AUTDLY | \
+                               ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD | ADC_CFGR1_EXTEN  | \
+                               ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN  | ADC_CFGR1_RES    | \
+                               ADC_CFGR1_SCANDIR| ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
+  
+    /* Reset register CFGR2 */
+    hadc->Instance->CFGR2 &= ~(ADC_CFGR2_TOVS  | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR | \
+                               ADC_CFGR2_OVSE  | ADC_CFGR2_CKMODE );
+  
+    
+    /* Reset register SMPR */
+    hadc->Instance->SMPR &= ~(ADC_SMPR_SMPR);
+    
+    /* Reset register TR */
+    hadc->Instance->TR &= ~(ADC_TR_LT | ADC_TR_HT);
+    
+    /* Reset register CALFACT */
+    hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
+  
+  
+  
+  
+    
+    /* Reset register DR */
+    /* bits in access mode read only, no direct reset applicable*/
+  
+    /* Reset register CALFACT */
+    hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT);
+  
+    /* ========== Hard reset ADC peripheral ========== */
+    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
+    /* forced to a similar state after device power-on.                       */
+    /* If needed, copy-paste and uncomment the following reset code into      */
+    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
+    /*                                                                        */
+    /*  __HAL_RCC_ADC1_FORCE_RESET()                                                  */
+    /*  __HAL_RCC_ADC1_RELEASE_RESET()                                                */
+  
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
+    
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+    
+    /* Set ADC state */
+    hadc->State = HAL_ADC_STATE_RESET;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */ 
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ *  @brief    ADC IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
+    /* performed automatically by hardware.                                   */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in 
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on ADC group regular */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are 
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured 
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still 
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param  hadc: ADC handle
+  * @param  Timeout: Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+  uint32_t tmp_Flag_EOC   = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_EOC = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+    if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+      
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+    }
+  }
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+  
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+     (hadc->Init.ContinuousConvMode == DISABLE)   )
+  {
+    /* If End of Sequence is reached, disable interrupts */
+    if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+    {
+      /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
+      /* ADSTART==0 (no conversion on going)                                  */
+      if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+      {
+        /* Disable ADC end of single conversion interrupt on group regular */
+        /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+        /* HAL_Start_IT(), but is not disabled here because can be used       */
+        /* by overrun IRQ process below.                                      */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+        
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* Change ADC state to error state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      }
+    }
+  }
+  
+  /* Clear end of conversion flag of regular group if low power feature       */
+  /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
+  /* until data register is read using function HAL_ADC_GetValue().           */
+  if (hadc->Init.LowPowerAutoWait == DISABLE)
+  {
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param  hadc: ADC handle
+  * @param  EventType: the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AWD_EVENT: ADC Analog watchdog event
+  *            @arg ADC_OVR_EVENT: ADC Overrun event
+  * @param  Timeout: Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set  
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten 
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U; 
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+  
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  /* Check selected event flag */
+  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  
+  switch(EventType)
+  {
+  /* Analog watchdog (level out of window) event */
+  case ADC_AWD_EVENT:
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+    
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+    break;
+    
+  /* Overrun event */
+  default: /* Case ADC_OVR_EVENT */
+    /* If overrun is set to overwrite previous data, overrun event is not     */
+    /* considered as an error.                                                */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+        
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+    }
+    
+    /* Clear ADC Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+    break;
+  }
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence), 
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling 
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)             
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)     
+  *          before calling HAL_ADC_Start_IT().
+  * @param  hadc: ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+    
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
+    /* performed automatically by hardware.                                   */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable ADC end of conversion interrupt */
+      /* Enable ADC overrun interrupt */  
+      switch(hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV: 
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+          break;
+      }
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in 
+  *         case of auto_injection mode), disable interrution of 
+  *         end-of-conversion, disable ADC peripheral.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential conversion on going, on ADC group regular */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+    
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+    
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete. 
+  *         Each of these interruptions has its dedicated callback function.
+  * @param  hadc: ADC handle
+  * @param  pData: Destination Buffer address.
+  * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are       */
+    /* performed automatically by hardware.                                     */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      tmp_hal_status = ADC_Enable(hadc);
+    }
+    
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+      
+      /* Reset ADC all error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+      
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+      
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+      
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+      
+      
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
+      /* start (in case of SW start):                                         */
+      
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+      
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      
+      /* Enable ADC DMA mode */
+      hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+      
+      /* Start the DMA channel */
+      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+      
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      hadc->Instance->CR |= ADC_CR_ADSTART;
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in 
+  *         case of auto_injection mode), disable ADC DMA transfer, disable 
+  *         ADC peripheral.
+  *         Each of these interruptions has its dedicated callback function.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+  
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+    
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+    
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep  */
+    /* in memory a potential failing status.                                  */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+    
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS 
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param  hadc: ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+  
+  /* Return ADC converted value */ 
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  
+  /* ========== Check End of Conversion flag for regular group ========== */
+  if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || 
+      (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS))   )
+  {
+    /* Update state machine on conversion status if not in error state */
+    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    }
+    
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+          
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+    
+    /* Conversion complete callback */
+    /* Note: into callback, to determine if conversion has been triggered     */
+    /*       from EOC or EOS, possibility to use:                             */
+    /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
+    HAL_ADC_ConvCpltCallback(hadc);
+    
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    /* Note: Management of low power auto-wait enabled: flags must be cleared */
+    /*       by user when fetching ADC conversion data.                       */
+    /*       This case is managed in IRQ handler, but this low-power mode     */
+    /*       should not be used with programming model IT or DMA.             */
+    /*       Refer to comment of parameter "LowPowerAutoWait".                */
+    if (hadc->Init.LowPowerAutoWait != ENABLE)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+    }
+  }
+  
+  /* ========== Check analog watchdog 1 flag ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+    
+    /* Level out of window 1 callback */
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+    
+    /* Clear ADC Analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+   
+  }
+  
+  
+  /* ========== Check Overrun flag ========== */
+  if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)            ||
+        HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)  )
+    {
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      
+      /* Clear ADC overrun flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      
+      /* Error callback */ 
+      HAL_ADC_ErrorCallback(hadc);
+    }
+    
+    /* Clear the Overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+  
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer 
+  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param  hadc: ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels:
+  *         VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
+  *         Sampling time constraints must be respected (sampling time can be 
+  *         adjusted in function of ADC clock frequency and sampling time 
+  *         setting).
+  *         Refer to device datasheet for timings values, parameters TS_vrefint,
+  *         TS_vlcd (STM32L0x3xx only), TS_temp (values rough order: 5us to 17us).
+  *         These internal paths can be be disabled using function 
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param  hadc: ADC handle
+  * @param  sConfig: Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_RANK(sConfig->Rank));
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Management of internal measurement channels: Vbat/VrefInt/TempSensor  */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) != RESET)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+    return HAL_ERROR;
+  }
+  
+  if (sConfig->Rank != ADC_RANK_NONE)
+  {
+    /* Enable selected channels */
+    hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK);
+    
+    /* Management of internal measurement channels: Vlcd (STM32L0x3xx only)/VrefInt/TempSensor */
+    /* internal measurement paths enable: If internal channel selected, enable  */
+    /* dedicated internal buffers and path.                                     */
+    
+    /* If Temperature sensor channel is selected, then enable the internal      */
+    /* buffers and path  */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR |= ADC_CCR_TSEN;   
+      
+      /* Delay for temperature sensor stabilization time */
+      ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US);
+    }
+    
+    /* If VRefInt channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR |= ADC_CCR_VREFEN;   
+    }
+    
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+    /* If Vlcd channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR |= ADC_CCR_VLCDEN;   
+    }
+#endif
+  }
+  else
+  {
+    /* Regular sequence configuration */
+    /* Reset the channel selection register from the selected channel */
+    hadc->Instance->CHSELR &= ~((uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK));
+    
+    /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+    /* internal measurement paths disable: If internal channel selected,    */
+    /* disable dedicated internal buffers and path.                         */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR &= ~ADC_CCR_TSEN;   
+    }
+    
+    /* If VRefInt channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VREFINT) == (ADC_CHANNEL_VREFINT & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR &= ~ADC_CCR_VREFEN;   
+    }
+    
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+    /* If Vlcd channel is selected, then enable the internal buffers and path   */
+    if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_VLCD) == (ADC_CHANNEL_VLCD & ADC_CHANNEL_MASK))
+    {
+      ADC->CCR &= ~ADC_CCR_VLCDEN;   
+    }
+#endif
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive  
+  *         calls to this function can be used to reconfigure some parameters 
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure 
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   Analog watchdog thresholds can be modified while ADC conversion
+  *         is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param  hadc: ADC handle
+  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  uint32_t tmpAWDHighThresholdShifted;
+  uint32_t tmpAWDLowThresholdShifted;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+  
+  if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+  {
+    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+  }
+
+  /* Verify if threshold is within the selected ADC resolution */
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Analog watchdog channels                                              */
+  /*  - Analog watchdog thresholds                                            */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+  {
+    /* Configure ADC Analog watchdog interrupt */
+    if(AnalogWDGConfig->ITMode == ENABLE)
+    {
+      /* Enable the ADC Analog watchdog interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+    }
+    else
+    {
+      /* Disable the ADC Analog watchdog interrupt */
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+    }
+    
+    /* Configuration of analog watchdog:                                        */
+    /*  - Set the analog watchdog mode                                          */
+    /*  - Set the Analog watchdog channel (is not used if watchdog              */
+    /*    mode "all channels": ADC_CFGR1_AWD1SGL=0)                             */
+    hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL |
+                               ADC_CFGR1_AWDEN  |
+                               ADC_CFGR1_AWDCH);
+    
+    hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
+                              (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK));
+    
+    
+    /* Shift the offset in function of the selected ADC resolution: Thresholds  */
+    /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0     */
+    tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+    tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+    
+    /* Clear High & Low high thresholds */
+    hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT);
+    
+    /* Set the high threshold */
+    hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted);
+    /* Set the low threshold */
+    hadc->Instance->TR |= tmpAWDLowThresholdShifted;
+  }
+  /* If a conversion is on going on regular group, no update could be done    */
+  /* on neither of the AWD configuration structure parameters.                */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ *  @brief    ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the  
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be 
+  *         compared with states bits.
+  *         For example:                                                         
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+  *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
+  * @param  hadc: ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param  hadc: ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @note   If low power mode AutoPowerOff is enabled, power-on/off phases are
+  *         performed automatically by hardware.
+  *         In this mode, this function is useless and must not be called because 
+  *         flag ADC_FLAG_RDY is not usable.
+  *         Therefore, this function must be called under condition of
+  *         "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+    
+    /* Enable the ADC peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Delay for ADC stabilization time. */
+    ADC_DelayMicroSecond(ADC_STAB_DELAY_US);
+
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+    
+    /* Wait for ADC effectively enabled */
+    while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        
+        return HAL_ERROR;
+      }
+    }
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+  
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if (ADC_IS_ENABLE(hadc) != RESET)
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
+    {
+      /* Disable the ADC peripheral */
+      __HAL_ADC_DISABLE(hadc);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+      
+      /* Set ADC error code to ADC IP internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      
+      return HAL_ERROR;
+    }
+     
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+    
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+    {
+      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        
+        return HAL_ERROR;
+      }
+    }
+  }
+  
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Stop ADC conversion.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped to disable the ADC.
+  * @param  hadc: ADC handle
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+    
+  /* Verification if ADC is not already stopped on regular group to bypass    */
+  /* this function if not needed.                                             */
+  if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
+  {
+    
+    /* Stop potential conversion on going on regular group */
+    /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+    if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
+        HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)                  )
+    {
+      /* Stop conversions on regular group */
+      hadc->Instance->CR |= ADC_CR_ADSTP;
+    }
+    
+    /* Wait for conversion effectively stopped */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+      
+    while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
+    {
+      if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+      
+        /* Set ADC error code to ADC IP internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+  }
+   
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DMA transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Update state machine on conversion status if not in error state */
+  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going.        */
+    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
+       (hadc->Init.ContinuousConvMode == DISABLE)   )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+          
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+          
+          /* Set ADC error code to ADC IP internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+    HAL_ADC_ConvCpltCallback(hadc);
+  }
+  else
+  {
+    /* Call DMA error callback */
+    hadc->DMA_Handle->XferErrorCallback(hdma);
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Half conversion callback */
+  HAL_ADC_ConvHalfCpltCallback(hadc); 
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma: pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+  
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+  
+  /* Error callback */
+  HAL_ADC_ErrorCallback(hadc); 
+}
+
+/**
+  * @brief  Delay micro seconds 
+  * @param  microSecond : delay
+  * @retval None
+  */
+static void ADC_DelayMicroSecond(uint32_t microSecond)
+{
+  /* Compute number of CPU cycles to wait for */
+  __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000U));
+
+  while(waitLoopIndex != 0U)
+  {
+    waitLoopIndex--;
+  } 
+}
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c
new file mode 100755
index 0000000..1f260e1
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c
@@ -0,0 +1,361 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          peripheral:
+  *           + Operation functions
+  *             ++ Calibration
+  *               +++ ADC automatic self-calibration
+  *               +++ Calibration factors get or set
+  *          Other functions (generic functions) are available in file 
+  *          "stm32l0xx_hal_adc.c".
+  *
+  @verbatim
+  [..] 
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32l0xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+  /* Fixed timeout values for ADC calibration, enable settling time, disable  */
+  /* settling time.                                                           */
+  /* Values defined to be higher than worst cases: low clock frequency,       */
+  /* maximum prescaler.                                                       */
+  /* Unit: ms                                                                 */
+  #define ADC_CALIBRATION_TIMEOUT      10U      
+
+/* Delay for VREFINT stabilization time. */
+/* Internal reference startup time max value is 3ms  (refer to device datasheet, parameter TVREFINT). */
+/* Unit: ms */
+#define SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT       ((uint32_t) 3U)
+
+/* Delay for TEMPSENSOR stabilization time. */
+/* Temperature sensor startup time max value is 10us  (refer to device datasheet, parameter tSTART). */
+/* Unit: ms */
+#define SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT    ((uint32_t) 1U)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Perform the ADC calibration.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @note   Calibration factor can be read after calibration, using function
+  *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+  * @param  hadc       ADC handle
+  * @param  SingleDiff: Selection of single-ended or differential input
+  *          This parameter can be only of the following values:
+  *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tickstart = 0U;
+  uint32_t backup_setting_adc_dma_transfer = 0U; /* Note: Variable not declared as volatile because register read is already declared as volatile */
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Calibration prerequisite: ADC must be disabled. */
+  if (ADC_IS_ENABLE(hadc) == RESET)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State, 
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+    
+    /* Disable ADC DMA transfer request during calibration */
+    /* Note: Specificity of this STM32 serie: Calibration factor is           */
+    /*       available in data register and also transfered by DMA.           */
+    /*       To not insert ADC calibration factor among ADC conversion data   */
+    /*       in array variable, DMA transfer must be disabled during          */
+    /*       calibration.                                                     */
+    backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
+    
+    /* Start ADC calibration */
+    hadc->Instance->CR |= ADC_CR_ADCAL;
+    
+    tickstart = HAL_GetTick();  
+    
+    /* Wait for calibration completion */
+    while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+    {
+      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_BUSY_INTERNAL,
+                          HAL_ADC_STATE_ERROR_INTERNAL);
+        
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+        
+        return HAL_ERROR;
+      }
+    }
+    
+    /* Restore ADC DMA transfer request after calibration */
+    SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
+    
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param  hadc: ADC handle.
+  * @param  SingleDiff: This parameter can be only:
+  *           @arg ADC_SINGLE_ENDED: Channel in mode input single ended.
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
+  
+  /* Return the ADC calibration value */ 
+  return ((hadc->Instance->CALFACT) & 0x0000007FU);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param  hadc: ADC handle
+  * @param  SingleDiff: This parameter can be only:
+  *           @arg ADC_SINGLE_ENDED: Channel in mode input single ended.
+  * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
+  assert_param(IS_ADC_CALFACT(CalibrationFactor)); 
+  
+  /* Process locked */
+  __HAL_LOCK(hadc);
+  
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
+       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
+  {
+    /* Set the selected ADC calibration value */ 
+    hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
+    hadc->Instance->CALFACT |= CalibrationFactor;
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+    
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+  
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enables the buffer of Vrefint for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
+  *         This function must be called before function HAL_ADC_Init() 
+  *         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
+  *         For more details on procedure and buffer current consumption, refer to device reference manual.
+  * @note   This is functional only if the LOCK is not set.
+  * @retval None
+*/
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void)
+{
+  uint32_t tickstart = 0U;
+  
+  /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
+  
+  /* Wait for Vrefint buffer effectively enabled */
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
+  {
+    if((HAL_GetTick() - tickstart) > SYSCFG_BUF_VREFINT_ENABLE_TIMEOUT)
+    { 
+      return HAL_ERROR;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the Buffer Vrefint for the ADC.
+  * @note This is functional only if the LOCK is not set.
+  * @retval None
+  */
+void HAL_ADCEx_DisableVREFINT(void)
+{
+  /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC);
+}
+
+/**
+* @brief  Enables the buffer of temperature sensor for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode)
+*         This function must be called before function HAL_ADC_Init()
+*         (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first)
+*         For more details on procedure and buffer current consumption, refer to device reference manual.
+* @note   This is functional only if the LOCK is not set.
+* @retval None
+*/
+HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void)
+{
+  uint32_t tickstart = 0U;
+  
+  /* Enable the Buffer for the ADC by setting ENBUF_SENSOR_ADC bit in the CFGR3 register */
+  SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
+  
+  /* Wait for Vrefint buffer effectively enabled */
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+  
+  while(HAL_IS_BIT_CLR(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF))
+  {
+    if((HAL_GetTick() - tickstart) > SYSCFG_BUF_TEMPSENSOR_ENABLE_TIMEOUT)
+    { 
+      return HAL_ERROR;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the VREFINT and Sensor for the ADC.
+  * @note This is functional only if the LOCK is not set.
+  * @retval None
+  */
+void HAL_ADCEx_DisableVREFINTTempSensor(void)
+{
+  /* Disable the Vrefint by resetting ENBUF_SENSOR_ADC bit in the CFGR3 register */
+  CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
new file mode 100755
index 0000000..a72be7d
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp.c
@@ -0,0 +1,824 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_comp.c
+  * @author  MCD Application Team
+  * @brief   COMP HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the COMP peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Start/Stop operation functions in polling mode
+  *           + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
+  *           + Peripheral control functions
+  *           + Peripheral state functions
+  *         
+  @verbatim
+================================================================================
+          ##### COMP Peripheral features #####
+================================================================================
+           
+  [..]       
+      The STM32L0xx device family integrates two analog comparators instances
+      COMP1 and COMP2:
+      (#) The COMP input minus (inverting input) and input plus (non inverting input)
+          can be set to internal references or to GPIO pins
+          (refer to GPIO list in reference manual).
+  
+      (#) The COMP output level is available using HAL_COMP_GetOutputLevel()
+          and can be redirected to other peripherals: GPIO pins (in mode
+          alternate functions for comparator), timers.
+          (refer to GPIO list in reference manual).
+  
+      (#) Pairs of comparators instances can be combined in window mode
+          (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+  
+      (#) The comparators have interrupt capability through the EXTI controller
+          with wake-up from sleep and stop modes:
+          (++) COMP1 is internally connected to EXTI Line 21
+          (++) COMP2 is internally connected to EXTI Line 22
+
+          From the corresponding IRQ handler, the right interrupt source can be retrieved
+          using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
+
+            ##### How to use this driver #####
+================================================================================
+  [..]
+      This driver provides functions to configure and program the comparator instances
+      of STM32L0xx devices.
+
+      To use the comparator, perform the following steps:
+      
+      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
+      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
+           using HAL_GPIO_Init().
+      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
+           using HAL_GPIO_Init().
+      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and 
+           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+           interrupt vector using HAL_NVIC_EnableIRQ() function.
+      
+      (#) Configure the comparator using HAL_COMP_Init() function:
+      (++) Select the input minus (inverting input)
+      (++) Select the input plus (non-inverting input)
+      (++) Select the output polarity  
+      (++) Select the power mode
+      (++) Select the window mode
+      
+      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
+          to enable internal control clock of the comparators.
+          However, this is a legacy strategy. In future STM32 families,
+          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
+          Therefore, for compatibility anticipation, it is recommended to 
+          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
+      
+      (#) Reconfiguration on-the-fly of comparator can be done by calling again
+          function HAL_COMP_Init() with new input structure parameters values.
+      
+      (#) Enable the comparator using HAL_COMP_Start() function.
+      
+      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
+          to manage comparator outputs (events and output level).
+      
+      (#) Disable the comparator using HAL_COMP_Stop() function.
+      
+      (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+      
+      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
+          The only way to unlock the comparator is a device hardware reset.
+  
+  @endverbatim
+  ******************************************************************************
+
+  Table 1. COMP inputs and output for STM32L0xx devices
+  +---------------------------------------------------------+
+  |                |                |   COMP1   |   COMP2   |
+  |----------------|----------------|-----------|-----------|
+  |                | IO1            |    PA1    |    PA3    |
+  | Input plus     | IO2            |    ---    |    PA4    |
+  |                | IO3            |    ---    |    PB5    |
+  |                | IO4            |    ---    |    PB6    |
+  |                | IO5            |    ---    |    PB7    |
+  |----------------|----------------|-----------------------|
+  |                | 1/4 VrefInt    |    ---    | Available |
+  |                | 1/2 VrefInt    |    ---    | Available |
+  |                | 3/4 VrefInt    |    ---    | Available |
+  | Input minus    | VrefInt        | Available | Available |
+  |                | DAC1 channel 1 | Available | Available |
+  |                | DAC1 channel 2 | Available | Available |
+  |                | IO1            |    PA0    |    PA2    |
+  |                | IO2            |    PA5    |    PA5    |
+  |                | IO3            |    ---    |    PB3    |
+  +---------------------------------------------------------+
+  | Output         |                |  PA0  (1) |  PA2  (1) |
+  |                |                |  PA6  (1) |  PA7  (1) |
+  |                |                |  PA11 (1) |  PA12 (1) |
+  |                |                |  LPTIM    |  LPTIM    |
+  |                |                |  TIM  (2) |  TIM  (2) |
+  +-----------------------------------------------------------+
+  (1) GPIO must be set to alternate function for comparator
+  (2) Comparators output to timers is set in timers instances.
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup COMP COMP
+  * @brief COMP HAL module driver
+  * @{
+  */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup COMP_Private_Constants
+  * @{
+  */
+
+/* Delay for COMP startup time.                                               */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define COMP_DELAY_STARTUP_US             ((uint32_t) 25U)  /*!< Delay for COMP startup time */
+
+/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt,    */
+/* delay based on VrefInt startup time).                                      */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "TVREFINT").                                                     */
+/* Unit: us                                                                   */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+#define COMP_OUTPUT_LEVEL_BITOFFSET_POS  ((uint32_t)  30U)
+
+#define C_REV_ID_A              0x1000U /* Cut1.0 */
+#define C_REV_ID_Z              0x1008U /* Cut1.1 */
+#define C_REV_ID_Y              0x1003U /* Cut1.2 */
+
+#define C_DEV_ID_L073           0x447U
+#define C_DEV_ID_L053           0x417U
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and de-initialization functions. 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions to initialize and de-initialize comparators 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the COMP according to the specified
+  *         parameters in the COMP_InitTypeDef and initialize the associated handle.
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   When the LPTIM connection is enabled, the following pins LPTIM_IN1(PB5, PC0)
+            and LPTIM_IN2(PB7, PC2) should not be configured in alternate function.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+  uint32_t tmp_csr = 0U;
+  uint32_t exti_line = 0U;
+  uint32_t comp_voltage_scaler_not_initialized = 0U;
+  __IO uint32_t wait_loop_index = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
+    assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
+    assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+    assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
+    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+    assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
+    
+    if(hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hcomp->Lock = HAL_UNLOCKED;
+      
+      /* Init SYSCFG and the low level hardware to access comparators */
+      /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE()            */
+      /*       to enable internal control clock of the comparators.           */
+      /*       However, this is a legacy strategy. In future STM32 families,  */
+      /*       COMP clock enable must be implemented by user                  */
+      /*       in "HAL_COMP_MspInit()".                                       */
+      /*       Therefore, for compatibility anticipation, it is recommended   */
+      /*       to implement __HAL_RCC_SYSCFG_CLK_ENABLE()                     */
+      /*       in "HAL_COMP_MspInit()".                                       */
+      __HAL_RCC_SYSCFG_CLK_ENABLE();
+      
+      /* Init the low level hardware */
+      HAL_COMP_MspInit(hcomp);
+    }
+    
+    /* Set COMP parameters */
+    tmp_csr = (hcomp->Init.InvertingInput   |
+               hcomp->Init.OutputPol         );
+    
+    /* Configuration specific to comparator instance: COMP2 */
+    if ((hcomp->Instance) == COMP2)
+    {
+      /* Comparator input plus configuration is available on COMP2 only */
+      /* Comparator power mode configuration is available on COMP2 only */
+      tmp_csr |= (hcomp->Init.NonInvertingInput |
+                  hcomp->Init.Mode               );
+      
+      /* COMP2 specificity: when using VrefInt or subdivision of VrefInt,     */
+      /* specific path must be enabled.                                       */
+      if((hcomp->Init.InvertingInput == COMP_INPUT_MINUS_VREFINT)    ||
+         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_4VREFINT) ||
+         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_2VREFINT) ||
+         (hcomp->Init.InvertingInput == COMP_INPUT_MINUS_3_4VREFINT)   )
+      {
+        /* Memorize voltage scaler state before initialization */
+        comp_voltage_scaler_not_initialized = (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP) == 0U);
+        
+        SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP  );
+        
+        /* Delay for COMP scaler bridge voltage stabilization */
+        /* Apply the delay if voltage scaler bridge is enabled for the first time */
+        if (comp_voltage_scaler_not_initialized != 0U)
+        {
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially              */
+          /*       CPU processing cycles.                                     */
+          wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
+          while(wait_loop_index != 0U)
+          {
+            wait_loop_index--;
+          }
+        }
+      }
+    }
+    
+    /* Set comparator output connection to LPTIM */
+    if (hcomp->Init.LPTIMConnection != COMP_LPTIMCONNECTION_DISABLED)
+    {
+      /* LPTIM connexion requested on COMP1 */
+      if ((hcomp->Instance) == COMP1)
+      {
+        /* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
+        assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
+        
+        /* Note: Compatibility with previous driver version using             */
+        /* generic literal COMP_LPTIMCONNECTION_ENABLED corresponding         */
+        /* to LPTIM input 1 for COMP1.                                        */
+          tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1);
+        }
+      else
+      {
+        /* Note : COMP2 can be connected to input 1 or input 2 of LPTIM if requested */
+        assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
+        
+        switch (hcomp->Init.LPTIMConnection)
+        {
+        case  COMP_LPTIMCONNECTION_IN1_ENABLED :
+          tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
+          break;
+        case  COMP_LPTIMCONNECTION_IN2_ENABLED :
+        default :
+          /* Note: Default case for compatibility with previous driver version*/
+          /* using generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
+          /* to LPTIM input 2 for COMP2.                                      */
+          
+          /* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM input 2 */
+          if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
+                            ||
+              ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
+                            ||
+              ((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
+          {
+            assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
+            
+            /* Error: On the selected device, COMP2 cannot be connected to LPTIM input 2 */
+            status = HAL_ERROR;
+          }
+          else
+          {
+            tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
+          }
+          break;
+        }
+      }
+    }
+    
+    /* Update comparator register */
+    if ((hcomp->Instance) == COMP1)
+    {
+      MODIFY_REG(hcomp->Instance->CSR,
+                 COMP_CSR_COMP1INNSEL     | COMP_CSR_COMP1WM       |
+                 COMP_CSR_COMP1LPTIM1IN1  | COMP_CSR_COMP1POLARITY  ,
+                 tmp_csr
+                );
+    }
+    else /* Instance == COMP2 */
+    {
+      MODIFY_REG(hcomp->Instance->CSR,
+                 COMP_CSR_COMP2SPEED     | COMP_CSR_COMP2INNSEL    |
+                 COMP_CSR_COMP2INPSEL    | COMP_CSR_COMP2POLARITY  |
+                 COMP_CSR_COMP2LPTIM1IN2 | COMP_CSR_COMP2LPTIM1IN1  ,
+                 tmp_csr
+                );
+    }
+    
+    /* Set window mode */
+    /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP     */
+    /*       instances. Therefore, this function can update another COMP      */
+    /*       instance that the one currently selected.                        */
+    if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
+    {
+      SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
+    }
+    else
+    {
+      CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
+    }
+    
+    /* Get the EXTI line corresponding to the selected COMP instance */
+    exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+    
+    /* Manage EXTI settings */
+    if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
+    {
+      /* Configure EXTI rising edge */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
+      {
+        SET_BIT(EXTI->RTSR, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->RTSR, exti_line);
+      }
+      
+      /* Configure EXTI falling edge */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
+      {
+        SET_BIT(EXTI->FTSR, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->FTSR, exti_line);
+      }
+      
+      /* Clear COMP EXTI pending bit (if any) */
+      WRITE_REG(EXTI->PR, exti_line);
+      
+      /* Configure EXTI event mode */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
+      {
+        SET_BIT(EXTI->EMR, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->EMR, exti_line);
+      }
+      
+      /* Configure EXTI interrupt mode */
+      if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
+      {
+        SET_BIT(EXTI->IMR, exti_line);
+      }
+      else
+      {
+        CLEAR_BIT(EXTI->IMR, exti_line);
+      }
+    }
+    else
+    {
+      /* Disable EXTI event mode */
+      CLEAR_BIT(EXTI->EMR, exti_line);
+      
+      /* Disable EXTI interrupt mode */
+      CLEAR_BIT(EXTI->IMR, exti_line);
+    }
+    
+    /* Set HAL COMP handle state */
+    /* Note: Transition from state reset to state ready,                      */
+    /*       otherwise (coming from state ready or busy) no state update.     */
+    if (hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the COMP peripheral.
+  * @note   Deinitialization cannot be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    /* Set COMP_CSR register to reset value */
+    WRITE_REG(hcomp->Instance->CSR, 0x00000000U);
+    
+    /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+    HAL_COMP_MspDeInit(hcomp);
+    
+    /* Set HAL COMP handle state */
+    hcomp->State = HAL_COMP_STATE_RESET;
+    
+    /* Release Lock */
+    __HAL_UNLOCK(hcomp);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions 
+ *  @brief   Start-Stop operation functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start a comparator instance.
+      (+) Stop a comparator instance.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+  __IO uint32_t wait_loop_index = 0U;
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    if(hcomp->State == HAL_COMP_STATE_READY)
+    {
+      /* Enable the selected comparator */
+      SET_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN);
+      
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_BUSY;
+      
+      /* Delay for COMP startup time */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially                  */
+      /*       CPU processing cycles.                                         */
+      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000U * 2U)));
+      while(wait_loop_index != 0U)
+      {
+        wait_loop_index--;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Stop the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    if((hcomp->State == HAL_COMP_STATE_BUSY)  ||
+       (hcomp->State == HAL_COMP_STATE_READY)   )
+    {
+      /* Disable the selected comparator */
+      CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxEN);
+
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Comparator IRQ handler.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+  /* Get the EXTI line corresponding to the selected COMP instance */
+  uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+  
+  /* Check COMP EXTI flag */
+  if(READ_BIT(EXTI->PR, exti_line) != RESET)
+  {
+    /* Check whether comparator is in independent or window mode */
+    if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0)
+    {
+      /* Clear COMP EXTI line pending bit of the pair of comparators          */
+      /* in window mode.                                                      */
+      /* Note: Pair of comparators in window mode can both trig IRQ when      */
+      /*       input voltage is changing from "out of window" area            */
+      /*       (low or high ) to the other "out of window" area (high or low).*/
+      /*       Both flags must be cleared to call comparator trigger          */
+      /*       callback is called once.                                       */
+      WRITE_REG(EXTI->PR, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
+    }
+    else
+    {
+      /* Clear COMP EXTI line pending bit */
+      WRITE_REG(EXTI->PR, exti_line);
+    }
+    
+    /* COMP trigger user callback */
+    HAL_COMP_TriggerCallback(hcomp);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions 
+ *  @brief   Management functions.
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the comparators. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator configuration.
+  * @note   A system reset is required to unlock the comparator configuration.
+  * @note   Locking the comparator from reset state is possible
+  *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the COMP handle allocation and lock status */
+  if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    
+    /* Set HAL COMP handle state */
+    hcomp->State = ((HAL_COMP_StateTypeDef)(hcomp->State | COMP_STATE_BITFIELD_LOCK));
+  }
+  
+  if(status == HAL_OK)
+  {
+    /* Set the lock bit corresponding to selected comparator */
+    __HAL_COMP_LOCK(hcomp);
+  }
+  
+  return status; 
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  *         The output level depends on the selected polarity.
+  *         If the polarity is not inverted:
+  *           - Comparator output is low when the input plus is at a lower
+  *             voltage than the input minus
+  *           - Comparator output is high when the input plus is at a higher
+  *             voltage than the input minus
+  *         If the polarity is inverted:
+  *           - Comparator output is high when the input plus is at a lower
+  *             voltage than the input minus
+  *           - Comparator output is low when the input plus is at a higher
+  *             voltage than the input minus
+  * @param  hcomp  COMP handle
+  * @retval Returns the selected comparator output level: 
+  *         @arg @ref COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref COMP_OUTPUT_LEVEL_HIGH
+  *       
+  */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+  
+  return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUTVALUE)
+                    >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @brief  Comparator callback.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+  
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_TriggerCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions 
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the COMP handle state.
+  * @param  hcomp  COMP handle
+  * @retval HAL state
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+  /* Check the COMP handle allocation */
+  if(hcomp == NULL)
+  {
+    return HAL_COMP_STATE_RESET;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+  /* Return HAL COMP handle state */
+  return hcomp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c
new file mode 100755
index 0000000..eb966bf
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_comp_ex.c
@@ -0,0 +1,149 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_comp_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended COMP HAL module driver.
+  * @brief   This file provides firmware functions to manage voltage reference
+  *          VrefInt that must be specifically controled for comparator
+  *          instance COMP2.
+  @verbatim 
+  ==============================================================================
+               ##### COMP peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the COMP interface for STM32L0XX
+       devices contains the following additional features
+
+       (+) Possibility to enable or disable the VREFINT which is used as input
+           to the comparator.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+/** @addtogroup COMPEx
+  * @brief Extended COMP HAL module driver
+  * @{
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup COMP_Private_Constants
+  * @{
+  */
+
+/* Delay for COMP voltage scaler stabilization time (voltage from VrefInt,    */
+/* delay based on VrefInt startup time).                                      */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "TVREFINT").                                                     */
+/* Unit: us                                                                   */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t)3000U)  /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMPEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMPEx_Exported_Functions_Group1
+  * @brief  Extended functions to manage VREFINT for the comparator
+  *
+  * @{
+  */
+
+/**
+  * @brief  Enable Vrefint and path to comparator, used by comparator
+  *         instance COMP2 input based on VrefInt or subdivision of VrefInt.
+  * @note   The equivalent of this function is managed automatically when
+  *         using function "HAL_COMP_Init()".
+  * @note   VrefInt requires a startup time
+  *         (refer to device datasheet, parameter "TVREFINT").
+  *         This function waits for the startup time
+  *         (alternative solution: poll for bit SYSCFG_CFGR3_VREFINT_RDYF set).
+  * @retval None
+  */
+void HAL_COMPEx_EnableVREFINT(void)
+{
+  __IO uint32_t wait_loop_index = 0U;
+  
+  /* Enable the Buffer for the COMP by setting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */
+  SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP);
+  
+  /* Wait loop initialization and execution */
+  /* Note: Variable divided by 2 to compensate partially              */
+  /*       CPU processing cycles.                                     */
+  wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
+  while(wait_loop_index != 0U)
+  {
+    wait_loop_index--;
+  }
+}
+
+/**
+  * @brief  Disable Vrefint and path to comparator, used by comparator
+  *         instance COMP2 input based on VrefInt or subdivision of VrefInt.
+  * @retval None
+  */
+void HAL_COMPEx_DisableVREFINT(void)
+{
+  /* Disable the Vrefint by resetting ENBUFLP_VREFINT_COMP bit in the CFGR3 register */
+  SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+/**
+  * @}
+  */ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
new file mode 100755
index 0000000..e43a423
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c
@@ -0,0 +1,550 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CRC peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### CRC How to use this driver #####
+ ===============================================================================
+    [..]
+
+    (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+
+    (#) Initialize CRC calculator
+         (++) specify generating polynomial (IP default or non-default one)
+         (++) specify initialization value (IP default or non-default one)
+         (++) specify input data format
+         (++) specify input or output data inversion mode if any
+
+    (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the 
+        input data buffer starting with the previously computed CRC as 
+        initialization value
+
+    (#) Use HAL_CRC_Calculate() function to compute the CRC value of the 
+        input data buffer starting with the defined initialization value 
+        (default or non-default) to initiate CRC calculation
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/** @addtogroup CRC
+  * @brief CRC HAL module driver
+  * @{
+  */
+
+/** @addtogroup CRC_Private
+  * @{
+  */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  
+      This section provides functions allowing to:
+
+      (#) Initialize the CRC according to the specified parameters 
+          in the CRC_InitTypeDef and create the associated handle
+
+      (#) DeInitialize the CRC peripheral
+
+      (#) Initialize the CRC MSP
+
+      (#) DeInitialize CRC MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and creates the associated handle.
+  * @param  hcrc: CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+   
+  if(hcrc->State == HAL_CRC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcrc->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  /* check whether or not non-default generating polynomial has been 
+   * picked up by user */
+  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); 
+  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+  {
+    /* initialize IP with default generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);  
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+  }
+  else
+  {
+    /* initialize CRC IP with generating polynomial defined by user */
+    assert_param(IS_CRC_POL_LENGTH(hcrc->Init.CRCLength));
+    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  
+  /* check whether or not non-default CRC initial value has been 
+   * picked up by user */
+  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+  {
+    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);  
+  }
+  else
+  {
+    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+  }
+  
+
+  /* set input data inversion mode */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); 
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 
+  
+  /* set output data inversion mode */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); 
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);  
+  
+  /* makes sure the input data format (bytes, halfwords or words stream)
+   * is properly specified by user */
+  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the CRC peripheral. 
+  * @param  hcrc: CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{ 
+  /* Check the CRC handle allocation */
+  if(hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+  
+  /* Check the CRC peripheral state */
+  if(hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+  
+  /* Reset IDR register content */
+  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc: CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the CRC MSP.
+  * @param  hcrc: CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
+   */
+}
+  
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Exported_Functions_Group2
+ *  @brief    management functions. 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+
+      (#) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          using combination of the previous CRC value and the new one.
+          
+          or
+          
+      (#) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**                  
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.  
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat.              
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0U; /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+  
+  /* Process locked */
+  __HAL_LOCK(hcrc); 
+    
+  /* Change CRC peripheral state */  
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:  
+      /* Enter Data to the CRC calculator */
+      for(index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_BYTES: 
+      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_HALFWORDS: 
+      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+      break;
+    default:
+      break;  
+  }
+  
+  /* Change CRC peripheral state */    
+  hcrc->State = HAL_CRC_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+  
+  /* Return the CRC computed value */ 
+  return temp;
+}
+
+
+/**                  
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.  
+  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the  
+  *        handle field hcrc->InputDataFormat. 
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */  
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0U; /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+    
+  /* Process locked */
+  __HAL_LOCK(hcrc); 
+  
+  /* Change CRC peripheral state */  
+  hcrc->State = HAL_CRC_STATE_BUSY;
+  
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is 
+  *  written in hcrc->Instance->DR) */
+  __HAL_CRC_DR_RESET(hcrc);
+  
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:  
+      /* Enter 32-bit input data to the CRC calculator */
+      for(index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_BYTES: 
+      /* Specific 8-bit input data handling  */
+      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+      break;
+      
+    case CRC_INPUTDATA_FORMAT_HALFWORDS: 
+      /* Specific 16-bit input data handling  */
+      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+      break;
+    default:
+      break;
+  }
+
+  /* Change CRC peripheral state */    
+  hcrc->State = HAL_CRC_STATE_READY; 
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+  
+  /* Return the CRC computed value */ 
+  return temp;
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Exported_Functions_Group3
+ *  @brief    Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the CRC state.
+  * @param  hcrc: CRC handle
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Private
+  * @{
+  */
+/**             
+  * @brief  Enter 8-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.  
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer
+  * @param  BufferLength: input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0U; /* input data buffer index */
+  
+   /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+    * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+    * handling by the IP */
+   for(i = 0U; i < (BufferLength/4U); i++)
+   {
+      hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1U]<<16U) | ((uint32_t)pBuffer[4U*i+2U]<<8U) | (uint32_t)pBuffer[4U*i+3U];
+   }
+   /* last bytes specific handling */
+   if ((BufferLength%4U) != 0U)
+   {
+     if  (BufferLength%4U == 1U)
+     {
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i];
+     }
+     if  (BufferLength%4U == 2U)
+     {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U];
+     }
+     if  (BufferLength%4U == 3U)
+     {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U];
+       *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i+2U];
+     }
+   }
+  
+  /* Return the CRC computed value */ 
+  return hcrc->Instance->DR;
+}
+
+/**             
+  * @brief  Enter 16-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.  
+  * @param  hcrc: CRC handle
+  * @param  pBuffer: pointer to the input data buffer
+  * @param  BufferLength: input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */  
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+   uint32_t i = 0U;  /* input data buffer index */
+  
+  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure 
+   * a correct type handling by the IP */
+  for(i = 0U; i < (BufferLength/2U); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1U];
+  }
+  if ((BufferLength%2U) != 0U)
+  {
+       *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2U*i];
+  }
+   
+  /* Return the CRC computed value */ 
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
new file mode 100755
index 0000000..1f29160
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c
@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_crc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended CRC HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CRC peripheral:
+  *           + Initialization/de-initialization functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### CRC specific features #####
+  ==============================================================================
+  [..] 
+  (#) Polynomial configuration.
+  (#) Input data reverse mode.
+  (#) Output data reverse mode.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @brief CRC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+ *  @brief    Extended CRC features functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### CRC Extended features functions #####
+ ===============================================================================  
+    [..]
+This subsection provides function allowing to:
+      (+) Set CRC polynomial if different from default one.
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the CRC polynomial if different from default one.
+  * @param  hcrc: CRC handle
+  * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
+  *         This parameter is written in normal representation, e.g.
+  *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 
+  *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     
+  * @param  PolyLength: CRC polynomial length 
+  *         This parameter can be one of the following values:
+  *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
+  *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
+  *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
+  *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)                
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+  /* Check the parameters */
+  assert_param(IS_CRC_POL_LENGTH(PolyLength));
+  
+  /* check polynomial definition vs polynomial size:
+   * polynomial length must be aligned with polynomial
+   * definition. HAL_ERROR is reported if Pol degree is 
+   * larger than that indicated by PolyLength.
+   * Look for MSB position: msb will contain the degree of
+   *  the second to the largest polynomial member. E.g., for
+   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+  while (((Pol & (1U << msb)) == 0) && (msb-- > 0)){}
+
+  switch (PolyLength)
+  {
+    case CRC_POLYLENGTH_7B:
+      if (msb >= HAL_CRC_LENGTH_7B) 
+      {
+        return  HAL_ERROR;
+      }
+      break;
+    case CRC_POLYLENGTH_8B:
+      if (msb >= HAL_CRC_LENGTH_8B)
+      {
+        return  HAL_ERROR;
+      }      
+      break;
+    case CRC_POLYLENGTH_16B:
+      if (msb >= HAL_CRC_LENGTH_16B)
+      {
+        return  HAL_ERROR;
+      }      
+      break;
+    case CRC_POLYLENGTH_32B:
+      /* no polynomial definition vs. polynomial length issue possible */
+      break; 
+    default:
+      break;                  
+  }
+
+  /* set generating polynomial */
+  WRITE_REG(hcrc->Instance->POL, Pol);
+  
+  /* set generating polynomial size */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);  
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Input data mode.
+  * @param  hcrc: CRC handle
+  * @param  InputReverseMode: Input Data inversion mode
+  *         This parameter can be one of the following values:
+  *          @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
+  *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
+  *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
+  *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal              
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{  
+  /* Check the parameters */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set input data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);    
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Output data mode.
+  * @param  hcrc: CRC handle
+  * @param  OutputReverseMode: Output Data inversion mode
+  *         This parameter can be one of the following values:
+  *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
+  *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+  * @retval HAL status
+  */                                   
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+  
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set output data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); 
+      
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
new file mode 100755
index 0000000..2e23f51
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c
@@ -0,0 +1,2177 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_cryp.c
+  * @author  MCD Application Team
+  * @brief   CRYP HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Cryptography (CRYP) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Processing functions by algorithm using polling mode
+  *           + Processing functions by algorithm using interrupt mode
+  *           + Processing functions by algorithm using DMA mode
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The CRYP HAL driver can be used as follows:
+
+      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+         (##) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE()
+         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+             (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+             (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+             (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
+             (+) Enable the DMA1 interface clock using 
+                 (++) __HAL_RCC_DMA1_CLK_ENABLE()
+             (+) Configure and enable two DMA Channels one for managing data transfer from
+                 memory to peripheral (input channel) and another channel for managing data
+                 transfer from peripheral to memory (output channel)
+             (+) Associate the initialized DMA handle to the CRYP DMA handle
+                 using  __HAL_LINKDMA()
+             (+) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream.
+                 (++) HAL_NVIC_SetPriority()
+                 (++) HAL_NVIC_EnableIRQ()
+    
+      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
+         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
+         (##) The encryption/decryption key.
+         (##) The initialization vector (counter). It is not used ECB mode.
+    
+      (#)Three processing (encryption/decryption) functions are available:
+         (##) Polling mode: encryption and decryption APIs are blocking functions
+              i.e. they process the data and wait till the processing is finished
+              e.g. HAL_CRYP_AESCBC_Encrypt()
+         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+              i.e. they process the data under interrupt
+              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+         (##) DMA mode: encryption and decryption APIs are not blocking functions
+              i.e. the data transfer is ensured by DMA
+              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+    
+      (#)When the processing function is called for the first time after HAL_CRYP_Init()
+         the CRYP peripheral is initialized and processes the buffer in input.
+         At second call, the processing function performs an append of the already
+         processed buffer.
+         When a new data block is to be processed, call HAL_CRYP_Init() then the
+         processing function.
+         
+      (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+#if defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @brief CRYP HAL module driver.
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup CRYP_Private CRYP Private
+  * @{
+  */
+
+#define  CRYP_ALGO_CHAIN_MASK         (AES_CR_MODE | AES_CR_CHMOD)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @addtogroup CRYP_Private
+  * @{
+  */
+
+static HAL_StatusTypeDef  CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
+static void               CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
+static void               CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
+static HAL_StatusTypeDef  CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+static void               CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void               CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void               CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void               CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup CRYP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRYP according to the specified parameters 
+          in the CRYP_InitTypeDef and creates the associated handle
+      (+) DeInitialize the CRYP peripheral
+      (+) Initialize the CRYP MSP
+      (+) DeInitialize CRYP MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP according to the specified
+  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{ 
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
+  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+  
+  if(hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRYP_MspInit(hcryp);
+  }
+  
+  /* Check if AES already enabled */
+  if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN))
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;  
+
+    /* Set the data type*/
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+    
+    /* Reset CrypInCount and CrypOutCount */
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Set the default CRYP phase */
+    hcryp->Phase = HAL_CRYP_PHASE_READY;
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
+    /* enabled is forbidden to avoid unpredictable AES behavior.*/
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+
+}
+
+/**
+  * @brief  DeInitializes the CRYP peripheral. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_BUSY;
+  
+  /* Set the default CRYP phase */
+  hcryp->Phase = HAL_CRYP_PHASE_READY;
+  
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0U;
+  hcryp->CrypOutCount = 0U;
+  
+  /* Disable the CRYP Peripheral Clock */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_CRYP_MspDeInit(hcryp);
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed, 
+            the HAL_CRYP_MspInit can be implemented in the user file */
+}
+
+/**
+  * @brief  DeInitializes CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed, 
+            the HAL_CRYP_MspDeInit can be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group2
+ *  @brief   processing functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### AES processing functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Encrypt plaintext using AES algorithm in different chaining modes
+      (+) Decrypt cyphertext using AES algorithm in different chaining modes
+    [..]  Three processing functions are available:
+      (+) Polling mode
+      (+) Interrupt mode
+      (+) DMA mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+
+  /* Check that data aligned on u32 and Size multiple of 16*/
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if(hcryp->State != HAL_CRYP_STATE_RESET)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+	
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if(hcryp->State != HAL_CRYP_STATE_RESET)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CBC mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
+  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if(hcryp->State != HAL_CRYP_STATE_RESET)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Write Plain Data and Get Cypher Data */
+    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if(hcryp->State != HAL_CRYP_STATE_RESET)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Write Cypher Data and Get Plain Data */
+    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if(hcryp->State != HAL_CRYP_STATE_RESET)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Write Cypher Data and Get Plain Data */
+    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
+  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Timeout: Specify Timeout value   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+{  
+  /* Process Locked */
+  __HAL_LOCK(hcryp);
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if initialization phase has already been performed */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.pKey);
+    
+    /* Reset the CHMOD & MODE bits */
+    CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+    
+    /* Set the CRYP peripheral in AES CTR decryption mode */
+    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+    
+    /* Set the Initialization Vector */
+    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Set the phase */
+    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+  }
+  
+  /* Write Cypher Data and Get Plain Data */
+  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+  
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hcryp);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CBC mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+   
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pPlainData;
+    hcryp->pCrypOutBuffPtr = pCypherData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;    
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;    
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    /* Get the buffer addresses and sizes */
+    hcryp->CrypInCount = Size;
+    hcryp->pCrypInBuffPtr = pCypherData;
+    hcryp->pCrypOutBuffPtr = pPlainData;
+    hcryp->CrypOutCount = Size;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CTR decryption mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC);
+    
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+    
+    /* Get the last input data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;    
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Set the CRYP peripheral in AES ECB mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {  
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Set the CRYP peripheral in AES CBC mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+{
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pPlainData;
+    outputaddr = (uint32_t)pCypherData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{  
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Reset the CHMOD & MODE bits */
+      CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK);
+      
+      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
+  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
+  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+{  
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+  
+  /* Check that data aligned on u32 */
+  if((((uint32_t)pPlainData & (uint32_t)0x00000003U) != 0U) || (((uint32_t)pCypherData & (uint32_t)0x00000003U) != 0U) || ((Size & (uint16_t)0x000FU) != 0U))
+  {
+    /* Process Locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  
+  /* Check if HAL_CRYP_Init has been called */
+  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcryp);
+    
+    inputaddr  = (uint32_t)pCypherData;
+    outputaddr = (uint32_t)pPlainData;
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+    
+    /* Check if initialization phase has already been performed */
+    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+    {
+      /* Set the key */
+      CRYP_SetKey(hcryp, hcryp->Init.pKey);
+      
+      /* Set the CRYP peripheral in AES CTR mode */
+      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
+      
+      /* Set the Initialization Vector */
+      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
+      
+      /* Set the phase */
+      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    }
+    
+    /* Set the input and output addresses and start DMA transfer */ 
+    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Release Lock */
+    __HAL_UNLOCK(hcryp);
+  
+    return HAL_ERROR;   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+ *  @brief   DMA callback functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### DMA callback functions  #####
+  ==============================================================================  
+    [..]  This section provides DMA callback functions:
+      (+) DMA Input data transfer complete
+      (+) DMA Output data transfer complete
+      (+) DMA error
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  CRYP error callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed, 
+            the HAL_CRYP_ErrorCallback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Input transfer completed callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed, 
+            the HAL_CRYP_InCpltCallback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Output transfer completed callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function should not be modified; when the callback is needed, 
+            the HAL_CRYP_OutCpltCallback can be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group4
+ *  @brief   CRYP IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                ##### CRYP IRQ handler management #####
+  ==============================================================================  
+[..]  This section provides CRYP IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles CRYP interrupt request.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check if error occurred*/
+  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET)
+  {
+    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET)
+    {
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR);
+    }
+    
+    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET)
+    {
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR);
+    }
+    
+    if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_CCF) != RESET)
+    {
+      __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CLEARFLAG_CCF);
+    }
+    
+    hcryp->State= HAL_CRYP_STATE_ERROR;
+    /* Disable Computation Complete Interrupt */
+    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
+    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
+    
+    HAL_CRYP_ErrorCallback(hcryp);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    return;
+  }
+  
+  /* Check if computation complete interrupt was enabled*/
+  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET)
+  {
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
+  
+    CRYP_EncryptDecrypt_IT(hcryp);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group5
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the CRYP state.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL state
+  */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Private
+  * @{
+  */
+
+/**
+  * @brief  IT function called under interruption context to continue encryption or decryption
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t inputaddr = 0U, outputaddr = 0U;
+
+  /* Get the last Output data adress */
+  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+  
+  /* Read the Output block from the Output Register */
+  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+  outputaddr+=4U;
+  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+  outputaddr+=4U;
+  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+  outputaddr+=4U;
+  *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+  
+  hcryp->pCrypOutBuffPtr += 16U;
+  hcryp->CrypOutCount -= 16U;
+  
+  /* Check if all input text is encrypted or decrypted */
+  if(hcryp->CrypOutCount == 0U)
+  {
+    /* Disable Computation Complete Interrupt */
+    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC);
+    __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+    
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+    
+    /* Call computation complete callback */
+    HAL_CRYPEx_ComputationCpltCallback(hcryp);
+  }
+  else /* Process the rest of input text */
+  {
+    /* Get the last Intput data adress */
+    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+    
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    hcryp->pCrypInBuffPtr += 16U;
+    hcryp->CrypInCount -= 16U;      
+  }
+  return HAL_OK;
+}
+/**
+  * @brief  DMA CRYP Input Data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for input request  */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+  
+  /* Call input data transfer complete callback */
+  HAL_CRYP_InCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP Output Data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
+     in the DMACR register */
+  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
+
+  /* Clear CCF Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
+
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+  
+  /* Call output data transfer complete callback */
+  HAL_CRYP_OutCpltCallback(hcryp);
+}
+
+/**
+  * @brief  DMA CRYP communication error callback. 
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  hcryp->State= HAL_CRYP_STATE_ERROR;
+  HAL_CRYP_ErrorCallback(hcryp);
+}
+
+/**
+  * @brief  Writes the Key in Key registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Key: Pointer to Key buffer
+  * @note Key must be written as little endian.
+  *         If Key pointer points at address n, 
+  *         n[15:0] contains key[96:127], 
+  *         (n+4)[15:0] contains key[64:95], 
+  *         (n+8)[15:0] contains key[32:63] and 
+  *         (n+12)[15:0] contains key[0:31]
+  * @retval None
+  */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
+{  
+  uint32_t keyaddr = (uint32_t)Key;
+  
+  hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4U;
+  hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4U;
+  hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4U;
+  hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+}
+
+/**
+  * @brief  Writes the InitVector/InitCounter in IV registers. 
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  InitVector: Pointer to InitVector/InitCounter buffer
+  * @note Init Vector must be written as little endian.
+  *         If Init Vector pointer points at address n, 
+  *         n[15:0] contains Vector[96:127], 
+  *         (n+4)[15:0] contains Vector[64:95], 
+  *         (n+8)[15:0] contains Vector[32:63] and 
+  *         (n+12)[15:0] contains Vector[0:31]
+  * @retval None
+  */
+static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
+{
+  uint32_t ivaddr = (uint32_t)InitVector;
+  
+  hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4U;
+  hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4U;
+  hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr+=4U;
+  hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+}
+
+/**
+  * @brief  Process Data: Writes Input data in polling mode and reads the output data
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the Input buffer
+  * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
+  * @param  Output: Pointer to the returned buffer
+  * @param  Timeout: Specify Timeout value  
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+  
+  uint32_t index = 0U;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  
+  for(index=0U; (index < Ilength); index += 16U)
+  {
+    /* Write the Input block in the Data Input register */
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+    inputaddr+=4U;
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+    
+    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+    {    
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
+          /* Change state */
+          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+          
+          /* Process Unlocked */          
+          __HAL_UNLOCK(hcryp);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF);
+    
+    /* Read the Output block from the Data Output Register */
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4U;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4U;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4U;
+    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+    outputaddr+=4U;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the DMA configuration and start the DMA transfer
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  inputaddr: address of the Input buffer
+  * @param  Size: Size of the Input buffer, must be a multiple of 16.
+  * @param  outputaddr: address of the Output buffer
+  * @retval None
+  */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+  
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+  /* Set the DMA error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+  /* Enable the DMA In DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);
+
+  /* Enable the DMA Out DMA Stream */
+  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);
+
+  /* Enable In and Out DMA requests */
+  SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
new file mode 100755
index 0000000..4ff7316
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp_ex.c
@@ -0,0 +1,118 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_cryp_ex.c
+  * @author  MCD Application Team
+  * @brief   CRYPEx HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Cryptography (CRYP) extension peripheral:
+  *           + Computation completed callback.
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+#if defined (STM32L021xx) ||defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+
+/** @addtogroup CRYPEx
+  * @brief CRYP HAL Extended module driver.
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+ *  @brief    Extended features functions. 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ =============================================================================== 
+    [..]  This section provides callback functions:
+      (+) Computation completed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Computation completed callbacks.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_ComputationCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+#endif /* STM32L021xx || STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c
new file mode 100755
index 0000000..80e6252
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac.c
@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_dac.c
+  * @author  MCD Application Team
+  * @brief   DAC HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions      
+  *     
+  *
+  @verbatim
+  ==============================================================================
+                      ##### DAC Peripheral features #####
+  ==============================================================================
+    [..]        
+      *** DAC Channels ***
+      ====================
+    [..]  
+    STM32F0 devices integrates no, one or two 12-bit Digital Analog Converters.
+    STM32L05x & STM32L06x devices have one converter (channel1)
+    STM32L07x & STM32L08x devices have two converters (i.e. channel1 & channel2)
+
+    When 2 converters are present (i.e. channel1 & channel2)  they 
+    can be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output
+      (#) DAC channel2 with DAC_OUT2 (PA5) as output (STM32L07x/STM32L08x only)
+      (#) Channel1 & channel2 can be used independently or simultaneously in dual mode (STM32L07x/STM32L08x only)
+  
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+    [..]
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+          The used pin (GPIOx_Pin9) must be configured in input mode.
+
+      (#) Timers TRGO: 
+          STM32L05x/STM32L06x : TIM2, TIM6 and TIM21
+          STM32L07x/STM32L08x : TIM2, TIM3, TIM6, TIM7 and TIM21
+          (DAC_Trigger_T2_TRGO, DAC_Trigger_T6_TRGO...)
+
+      (#) Software using DAC_Trigger_Software
+
+      *** DAC Buffer mode feature ***
+      ===============================
+      [..] 
+      Each DAC channel integrates an output buffer that can be used to
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use
+      sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+      [..]
+      (@) Refer to the device datasheet for more details about output
+          impedance value with and without output buffer.
+
+       *** DAC wave generation feature ***
+       ===================================
+       [..]
+       Both DAC channels can be used to generate
+         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
+         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
+
+       *** DAC data format ***
+       =======================
+       [..]
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_ALIGN_8B_R
+         (#) 12-bit left alignment using DAC_ALIGN_12B_L
+         (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+       *** DAC data value to voltage correspondence ***
+       ================================================
+       [..]
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation: 
+       DAC_OUTx = VREF+ * DOR / 4095
+       with  DOR is the Data Output Register
+          VEF+ is the input voltage reference (refer to the device datasheet)
+        e.g. To set DAC_OUT1 to 0.7V, use
+          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+       *** DMA requests  ***
+       =====================
+       [..]
+       A DMA1 request can be generated when an external trigger (but not
+       a software trigger) occurs if DMA1 requests are enabled using
+       HAL_DAC_Start_DMA()
+       [..]
+       DMA1 requests are mapped as following:
+         (#) DAC channel1 : mapped on DMA1 Request9 channel2 which must be
+             already configured
+         (#) DAC channel2 : mapped on DMA1 Request15 channel4 which must be 
+             already configured (STM32L07x/STM32L08x only)
+       
+    -@- For Dual mode (STM32L07x/STM32L08x only) and specific signal Triangle and noise generation please 
+        refer to Extension Features Driver description        
+
+
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using HAL_DAC_Init()
+      (+) Configure DAC_OUT1: PA4 in analog mode.
+      (+) Configure DAC_OUT2: PA5 in analog mode (STM32L07x/STM32L08x only).
+      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start() 
+       (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+       (+) Stop the DAC peripheral using HAL_DAC_Stop()
+       
+     *** DMA mode IO operation ***    
+     ==============================
+     [..]    
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
+           of data to be transferred at each end of conversion
+       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
+           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+           HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2()  
+           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2
+           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+     *** DAC HAL driver macros list ***
+     ============================================= 
+     [..]
+       Below the list of most used macros in DAC HAL driver.
+       
+      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+      
+     [..]
+      (@) You can refer to the DAC HAL driver header file for more useful macros  
+   
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+#ifdef HAL_DAC_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @brief DAC driver modules
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DAC.
+      (+) De-initialize the DAC.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  if(hdac->State == HAL_DAC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hdac->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_DAC_MspInit(hdac);
+  }
+
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+  /* Check DAC handle */
+  if(hdac == NULL)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_DAC_MspDeInit(hdac);
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the DAC MSP.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.  
+  * @retval None
+  */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ *  @brief    IO operation functions 
+ *
+@verbatim
+  ==============================================================================
+             ##### IO operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion (STM32L07xx/STM32L08xx only)
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+  UNUSED(Channel);
+
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel using DMA.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+  UNUSED(Channel);
+  UNUSED(pData);
+  UNUSED(Length);
+  UNUSED(Alignment);
+
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+  UNUSED(Channel);
+
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @retval The selected DAC channel data output value.
+  */
+__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+  UNUSED(Channel);
+
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+
+  /* Return function status */
+  return 0U;
+}
+
+/**
+  * @brief  Handles DAC interrupt request
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+
+}
+
+/**
+  * @brief  Conversion complete callback in non blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel1.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+  
+/** @addtogroup DAC_Exported_Functions_Group3
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels.
+      (+) Set the specified data holding register value for DAC channel.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC configuration structure.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+  uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Get the DAC CR value */
+  tmpreg1 = hdac->Instance->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << Channel;
+  /* Write to DAC CR */
+  hdac->Instance->CR = tmpreg1;
+  /* Disable wave generation */
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << Channel));
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ *  @brief   Peripheral State and Errors functions 
+ *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Errors functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DAC state.
+      (+) Check the DAC Errors.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the DAC state
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL state
+  */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+  /* Return DAC state */
+  return hdac->State;
+}
+
+
+/**
+  * @brief  Return the DAC error code
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval DAC Error Code
+  */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+  return hdac->ErrorCode;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @param  Alignment: Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+  UNUSED(Channel);
+  UNUSED(Alignment);
+  UNUSED(Data);
+  /* Note : This function is defined into this file for library reference. */
+  /*        Function content is located into file stm32l0xx_hal_dac_ex.c   */
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_DAC_MODULE_ENABLED */
+#endif /* !STM32L011xx && STM32L021xx && !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx&& !STM32L071xx&& !STM32L081xx*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c
new file mode 100755
index 0000000..bbf782f
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c
@@ -0,0 +1,1049 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended DAC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of DAC extension peripheral:
+  *           + Extended features functions
+  *     
+  *     
+  @verbatim
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+  
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+#ifdef HAL_DAC_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DACEx DACEx
+  * @brief DAC driver modules
+  * @{
+  */
+
+/** @addtogroup DACEx_Private
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
+#endif
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ *  @brief    Extended features functions 
+ *
+
+  * @{
+  */
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+  uint32_t tmp = 0U;
+  
+  tmp |= hdac->Instance->DOR1;
+  
+  tmp |= hdac->Instance->DOR2 << 16U;
+  
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+#endif
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @param  Amplitude: Select max triangle amplitude. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+ 
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC. 
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only)
+  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+/* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{  
+  uint32_t data = 0U, tmp = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8U) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16U) | Data1;
+  }
+  
+  tmp = (uint32_t)hdac->Instance;
+  tmp += DAC_DHR12RD_ALIGNEMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Conversion complete callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  uint32_t tmp1 = 0U, tmp2 = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+    /* Check if software trigger enabled */
+    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+    }
+  }
+  else
+  {
+    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
+    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
+    /* Check if software trigger enabled */
+    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+    {
+      /* Enable the selected DAC software conversion*/
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+    }
+  }
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel using DMA.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Set the DMA transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+    /* Set the DMA half transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+    /* Set the DMA error callback for channel1 */
+    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+    /* Enable the selected DAC channel1 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+       
+    /* Case of use of channel 1 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+        break;
+      default:
+        break;
+    }
+    UNUSED(tmpreg);		/* avoid warning on tmpreg affectation with stupid compiler */
+  }
+  else
+  {
+    /* Set the DMA transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+    /* Set the DMA half transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+    
+    /* Set the DMA error callback for channel2 */
+    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+    /* Enable the selected DAC channel2 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+    /* Case of use of channel 2 */
+    switch(Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+        break;
+      case DAC_ALIGN_8B_R:
+        /* Get DHR8R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+        break;
+      default:
+        break;
+    }
+  }
+  
+  /* Enable the DMA Stream */
+  if(Channel == DAC_CHANNEL_1)
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  } 
+  else
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+    
+    /* Enable the DMA Stream */
+    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+  }
+  
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Disable the selected DAC channel DMA request */
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
+
+  /* Disable the Peripharal */
+  __HAL_DAC_DISABLE(hdac, Channel);
+
+  /* Disable the DMA Channel */
+  /* Channel1 is used */
+  if(Channel == DAC_CHANNEL_1)
+  { 
+    status = HAL_DMA_Abort(hdac->DMA_Handle1);
+  }
+  else /* Channel2 is used for */
+  { 
+    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
+  }
+
+  /* Check if DMA Channel effectively disabled */
+  if(status != HAL_OK)
+  {
+    /* Update DAC state machine to error */
+    hdac->State = HAL_DAC_STATE_ERROR;
+  }
+  else
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Returns the DAC channel data output register value */
+  if(Channel == DAC_CHANNEL_1)
+  {
+    return hdac->Instance->DOR1;
+  }
+  else
+  {
+    return hdac->Instance->DOR2;
+  }
+}
+
+/**
+  * @brief  Handles DAC interrupt request
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+  /* Check underrun flag of DAC channel 1 */
+  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+  {
+    /* Change DAC state to error state */
+    hdac->State = HAL_DAC_STATE_ERROR;
+
+    /* Set DAC error code to chanel1 DMA underrun error */
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+    /* Clear the underrun flag */
+    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+    /* Disable the selected DAC channel1 DMA request */
+    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+    /* Error callback */
+    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+  }
+  
+  /* Check underrun flag of DAC channel 2 */
+  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+  {
+    /* Change DAC state to error state */
+    hdac->State = HAL_DAC_STATE_ERROR;
+    
+    /* Set DAC error code to channel2 DMA underrun error */
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
+    
+    /* Clear the underrun flag */
+    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+    
+    /* Disable the selected DAC channel1 DMA request */
+    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+      
+    /* Error callback */ 
+    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+  }  
+}
+
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Alignment: Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+  __IO uint32_t tmp = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)hdac->Instance; 
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
+  }
+  else
+  {
+    tmp += DAC_DHR12R2_ALIGNEMENT(Alignment);
+  }
+
+  /* Set the DAC channel selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+
+  /* Return function status */
+  return HAL_OK;
+}
+#else /* All products with only one channel */
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  uint32_t tmp1 = 0U, tmp2 = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+
+  tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+  tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+  /* Check if software trigger enabled */
+  if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
+  {
+    /* Enable the selected DAC software conversion */
+    SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+  }
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel using DMA.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @param  pData: The destination peripheral Buffer address.
+  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment: Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Set the DMA transfer complete callback for channel1 */
+  hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+  /* Set the DMA half transfer complete callback for channel1 */
+  hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+  /* Set the DMA error callback for channel1 */
+  hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+  /* Enable the selected DAC channel1 DMA request */
+  SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+     
+  /* Case of use of channel 1 */
+  switch(Alignment)
+  {
+    case DAC_ALIGN_12B_R:
+      /* Get DHR12R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+      break;
+    case DAC_ALIGN_12B_L:
+      /* Get DHR12L1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+      break;
+    case DAC_ALIGN_8B_R:
+      /* Get DHR8R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+      break;
+    default:
+      break;
+  }
+  UNUSED(tmpreg);		/* avoid warning on tmpreg affectation with stupid compiler */
+  
+  /* Enable the DMA Stream */
+  /* Enable the DAC DMA underrun interrupt */
+  __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+  
+  /* Enable the DMA Stream */
+  HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  
+  /* Enable the Peripharal */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Disable the selected DAC channel DMA request */
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel));
+
+  /* Disable the Peripharal */
+  __HAL_DAC_DISABLE(hdac, Channel);
+
+  /* Disable the DMA Channel */
+  status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+  /* Check if DMA Channel effectively disabled */
+  if(status != HAL_OK)
+  {
+    /* Update DAC state machine to error */
+    hdac->State = HAL_DAC_STATE_ERROR;
+  }
+  else
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  
+  /* Returns the DAC channel data output register value */
+  return hdac->Instance->DOR1;
+}
+
+/**
+  * @brief  Handles DAC interrupt request
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+{
+  /* Check underrun flag of DAC channel 1 */
+  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+  {
+    /* Change DAC state to error state */
+    hdac->State = HAL_DAC_STATE_ERROR;
+
+    /* Set DAC error code to chanel1 DMA underrun error */
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+
+    /* Clear the underrun flag */
+    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+    /* Disable the selected DAC channel1 DMA request */
+    CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+    /* Error callback */
+    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  * @param  Alignment: Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+  __IO uint32_t tmp = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)hdac->Instance; 
+  tmp += DAC_DHR12R1_ALIGNEMENT(Alignment);
+
+  /* Set the DAC channel selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#endif  /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Private
+  * @{
+  */
+#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx)
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+}
+
+/**
+  * @brief  DMA error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DACEx_ErrorCallbackCh2(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DAC_ConvCpltCallbackCh1(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  /* Conversion complete callback */
+  HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+  * @brief  DMA error callback
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+  HAL_DAC_ErrorCallbackCh1(hdac);
+
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_DAC_MODULE_ENABLED */
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c
new file mode 100755
index 0000000..fccaf00
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_firewall.c
@@ -0,0 +1,305 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_firewall.c
+  * @author  MCD Application Team
+  * @brief   FIREWALL HAL module driver.
+  *          This file provides firmware functions to manage the Firewall
+  *          Peripheral initialization and enabling.
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver ##### 
+ ===============================================================================
+  [..]
+    The FIREWALL HAL driver can be used as follows:
+              
+    (#) Declare a FIREWALL_InitTypeDef initialization structure.
+  
+    (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall
+
+    (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API
+    
+    (#) To ensure that any code executed outside the protected segment closes the
+        FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling 
+        __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment
+        or
+        HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment
+        after HAL_FIREWALL_Config() call.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+
+/** @addtogroup FIREWALL
+  * @brief HAL FIREWALL module driver
+  * @{
+  */
+
+    
+
+/** @addtogroup FIREWALL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FIREWALL_Exported_Functions_Group1
+  * @brief    Initialization and Configuration Functions 
+  *
+@verbatim    
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides the functions allowing to initialize the Firewall.
+    Initialization is done by HAL_FIREWALL_Config(): 
+
+      (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro.
+           
+      (+) Set the protected code segment address start and length.
+          
+      (+) Set the protected non-volatile and/or volatile data segments 
+          address starts and lengths if applicable.          
+          
+      (+) Set the volatile data segment execution and sharing status.
+      
+      (+) Length must be set to 0 for an unprotected segment.      
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters.
+  * @param fw_init: Firewall initialization structure
+  * @note  The API returns HAL_ERROR if the Firewall is already enabled.     
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init)
+{
+  /* Check the Firewall initialization structure allocation */
+  if(fw_init == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Enable Firewall clock */
+  __HAL_RCC_FIREWALL_CLK_ENABLE();
+
+  /* Make sure that Firewall is not enabled already */
+  if (__HAL_FIREWALL_IS_ENABLED() != RESET)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check Firewall configuration addresses and lengths when segment is protected */
+  /* Code segment */
+  if (fw_init->CodeSegmentLength != 0U)
+  {
+    assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress));
+    assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength));  
+  }
+  /* Non volatile data segment */
+  if (fw_init->NonVDataSegmentLength != 0U)
+  {
+    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress));
+    assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength));  
+  }
+  /* Volatile data segment */
+  if (fw_init->VDataSegmentLength != 0U)
+  {
+    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress));
+    assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength));  
+  }
+  
+  /* Check Firewall Configuration Register parameters */
+  assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution));
+  assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared));
+  
+  
+   /* Configuration */
+  
+  /* Protected code segment start address configuration */
+  WRITE_REG(FIREWALL->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress));
+	/* Protected code segment length configuration */
+  WRITE_REG(FIREWALL->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength));
+  
+  /* Protected non volatile data segment start address configuration */
+  WRITE_REG(FIREWALL->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress));
+	/* Protected non volatile data segment length configuration */
+  WRITE_REG(FIREWALL->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength));
+  
+  /* Protected volatile data segment start address configuration */
+  WRITE_REG(FIREWALL->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress));
+	/* Protected volatile data segment length configuration */
+  WRITE_REG(FIREWALL->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength));  
+  
+  /* Set Firewall Configuration Register VDE and VDS bits
+     (volatile data execution and shared configuration) */  
+  MODIFY_REG(FIREWALL->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Retrieve the Firewall configuration.
+  * @param fw_config: Firewall configuration, type is same as initialization structure
+  * @note This API can't be executed inside a code area protected by the Firewall
+  *       when the Firewall is enabled
+  * @note If NVDSL register is different from 0, that is, if the non volatile data segment 
+  *       is defined, this API can't be executed when the Firewall is enabled.      
+  * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status            
+  * @retval None
+  */
+void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config)
+{
+
+  /* Enable Firewall clock, in case no Firewall configuration has been carried 
+     out up to this point */
+  __HAL_RCC_FIREWALL_CLK_ENABLE();
+
+  /* Retrieve code segment protection setting */
+  fw_config->CodeSegmentStartAddress = (READ_REG(FIREWALL->CSSA) & FW_CSSA_ADD);
+  fw_config->CodeSegmentLength = (READ_REG(FIREWALL->CSL) & FW_CSL_LENG);
+  
+  /* Retrieve non volatile data segment protection setting */
+  fw_config->NonVDataSegmentStartAddress = (READ_REG(FIREWALL->NVDSSA) & FW_NVDSSA_ADD);
+  fw_config->NonVDataSegmentLength = (READ_REG(FIREWALL->NVDSL) & FW_NVDSL_LENG);
+  
+  /* Retrieve volatile data segment protection setting */
+  fw_config->VDataSegmentStartAddress = (READ_REG(FIREWALL->VDSSA) & FW_VDSSA_ADD);
+  fw_config->VDataSegmentLength = (READ_REG(FIREWALL->VDSL) & FW_VDSL_LENG);     
+  
+  /* Retrieve volatile data execution setting */
+  fw_config->VolatileDataExecution = (READ_REG(FIREWALL->CR) & FW_CR_VDE);
+  
+  /* Retrieve volatile data shared setting */
+  fw_config->VolatileDataShared = (READ_REG(FIREWALL->CR) & FW_CR_VDS);
+  
+  return;
+}
+
+
+
+/**
+  * @brief Enable FIREWALL. 
+  * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.
+  *       Once enabled, the Firewall cannot be disabled by software. Only a 
+  *       system reset can set again FWDIS bit.           
+  * @retval None
+  */
+void HAL_FIREWALL_EnableFirewall(void)
+{
+  /* Clears FWDIS bit of SYSCFG CFGR1 register */
+  CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);
+  
+}
+
+/**
+  * @brief Enable FIREWALL pre arm. 
+  * @note When FPA bit is set, any code executed outside the protected segment 
+  *       will close the Firewall. 
+  * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro
+  *       but can't be executed inside a code area protected by the Firewall. 
+  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
+  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
+  *          when the non volatile data segment is not defined),
+  *          **  this API can be executed when the Firewall is closed
+  *          **  when the Firewall is opened, user should resort to 
+  *              __HAL_FIREWALL_PREARM_ENABLE() macro instead
+  * @note When the Firewall is enabled and  NVDSL register is different from 0
+  *          (that is, when the non volatile data segment is defined)
+  *          **  FW_CR register can be accessed only when the Firewall is opened: 
+  *              user should resort to  __HAL_FIREWALL_PREARM_ENABLE() macro instead.               
+  * @retval None
+  */
+void HAL_FIREWALL_EnablePreArmFlag(void)
+{
+  /* Set FPA bit */
+  SET_BIT(FIREWALL->CR, FW_CR_FPA);
+}
+
+
+/**
+  * @brief Disable FIREWALL pre arm.
+  * @note When FPA bit is reset, any code executed outside the protected segment 
+  *       when the Firewall is opened will generate a system reset.
+  * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro
+  *       but can't be executed inside a code area protected by the Firewall.
+  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.   
+  * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is, 
+  *          when the non volatile data segment is not defined),
+  *          **  this API can be executed when the Firewall is closed
+  *          **  when the Firewall is opened, user should resort to 
+  *              __HAL_FIREWALL_PREARM_DISABLE() macro instead
+  * @note When the Firewall is enabled and  NVDSL register is different from 0
+  *          (that is, when the non volatile data segment is defined)
+  *          **  FW_CR register can be accessed only when the Firewall is opened: 
+  *              user should resort to  __HAL_FIREWALL_PREARM_DISABLE() macro instead.               
+          
+  * @retval None
+  */
+void HAL_FIREWALL_DisablePreArmFlag(void)
+{
+  /* Clear FPA bit */
+  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* #if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c
new file mode 100755
index 0000000..57a11c9
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c
@@ -0,0 +1,1436 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_i2s.c
+  * @author  MCD Application Team
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  @verbatim
+ ===============================================================================
+                  ##### How to use this driver #####
+ ===============================================================================
+ [..]
+    The I2S HAL driver can be used as follow:
+    
+    (#) Declare a I2S_HandleTypeDef handle structure.
+    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+        (##) Enable the SPIx interface clock.                      
+        (##) I2S pins configuration:
+            (+++) Enable the clock for the I2S GPIOs.
+            (+++) Configure these I2S pins as alternate function.
+        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+             and HAL_I2S_Receive_IT() APIs).
+            (+++) Configure the I2Sx interrupt priority.
+            (+++) Enable the NVIC I2S IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+             and HAL_I2S_Receive_DMA() APIs:
+            (+++) Declare a DMA handle structure for the Tx/Rx Channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
+            (+++) Configure the DMA Tx/Rx Channel.
+            (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
+                  DMA Tx/Rx Channel.
+
+   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+       using HAL_I2S_Init() function.
+
+   -@- The specific I2S interrupts (Transmission complete interrupt, 
+       RXNE interrupt and Error Interrupts) will be managed using the macros
+       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+   -@- Make sure that either:
+       (+@) External clock source is configured after setting correctly 
+            the define constant HSE_VALUE in the stm32l0xx_hal_conf.h file. 
+
+    (#) Three mode of operations are available within this driver :     
+
+   *** Polling mode IO operation ***
+   =================================
+   [..]
+     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 
+     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+   *** Interrupt mode IO operation ***
+   ===================================
+   [..]
+     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+   *** DMA mode IO operation ***
+   ==============================
+   [..]
+     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+   *** I2S HAL driver macros list ***
+   ===================================
+   [..]
+     Below the list of most used macros in USART HAL driver.
+       
+      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 
+      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+    [..]
+      (@) You can refer to the I2S HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/** @addtogroup I2S I2S
+  * @brief I2S HAL module driver
+  * @{
+  */
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup I2S_Private
+  * @{
+  */
+static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 
+static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+/**
+  * @}
+  */
+  
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+  * @{
+  */
+
+/** @addtogroup  I2S_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and 
+          de-initialiaze the I2Sx peripheral in simplex mode:
+
+      (+) User must Implement HAL_I2S_MspInit() function in which he configures 
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2S_Init() to configure the selected device with 
+          the selected configuration:
+        (++) Mode
+        (++) Standard 
+        (++) Data Format
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) Polarity
+
+     (+) Call the function HAL_I2S_DeInit() to restore the default configuration 
+         of the selected I2Sx periperal. 
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initializes the I2S according to the specified parameters 
+  *         in the I2S_InitTypeDef and create the associated handle.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+  uint32_t tmp = 0U, i2sclk = 0U, tmpreg = 0U;
+  
+  /* Check the I2S handle allocation */
+  if(hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
+  
+  if(hi2s->State == HAL_I2S_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2s->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2S_MspInit(hi2s);
+  }
+  
+  hi2s->State = HAL_I2S_STATE_BUSY;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+  {
+    i2sodd = (uint32_t)0U;
+    i2sdiv = (uint32_t)2U;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) *******************/
+    if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1U;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2U;
+    }
+
+    /* Get the source clock value: based on System Clock value */
+    i2sclk = HAL_RCC_GetSysClockFreq();    
+
+    /* Compute the Real divider depending on the MCLK output state, with a floating point */
+    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
+    }
+
+    /* Remove the flatting point */
+    tmp = tmp / 10U;  
+
+    /* Check the parity of the divider */
+    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint32_t) (i2sodd << 8U);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+  {
+    /* Set the default values */
+    i2sdiv = 2U;
+    i2sodd = 0U;
+  }
+
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
+  /* Write to SPIx I2SPR register the computed value */
+  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+  
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  /* And configure the I2S with the I2S_InitStruct values                      */
+  MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
+                                        SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
+                                        SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
+                                        SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD),\
+                                       (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
+                                        hi2s->Init.Standard | hi2s->Init.DataFormat |\
+                                        hi2s->Init.CPOL));
+										
+  /* Get the I2SCFGR register value */
+  tmpreg = hi2s->Instance->I2SCFGR;
+  
+#if defined(SPI_I2SCFGR_ASTRTEN)
+  if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) 
+  {
+  /* Write to SPIx I2SCFGR */  
+  hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+  }
+  else
+  {
+  /* Write to SPIx I2SCFGR */  
+  hi2s->Instance->I2SCFGR = tmpreg;    
+  }
+#else
+  /* Write to SPIx I2SCFGR */  
+  hi2s->Instance->I2SCFGR = tmpreg;
+#endif
+									
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State= HAL_I2S_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DeInitializes the I2S peripheral 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if(hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  hi2s->State = HAL_I2S_STATE_BUSY;
+  
+  /* Disable the I2S Peripheral Clock */
+  __HAL_I2S_DISABLE(hi2s);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_I2S_MspDeInit(hi2s);
+
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State = HAL_I2S_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2s);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief I2S MSP Init
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief I2S MSP DeInit
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+  *  @brief Data transfers functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2S data 
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode. 
+            The status of all data processing is returned by the same function 
+            after finishing transfer.  
+       (++) No-Blocking mode : The communication is performed using Interrupts 
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the 
+            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2S_Transmit()
+        (++) HAL_I2S_Receive()
+        
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2S_Transmit_IT()
+        (++) HAL_I2S_Receive_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2S_Transmit_DMA()
+        (++) HAL_I2S_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2S_TxCpltCallback()
+        (++) HAL_I2S_RxCpltCallback()
+        (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Transmit an amount of data in blocking mode
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @param  Timeout: Timeout duration
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if((pData == NULL ) || (Size == 0U)) 
+  {
+    return  HAL_ERROR;                                    
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  { 
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = (Size << 1U);
+      hi2s->TxXferCount = (Size << 1U);
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+     
+    /* Set state and reset error code */
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+    hi2s->pTxBuffPtr = pData;
+      
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+    
+    while(hi2s->TxXferCount > 0U)
+    {
+      /* Wait until TXE flag is set */
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+      hi2s->TxXferCount--;   
+    } 
+
+    /* Wait until TXE flag is set, to confirm the end of the transaction */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    } 
+
+    /* Check if Slave mode is selected */
+    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+    {	
+      /* Wait until Busy flag is reset */
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    hi2s->State = HAL_I2S_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @param Timeout: Timeout duration
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+  *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+  * @note This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  if((pData == NULL ) || (Size == 0U)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  { 
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = (Size << 1U);
+      hi2s->RxXferCount = (Size << 1U);
+    }
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+        
+    /* Set state and reset error code */
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+    hi2s->pRxBuffPtr = pData;
+    
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Check if Master Receiver mode is selected */
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+    {
+      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+      access to the SPI_SR register. */ 
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+    }
+
+    /* Receive data */
+    while(hi2s->RxXferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      
+      (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+      hi2s->RxXferCount--;
+    }
+    
+    hi2s->State = HAL_I2S_STATE_READY; 
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  if((pData == NULL) || (Size == 0U)) 
+  {
+    return  HAL_ERROR;
+  }
+  
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+    
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    hi2s->pTxBuffPtr = pData;
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = (Size << 1U);
+      hi2s->TxXferCount = (Size << 1U);
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+
+    /* Enable TXE and ERR interrupt */
+    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 
+  * between Master and Slave otherwise the I2S interrupt should be optimized. 
+  * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+    if((pData == NULL) || (Size == 0U)) 
+    {
+      return  HAL_ERROR;
+    }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    hi2s->pRxBuffPtr = pData;
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = (Size << 1U);
+      hi2s->RxXferCount = (Size << 1U);
+    }  
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    
+    /* Enable RXNE and ERR interrupt */
+    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+    
+    /* Check if the I2S is already enabled */ 
+    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY; 
+  } 
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with DMA
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Transmit data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  if((pData == NULL) || (Size == 0U)) 
+  {
+    return  HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {  
+    hi2s->pTxBuffPtr = pData;
+    hi2s->State = HAL_I2S_STATE_BUSY_TX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->TxXferSize = (Size << 1U);
+      hi2s->TxXferCount = (Size << 1U);
+    }
+    else
+    {
+      hi2s->TxXferSize = Size;
+      hi2s->TxXferCount = Size;
+    }
+
+    /* Set the I2S Tx DMA Half transfert complete callback */
+    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+    /* Set the I2S Tx DMA transfert complete callback */
+    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+    /* Set the DMA error callback */
+    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+    /* Enable the Tx DMA Channel */
+    HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+    /* Check if the I2S is already enabled */ 
+    if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+    /* Check if the I2S Tx request is already enabled */ 
+    if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+    {
+      /* Enable Tx DMA Request */  
+      SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with DMA 
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param Size: number of data sample to be sent:
+  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *       configuration phase, the Size parameter means the number of 16-bit data length 
+  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
+  *       the Size parameter means the number of 16-bit data length. 
+  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
+  *       between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  if((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if(hi2s->State == HAL_I2S_STATE_READY)
+  {
+    hi2s->pRxBuffPtr = pData;
+    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+    {
+      hi2s->RxXferSize = (Size << 1U);
+      hi2s->RxXferCount = (Size << 1U);
+    }
+    else
+    {
+      hi2s->RxXferSize = Size;
+      hi2s->RxXferCount = Size;
+    }
+    
+    
+    /* Set the I2S Rx DMA Half transfert complete callback */
+    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+    
+    /* Set the I2S Rx DMA transfert complete callback */
+    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+    
+    /* Set the DMA error callback */
+    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+    
+    /* Check if Master Receiver mode is selected */
+    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+    {
+      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+      access to the SPI_SR register. */ 
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+    }
+    
+    /* Enable the Rx DMA Channel */
+    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
+    
+    /* Check if the I2S is already enabled */ 
+    if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+    {
+      /* Enable I2S peripheral */
+      __HAL_I2S_ENABLE(hi2s);
+    }
+
+     /* Check if the I2S Rx request is already enabled */ 
+    if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+    {
+      /* Enable Rx DMA Request */  
+      SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pauses the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+  {
+    /* Disable the I2S DMA Tx request */
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  {
+    /* Disable the I2S DMA Rx request */
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief Resumes the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+  {
+    /* Enable the I2S DMA Tx request */
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+  }
+  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  {
+    /* Enable the I2S DMA Rx request */
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+  }
+  
+  /* If the I2S peripheral is still not enabled, enable it */
+  if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+  {
+    /* Enable I2S peripheral */    
+    __HAL_I2S_ENABLE(hi2s);
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the audio stream playing from the Media.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+  
+  /* Disable the I2S Tx/Rx DMA requests */
+  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+  
+  /* Abort the I2S DMA Channel tx */
+  if(hi2s->hdmatx != NULL)
+  {
+    /* Disable the I2S DMA channel */
+    __HAL_DMA_DISABLE(hi2s->hdmatx);
+    HAL_DMA_Abort(hi2s->hdmatx);
+  }
+  /* Abort the I2S DMA Channel rx */
+  if(hi2s->hdmarx != NULL)
+  {
+    /* Disable the I2S DMA channel */
+    __HAL_DMA_DISABLE(hi2s->hdmarx);
+    HAL_DMA_Abort(hi2s->hdmarx);
+  }
+
+  /* Disable I2S peripheral */
+  __HAL_I2S_DISABLE(hi2s);
+  
+  hi2s->State = HAL_I2S_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2S interrupt request.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{  
+  uint32_t i2ssr = hi2s->Instance->SR;
+  
+  /* I2S in mode Receiver ------------------------------------------------*/
+  if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
+     ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+  {
+    I2S_Receive_IT(hi2s);
+    return;
+  }
+
+  /* I2S in mode Tramitter -----------------------------------------------*/
+  if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+  {     
+    I2S_Transmit_IT(hi2s);
+    return;
+  } 
+
+  /* I2S interrupt error -------------------------------------------------*/
+  if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
+  {
+    /* I2S Overrun error interrupt occured ---------------------------------*/
+    if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
+    {
+      /* Disable RXNE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+      
+      /* Set the error code and execute error callback*/
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+    } 
+    
+    /* I2S Underrun error interrupt occured --------------------------------*/
+    if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
+    {
+      /* Disable TXE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+      
+      /* Set the error code and execute error callback*/
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+    }
+    
+    /* Set the I2S State ready */
+    hi2s->State = HAL_I2S_STATE_READY; 
+    /* Call the Error Callback */
+    HAL_I2S_ErrorCallback(hi2s);
+  }
+}
+
+/**
+  * @brief Tx Transfer Half completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxCpltCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Rx Transfer half completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief I2S error callbacks
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_ErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+  *  @brief   Peripheral State functions 
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral 
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2S state
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL state
+  */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->State;
+}
+
+/**
+  * @brief  Return the I2S error code
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval I2S Error Code
+  */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup I2S_Private
+  * @{
+  */
+/**
+  * @brief DMA I2S transmit process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  
+  if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+    hi2s->TxXferCount = 0U;
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+  HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+  * @brief DMA I2S transmit process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+  * @brief DMA I2S receive process complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    /* Disable Rx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+    hi2s->RxXferCount = 0U;
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+  HAL_I2S_RxCpltCallback(hi2s); 
+}
+
+/**
+  * @brief DMA I2S receive process half complete callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  HAL_I2S_RxHalfCpltCallback(hi2s); 
+}
+
+/**
+  * @brief DMA I2S communication error callback 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Disable Rx and Tx DMA Request */
+  CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+  hi2s->TxXferCount = 0U;
+  hi2s->RxXferCount = 0U;
+
+  hi2s->State= HAL_I2S_STATE_READY;
+
+  /* Set the error code and execute error callback*/
+  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+  HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+  * @brief Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Transmit data */
+  hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+  hi2s->TxXferCount--;
+    
+  if(hi2s->TxXferCount == 0U)
+  {
+    /* Disable TXE and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+    hi2s->State = HAL_I2S_STATE_READY;
+    HAL_I2S_TxCpltCallback(hi2s);
+  }
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode with Interrupt
+  * @param hi2s: I2S handle
+  * @retval None
+  */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Receive data */    
+  (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+  hi2s->RxXferCount--;
+  
+  if(hi2s->RxXferCount == 0U)
+  {
+    /* Disable RXNE and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+    hi2s->State = HAL_I2S_STATE_READY;     
+    HAL_I2S_RxCpltCallback(hi2s); 
+  }
+}
+
+
+/**
+  * @brief This function handles I2S Communication Timeout.
+  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param Flag: Flag checked
+  * @param Status: Value of the flag expected
+  * @param Timeout: Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
+          /* Set the I2S State ready */
+          hi2s->State= HAL_I2S_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2s);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+    {
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+        {
+          /* Set the I2S State ready */
+          hi2s->State= HAL_I2S_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2s);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c
new file mode 100755
index 0000000..ecf973c
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c
@@ -0,0 +1,2357 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_irda.c
+  * @author  MCD Application Team
+  * @brief   IRDA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the IrDA (Infrared Data Association) Peripheral
+  *          (IRDA)
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The IRDA HAL driver can be used as follows:
+
+    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+        in setting the associated USART or UART in IRDA mode:
+        (++) Enable the USARTx/UARTx interface clock.
+        (++) USARTx/UARTx pins configuration:
+            (+++) Enable the clock for the USARTx/UARTx GPIOs.
+            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+             and HAL_IRDA_Receive_IT() APIs): 
+            (+++) Configure the USARTx/UARTx interrupt priority.
+            (+++) Enable the NVIC USARTx/UARTx IRQ handle.            
+            (+++) The specific IRDA interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+                
+        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+             and HAL_IRDA_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+        the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_IRDA_MspInit() API.
+        
+         -@@- The specific IRDA interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+     
+    (#) Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** IRDA HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IRDA HAL driver.
+
+       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+     [..]
+       (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IRDA IRDA
+  * @brief HAL IRDA module driver
+  * @{
+  */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+  * @{
+  */
+#define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
+#define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  in asynchronous IRDA mode.
+  (+) For the asynchronous mode only these parameters can be configured:
+      (++) Baud Rate
+      (++) Word Length
+      (++) Parity: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+      (++) Power mode
+      (++) Prescaler setting
+      (++) Receiver/transmitter modes
+
+  [..]
+  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible IRDA frame formats are listed in the 
+  following table.
+  
+    Table 1. IRDA frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the IRDA mode according to the specified
+  *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
+  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  if(hirda->gState == HAL_IRDA_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hirda->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_IRDA_MspInit(hirda);
+  }
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* Disable the Peripheral to update the configuration registers */
+  __HAL_IRDA_DISABLE(hirda);
+
+  /* Set the IRDA Communication parameters */
+  if (IRDA_SetConfig(hirda) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+  /* set the UART/USART in IRDA mode */
+  hirda->Instance->CR3 |= USART_CR3_IREN;
+
+  /* Enable the Peripheral */
+  __HAL_IRDA_ENABLE(hirda);
+
+  /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+  return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+  * @brief DeInitialize the IRDA peripheral.
+  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if(hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+  HAL_IRDA_MspDeInit(hirda);
+  /* Disable the Peripheral */
+  __HAL_IRDA_DISABLE(hirda);
+
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+  hirda->gState    = HAL_IRDA_STATE_RESET;
+  hirda->RxState   = HAL_IRDA_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the IRDA MSP.
+  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the IRDA MSP.
+  * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+  *  @brief   IRDA Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+  [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+
+    (#) There are two mode of transfer:
+        (++) Blocking mode: the communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: the communication is performed using Interrupts
+             or DMA, these API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_IRDA_Transmit()
+        (++) HAL_IRDA_Receive()
+
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_IRDA_Transmit_IT()
+        (++) HAL_IRDA_Receive_IT()
+        (++) HAL_IRDA_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_IRDA_Transmit_DMA()
+        (++) HAL_IRDA_Receive_DMA()
+        (++) HAL_IRDA_DMAPause()
+        (++) HAL_IRDA_DMAResume()
+        (++) HAL_IRDA_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+        (++) HAL_IRDA_TxHalfCpltCallback()
+        (++) HAL_IRDA_TxCpltCallback()
+        (++) HAL_IRDA_RxHalfCpltCallback()
+        (++) HAL_IRDA_RxCpltCallback()
+        (++) HAL_IRDA_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_IRDA_Abort()
+        (+) HAL_IRDA_AbortTransmit()
+        (+) HAL_IRDA_AbortReceive()
+        (+) HAL_IRDA_Abort_IT()
+        (+) HAL_IRDA_AbortTransmit_IT()
+        (+) HAL_IRDA_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_IRDA_AbortCpltCallback()
+        (+) HAL_IRDA_AbortTransmitCpltCallback()
+        (+) HAL_IRDA_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @param  Timeout Specify timeout value.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tickstart = 0;
+
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+    while(hirda->TxXferCount > 0U)
+    {
+      hirda->TxXferCount--;
+
+      if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData;
+        hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+        pData += 2;
+      }
+      else
+      {
+        hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+      }
+    }
+
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @param  Timeout Specify timeout value.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be received from RDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+    uhMask = hirda->Mask;
+
+    /* Check data remaining to be received */
+    while(hirda->RxXferCount > 0U)
+    {
+      hirda->RxXferCount--;
+
+      if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pData ;
+        *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+        pData +=2U;
+      }
+      else
+      {
+        *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the IRDA Transmit Data Register Empty Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to the RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the IRDA transmit DMA channel */
+    HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  pData Pointer to data buffer.
+  * @param  Size Amount of data to be received.
+  * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+    {
+      if((((uint32_t)pData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Pause the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+  {
+    /* Disable the IRDA DMA Tx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the IRDA DMA Rx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    /* Enable the IRDA DMA Tx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+  }
+  if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the IRDA DMA Rx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+     HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: 
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
+     the stream and the corresponding call back is executed. */
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel */
+    if(hirda->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+      (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel */
+    if(hirda->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+
+    IRDA_EndRxTransfer(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  hirda->TxXferCount = 0; 
+  hirda->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hirda->TxXferCount = 0; 
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hirda->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hirda->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hirda->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the IRDA DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* IRDA Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        hirda->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* IRDA Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        hirda->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hirda->TxXferCount = 0; 
+    hirda->RxXferCount = 0;
+
+    /* Reset errorCode */
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->gState and hirda->RxState to Ready */
+    hirda->gState  = HAL_IRDA_STATE_READY;
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hirda->TxXferCount = 0; 
+
+      /* Restore hirda->gState to Ready */
+      hirda->gState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_IRDA_AbortTransmitCpltCallback(hirda);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hirda->TxXferCount = 0; 
+
+    /* Restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortTransmitCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback : 
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hirda->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+      /* Restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_IRDA_AbortReceiveCpltCallback(hirda);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hirda->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_IRDA_AbortReceiveCpltCallback(hirda);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle IRDA interrupt request.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == RESET)
+  {
+    /* IRDA in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      IRDA_Receive_IT(hirda);
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(hirda->Instance->CR3);
+  if(   (errorflags != RESET) 
+     && (    ((cr3its & USART_CR3_EIE) != RESET)
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+  {
+    /* IRDA parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+    }
+
+    /* IRDA frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+    }
+
+    /* IRDA noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+    }
+
+    /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+    }
+
+    /* Call IRDA Error Call back function if need be --------------------------*/
+    if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+    {
+      /* IRDA in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        IRDA_Receive_IT(hirda);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
+          (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the IRDA state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        IRDA_EndRxTransfer(hirda);
+
+        /* Disable the IRDA DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the IRDA DMA Rx channel */
+          if(hirda->hdmarx != NULL)
+          {
+            /* Set the IRDA DMA Abort callback : 
+               will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_IRDA_ErrorCallback(hirda);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_IRDA_ErrorCallback(hirda);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_IRDA_ErrorCallback(hirda);
+        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* IRDA in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    IRDA_Transmit_IT(hirda);
+    return;
+  }
+
+  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    IRDA_EndTransmit_IT(hirda);
+    return;
+  }
+
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer complete callback.
+  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA error callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Receive Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   IRDA State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of IrDA
+    communication process and also return Peripheral Errors occurred during communication process
+     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+         of the IRDA peripheral handle.
+     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the IRDA handle state.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL state
+  */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+  /* Return IRDA handle state */
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = hirda->gState;
+  temp2 = hirda->RxState;
+
+  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the IRDA handle error code.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval IRDA Error Code
+  */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+  return hirda->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure the IRDA peripheral.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tmpreg                     = 0x00000000U;
+  IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret               = HAL_OK;
+
+  /* Check the communication parameters */
+  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+  assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+  assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Configure the IRDA Word Length, Parity and transfer Mode:
+     Set the M bits according to hirda->Init.WordLength value
+     Set PCE and PS bits according to hirda->Init.Parity value
+     Set TE and RE bits according to hirda->Init.Mode value */
+  tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+  MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  IRDA_GETCLOCKSOURCE(hirda, clocksource);
+  switch (clocksource)
+  {
+    case IRDA_CLOCKSOURCE_PCLK1:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_PCLK2:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_HSI:
+      hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_SYSCLK:
+      hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_LSE:
+      hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
+      break;
+    case IRDA_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Check the IRDA Idle State.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the IRDA ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the IRDA state*/
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle IRDA Communication Timeout.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  Flag Specifies the IRDA flag to check.
+  * @param  Status Flag status (SET or RESET)
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+        hirda->gState  = HAL_IRDA_STATE_READY;
+        hirda->RxState = HAL_IRDA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hirda);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+  * @brief  DMA IRDA transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    hirda->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the IRDA Transmit Complete Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+    HAL_IRDA_TxCpltCallback(hirda);
+  }
+
+}
+
+/**
+  * @brief  DMA IRDA transmit process half complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA receive process complete callback.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    hirda->RxXferCount = 0;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+  }
+
+  HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+  * @brief DMA IRDA receive process half complete callback.
+  * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if (  (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    hirda->TxXferCount = 0;
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if (  (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    hirda->RxXferCount = 0;
+    IRDA_EndRxTransfer(hirda);
+  }
+
+  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+  HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+  hirda->RxXferCount = 0;
+  hirda->TxXferCount = 0;
+
+  HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+  
+  hirda->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hirda->hdmarx != NULL)
+  {
+    if(hirda->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0;
+  hirda->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+  
+  hirda->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hirda->hdmatx != NULL)
+  {
+    if(hirda->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0;
+  hirda->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+  hirda->TxXferCount = 0;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hirda->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+
+  /* Check that a Tx process is ongoing */
+  if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if(hirda->TxXferCount == 0U)
+    {
+      /* Disable the IRDA Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the IRDA Transmit Complete Interrupt */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (uint16_t*) hirda->pTxBuffPtr;
+        hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+        hirda->pTxBuffPtr += 2U;
+      }
+      else
+      {
+        hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
+      }
+      hirda->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable the IRDA Transmit Complete Interrupt */
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  HAL_IRDA_TxCpltCallback(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Receive_IT()
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t* tmp;
+  uint16_t  uhMask = hirda->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      tmp = (uint16_t*) hirda->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      hirda->pRxBuffPtr +=2U;
+    }
+    else
+    {
+      *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+    }
+
+    if(--hirda->RxXferCount == 0U)
+    {
+      /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      HAL_IRDA_RxCpltCallback(hirda);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c
new file mode 100755
index 0000000..6310686
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_iwdg.c
@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+        if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both can not be 
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is 
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, 
+        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+        prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending 
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+    [..] Min-max timeout value @32KHz (LSI): ~0.512ms / ~32.0s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32L0xx
+         devices provide the capability to measure the LSI frequency (LSI clock
+         connected internally to TIM5 CH4 input capture). The measured value
+         can be used to have an IWDG timeout with an acceptable accuracy.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI 
+           clock is forced ON and IWDG counter starts downcounting.
+      (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & 
+           IWDG_WINR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload 
+           value will be loaded in the IWDG counter each time the watchdog is 
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Wait for status flags to be reset
+      (++) Depending on window parameter:
+        (+++) If Window Init parameter is same as Window register value, 
+             nothing more is done but reload counter value in order to exit 
+             function withy exact time base.
+        (+++) Else modify Window register. This will automatically reload
+             watchdog counter.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+  * @{
+  */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
+   higher prescaler (256), and according to LSI variation, we need to wait at 
+   least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT            48U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ *  @brief    Initialization and Start functions.
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the 
+          IWDG_InitTypeDef of associated handle.
+      (+) Manage Window option.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog 
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IWDG according to the specified parameters in the 
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function, 
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if(hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+  /* Enable IWDG. LSI is turned on automaticaly */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+   /* Wait for register to be updated */
+  while(hiwdg->Instance->SR != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* If window parameter is different than current value, modify window 
+  register */
+  if(hiwdg->Instance->WINR != hiwdg->Init.Window)
+  {
+    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+    even if window feature is disabled, Watchdog will be reloaded by writing 
+    windows register */
+    hiwdg->Instance->WINR = hiwdg->Init.Window;
+  }
+  else
+  {
+    /* Reload IWDG counter with value defined in the reload register */
+    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ *  @brief   IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c
new file mode 100755
index 0000000..dac4d8c
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lcd.c
@@ -0,0 +1,625 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_lcd.c
+  * @author  MCD Application Team
+  * @brief   LCD Controller HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the LCD Controller (LCD) peripheral:
+  *           + Initialization/de-initialization methods
+  *           + I/O operation methods
+  *           + Peripheral State methods
+  *           
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================   
+      [..] The LCD HAL driver can be used as follow:
+    
+      (#) Declare a LCD_HandleTypeDef handle structure.
+
+      (#) Prepare the initialization of the LCD low level resources by implementing your HAL_LCD_MspInit() API:
+          (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, use the RCC function 
+               HAL_RCCEx_PeriphCLKConfig, indicating here RCC_PERIPHCLK_LCD and the selected clock 
+               source (HSE, LSI or LSE)
+          (##) The frequency generator allows you to achieve various LCD frame rates starting from an 
+               LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.
+          (##) LCD pins configuration:
+              - Enable the clock for the LCD GPIOs
+              - Configure these LCD pins as alternate function no-pull.
+          (##) Enable the LCD interface clock.
+
+      (#) Set the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias, Voltage Source, 
+          Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
+
+      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
+          (##) The HAL_LCD_Init() API configures the low level Hardware (GPIO, CLOCK, ...etc)
+               by calling the user customized HAL_LCD_MspInit() API.
+      (#) After calling the HAL_LCD_Init() the LCD RAM memory is cleared
+
+      (#) Optionally you can update the LCD configuration using these macros:
+           (##) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
+           (##) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
+           (##) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro  
+           (##) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
+           (##) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro  
+
+      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
+          several times to update the different LCD RAM registers before calling 
+          HAL_LCD_UpdateDisplayRequest() API.
+
+      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
+
+      (#) When the LCD RAM memory is updated, enable the update display request calling
+          the HAL_LCD_UpdateDisplayRequest() API.
+
+      [..] LCD and low power modes: The LCD remain active during STOP mode.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+
+/** @addtogroup LCD
+  * @brief LCD HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup LCD_Private
+  * @{
+  */
+#define LCD_TIMEOUT_VALUE             1000U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup LCD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LCD_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions 
+  *
+@verbatim    
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]
+
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  DeInitializes the LCD peripheral. 
+  * @param  hlcd: LCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Check the LCD handle allocation */
+  if(hlcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
+
+  /* Check the LCD peripheral state */
+  if(hlcd->State == HAL_LCD_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  hlcd->State = HAL_LCD_STATE_BUSY;
+  
+  /* Disable the peripheral */
+  __HAL_LCD_DISABLE(hlcd);
+
+  /*Disable Highdrive by default*/
+  __HAL_LCD_HIGHDRIVER_DISABLE(hlcd);
+
+  /* DeInit the low level hardware */
+  HAL_LCD_MspDeInit(hlcd);
+  
+  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
+  hlcd->State = HAL_LCD_STATE_RESET;
+    
+  /* Release Lock */
+  __HAL_UNLOCK(hlcd);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Initializes the LCD peripheral according to the specified parameters 
+  *         in the LCD_InitStruct.
+  * @note   This function can be used only when the LCD is disabled.
+  *         The LCD HighDrive can be enabled/disabled using related macros up to user.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00U;
+  uint8_t counter = 0U;
+    
+  /* Check the LCD handle allocation */
+  if(hlcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check function parameters */
+  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
+  assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
+  assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
+  assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
+  assert_param(IS_LCD_BIAS(hlcd->Init.Bias));  
+  assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
+  assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
+  assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive));
+  assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
+  assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); 
+  assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); 
+  assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); 
+  assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment));
+  
+  if(hlcd->State == HAL_LCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    __HAL_UNLOCK(hlcd);
+
+    /* Initialize the low level hardware (MSP) */
+    HAL_LCD_MspInit(hlcd);
+  }
+  
+  hlcd->State = HAL_LCD_STATE_BUSY;
+  
+  /* Disable the peripheral */
+  __HAL_LCD_DISABLE(hlcd);
+  
+  /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
+     in the LCD_SR register */
+  for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
+  {
+    hlcd->Instance->RAM[counter] = 0U;
+  }
+  /* Enable the display request */
+  SET_BIT(hlcd->Instance->SR, LCD_SR_UDR);
+  
+  /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: 
+  Set PS[3:0] bits according to hlcd->Init.Prescaler value 
+     Set DIV[3:0] bits according to hlcd->Init.Divider value
+     Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
+     Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
+     Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
+     Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value 
+     Set CC[2:0] bits according to hlcd->Init.Contrast value
+     Set HD[0] bit according to hlcd->Init.HighDrive value*/
+
+  MODIFY_REG(hlcd->Instance->FCR, \
+             (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
+             LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \
+             (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
+             hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
+
+  /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register 
+     This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
+     domain. It is cleared by hardware when writing to the LCD_FCR register.*/
+  LCD_WaitForSynchro(hlcd);
+  
+  /* Configure the LCD Duty, Bias, Voltage Source, Dead Time:
+     Set DUTY[2:0] bits according to hlcd->Init.Duty value 
+     Set BIAS[1:0] bits according to hlcd->Init.Bias value
+     Set VSEL bit according to hlcd->Init.VoltageSource value
+     Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
+  MODIFY_REG(hlcd->Instance->CR, \
+             (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
+             (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
+  
+  /* Enable the peripheral */
+  __HAL_LCD_ENABLE(hlcd);
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+      
+  /* Wait Until the LCD is enabled */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    { 
+      hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
+      return HAL_TIMEOUT;
+    } 
+  }
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  /*!< Wait Until the LCD Booster is ready */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    {   
+      hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
+      return HAL_TIMEOUT;
+    } 
+  }
+ 
+  /* Initialize the LCD state */
+  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
+  hlcd->State= HAL_LCD_STATE_READY;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  LCD MSP DeInit.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+ __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlcd);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_LCD_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  LCD MSP Init.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+ __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlcd);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_LCD_MspInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup LCD_Exported_Functions_Group2
+  *  @brief LCD RAM functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+ [..] Using its double buffer memory the LCD controller ensures the coherency of the 
+ displayed information without having to use interrupts to control LCD_RAM 
+ modification.
+ The application software can access the first buffer level (LCD_RAM) through 
+ the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
+ it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
+ This UDR flag (update display request) requests the updated information to be 
+ moved into the second buffer level (LCD_DISPLAY).
+ This operation is done synchronously with the frame (at the beginning of the 
+ next frame), until the update is completed, the LCD_RAM is write protected and 
+ the UDR flag stays high.
+ Once the update is completed another flag (UDD - Update Display Done) is set and
+ generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
+ The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one 
+ even frame.
+ The update will not occur (UDR = 1 and UDD = 0) until the display is 
+ enabled (LCDEN = 1).
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a word in the specific LCD RAM.
+  * @param  hlcd: LCD handle
+  * @param  RAMRegisterIndex: specifies the LCD RAM Register.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
+  *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
+  *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
+  *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
+  *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
+  *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
+  *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6 
+  *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7  
+  *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
+  *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
+  *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
+  *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
+  *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12 
+  *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13 
+  *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14 
+  *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
+  * @param  RAMRegisterMask: specifies the LCD RAM Register Data Mask.
+  * @param  Data: specifies LCD Data Value to be written.
+  * @note   For LCD glass COM*SEG as 8*40 for example, the LCD common terminals COM[0,7]
+  *         are mapped on 32bits LCD_RAM_REGISTER[0,14] according to rules: COM(n) spread
+  *  	    on LCD_RAM_REGISTER(2*n) and  LCD_RAM_REGISTER(2*n+1).The segment terminals 
+  *		    SEG[0,39] of COM(n) correspond to LSB bits of related LCD_RAM_REGISTER(2*n)[0,31]
+  *		    and LCD_RAM_REGISTER(2*n+1)[0,7] 
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
+{
+  uint32_t tickstart = 0x00U; 
+  
+  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
+  {
+    /* Check the parameters */
+    assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
+    
+    if(hlcd->State == HAL_LCD_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(hlcd);
+      hlcd->State = HAL_LCD_STATE_BUSY;
+      
+      /* Get timeout */
+      tickstart = HAL_GetTick();
+      
+      /*!< Wait Until the LCD is ready */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
+      {
+        if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
+        { 
+          hlcd->ErrorCode = HAL_LCD_ERROR_UDR;      
+          /* Process Unlocked */
+          __HAL_UNLOCK(hlcd);
+          return HAL_TIMEOUT;
+        } 
+      }
+    }
+/* Copy the new Data bytes to LCD RAM register */
+    MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief Clears the LCD RAM registers.
+  * @param hlcd: LCD handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00U; 
+  uint32_t counter = 0U;
+
+  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hlcd);
+    
+    hlcd->State = HAL_LCD_STATE_BUSY;
+    
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+    
+    /*!< Wait Until the LCD is ready */
+    while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
+    {
+      if( (HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
+      { 
+        hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hlcd);
+
+        return HAL_TIMEOUT;
+      } 
+    }
+    /* Clear the LCD_RAM registers */
+    for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
+    {
+      hlcd->Instance->RAM[counter] = 0U;
+    }
+    
+    /* Update the LCD display */
+    HAL_LCD_UpdateDisplayRequest(hlcd);     
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enables the Update Display Request.
+  * @param  hlcd: LCD handle
+  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to 
+  *         transfer the updated data to the second level buffer. 
+  *         The UDR bit stays set until the end of the update and during this 
+  *         time the LCD_RAM is write protected. 
+  * @note   When the display is disabled, the update is performed for all 
+  *         LCD_DISPLAY locations.
+  *         When the display is enabled, the update is performed only for locations 
+  *         for which commons are active (depending on DUTY). For example if 
+  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.    
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00U;
+  
+  /* Clear the Update Display Done flag before starting the update display request */
+  __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
+  
+  /* Enable the display request */
+  hlcd->Instance->SR |= LCD_SR_UDR;
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+  
+  /*!< Wait Until the LCD display is done */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
+    { 
+      hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hlcd);
+  
+      return HAL_TIMEOUT;
+    }
+  }
+
+  hlcd->State = HAL_LCD_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hlcd);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup LCD_Exported_Functions_Group3
+  *  @brief   LCD State functions 
+  *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+     This subsection provides a set of functions allowing to control the LCD:
+      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. 
+      (+) HAL_LCD_GetError() API to return the LCD error code. 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Returns the LCD state.
+  * @param hlcd: LCD handle
+  * @retval HAL state
+  */
+HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
+{
+  return hlcd->State;
+}
+
+/**
+  * @brief Return the LCD error code
+  * @param hlcd: LCD handle
+  * @retval LCD Error Code
+  */
+uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
+{
+  return hlcd->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup LCD_Private
+  * @{
+  */
+
+/**
+  * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
+  *   This function must be called after any write operation to LCD_FCR register.
+  * @param  hlcd: LCD handle
+  * @retval None
+  */
+HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
+{
+  uint32_t tickstart = 0x00U; 
+  
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Loop until FCRSF flag is set */
+  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
+    {       
+      hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
+      return HAL_TIMEOUT;
+    } 
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_LCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+#endif /* #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c
new file mode 100755
index 0000000..43c712e
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_lptim.c
@@ -0,0 +1,1654 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_lptim.c
+  * @author  MCD Application Team
+  * @brief   LPTIM HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Low Power Timer (LPTIM) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Start/Stop operation functions in polling mode.
+  *           + Start/Stop operation functions in interrupt mode.
+  *           + Reading operation functions.
+  *           + Peripheral State functions.
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The LPTIM HAL driver can be used as follows:
+
+      (#)Initialize the LPTIM low level resources by implementing the
+        HAL_LPTIM_MspInit():
+         (##) Enable the LPTIM interface clock using __HAL_RCC_LPTIM1_CLK_ENABLE().
+         (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+             (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+             (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+             (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+    
+      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+         configures mainly:
+         (##) The instance: Only LPTIM1 is present in STM32L053xx.
+         (##) Clock: the counter clock.
+                 - Source   : it can be either the ULPTIM input (IN1) or one of
+                              the internal clock; (APB, LSE, LSI or MSI).
+                 - Prescaler: select the clock divider.
+         (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected
+               as counter clock source.
+                 - Polarity:   polarity of the active edge for the counter unit
+                               if the ULPTIM input is selected.
+                 - SampleTime: clock sampling time to configure the clock glitch
+                               filter.              
+         (##) Trigger: How the counter start.
+                 - Source: trigger can be software or one of the hardware triggers.
+                 - ActiveEdge : only for hardware trigger.
+                 - SampleTime : trigger sampling time to configure the trigger
+                                glitch filter.
+         (##) OutputPolarity : 2 opposite polarities are possibles.
+         (##) UpdateMode: specifies whether the update of the autoreload and
+              the compare values is done immediately or after the end of current
+              period.   
+    
+      (#)Six modes are available:
+      
+         (##) PWM Mode: To generate a PWM signal with specified period and pulse,
+         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+         mode.
+         
+         (##) One Pulse Mode: To generate pulse with specified width in response
+         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+         
+         (##) Set once Mode: In this mode, the output changes the level (from
+         low level to high level if the output polarity is configured high, else
+         the opposite) when a compare match occurs. To start this mode, call 
+         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+         interruption mode.
+         
+         (##) Encoder Mode: To use the encoder interface call
+         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for 
+         interruption mode.
+         
+         (##) Time out Mode: an active edge on one selected trigger input rests
+         the counter. The first trigger event will start the timer, any
+         successive trigger event will reset the counter and the timer will
+         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or 
+         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+         
+         (##) Counter Mode: counter can be used to count external events on
+         the LPTIM Input1 or it can be used to count internal clock cycles.
+         To start this mode, call HAL_LPTIM_Counter_Start() or 
+         HAL_LPTIM_Counter_Start_IT() for interruption mode.             
+
+    
+      (#) User can stop any process by calling the corresponding API:
+          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+          already started in interruption mode.
+         
+       (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+
+/** @addtogroup LPTIM
+  * @brief LPTIM HAL module driver.
+  * @{
+  */
+
+/** @addtogroup LPTIM_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions. 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the LPTIM according to the specified parameters in the
+          LPTIM_InitTypeDef and creates the associated handle.
+      (+) DeInitialize the LPTIM peripheral.
+      (+) Initialize the LPTIM MSP.
+      (+) DeInitialize LPTIM MSP. 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the LPTIM according to the specified parameters in the
+  *         LPTIM_InitTypeDef and creates the associated handle.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+  uint32_t tmpcfgr = 0U;
+  
+  /* Check the LPTIM handle allocation */
+  if(hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));  
+  if((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+  }  
+  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+  }  
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));  
+  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+  
+  if(hlptim->State == HAL_LPTIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hlptim->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_LPTIM_MspInit(hlptim);
+  }
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+  
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+  
+  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+  }
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+  }
+    
+  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
+  
+  /* Set initialization parameters */
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+              hlptim->Init.Clock.Prescaler |
+              hlptim->Init.OutputPolarity  |
+              hlptim->Init.UpdateMode      |
+              hlptim->Init.CounterSource);
+  
+  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)
+  {
+    tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+  } 
+  
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable External trigger and set the trigger source */
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+                hlptim->Init.Trigger.ActiveEdge |
+                hlptim->Init.Trigger.SampleTime);
+  }
+  
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the LPTIM peripheral. 
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the LPTIM handle allocation */
+  if(hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the LPTIM Peripheral Clock */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_LPTIM_MspDeInit(hlptim);
+  
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_RESET;
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hlptim);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the LPTIM MSP.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes LPTIM MSP.
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ *  @brief   Start-Stop operation functions. 
+ *
+@verbatim   
+  ==============================================================================
+                ##### LPTIM Start Stop operation functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start the PWM mode.
+      (+) Stop the PWM mode.
+      (+) Start the One pulse mode.
+      (+) Stop the One pulse mode.
+      (+) Start the Set once mode.
+      (+) Stop the Set once mode.
+      (+) Start the Encoder mode.
+      (+) Stop the Encoder mode.
+      (+) Start the Timeout mode.
+      (+) Stop the Timeout mode.      
+      (+) Start the Counter mode.
+      (+) Stop the Counter mode.
+      
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Starts the LPTIM PWM generation.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM PWM generation.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+ 
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+    /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM One pulse generation.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in single mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM One pulse generation.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM in Set once mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM Set once mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Pulse : Specifies the compare value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Pulse));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Compare write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  }  
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the pulse value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Compare write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* If external trigger source is used, then disable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Disable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+  } 
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Encoder interface.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  uint32_t tmpcfgr = 0U;
+   
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+  
+  /* Configure edge sensitivity for encoder mode */
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+  
+  /* Clear CKPOL bits */
+  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+  
+  /* Set Input polarity */
+  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+  
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+ 
+  /* Set ENC bit to enable the encoder interface */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Encoder interface.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Encoder interface in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  uint32_t tmpcfgr = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Configure edge sensitivity for encoder mode */
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+  
+  /* Clear CKPOL bits */
+  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+  
+  /* Set Input polarity */
+  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+  
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+ 
+  /* Set ENC bit to enable the encoder interface */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+  
+  /* Enable "switch to down direction" interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
+  
+  /* Enable "switch to up direction" interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);  
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Encoder interface in nterrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+  
+  /* Disable "switch to down direction" interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
+  
+  /* Disable "switch to up direction" interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); 
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Timeout function. The first trigger event will start the
+  *         timer, any successive trigger event will reset the counter and
+  *         the timer restarts.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Timeout : Specifies the TimeOut value to rest the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Timeout function.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Timeout function in interrupt mode. The first trigger 
+  *         event will start the timer, any successive trigger event will reset
+  *         the counter and the timer restarts.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  Timeout : Specifies the TimeOut value to rest the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;  
+  
+  /* Enable Compare match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Timeout function in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+  
+  /* Disable Compare match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Counter mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Counter mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the Counter mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @param  Period : Specifies the Autoreload value.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(Period));
+               
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+  
+  /* Enable Autoreload write complete interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Enable Autoreload match interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  
+  /* Load the period value in the autoreload register */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+  
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+    
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the Counter mode in interrupt mode.
+  * @param  hlptim : LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  /* Set the LPTIM state */
+  hlptim->State= HAL_LPTIM_STATE_BUSY;
+  
+  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+  
+  /* Disable Autoreload write complete interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
+  
+  /* Disable Autoreload match interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
+  
+  /* Change the TIM state*/
+  hlptim->State= HAL_LPTIM_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ *  @brief  Read operation functions.
+ *
+@verbatim   
+  ==============================================================================
+                  ##### LPTIM Read operation functions #####
+  ==============================================================================  
+[..]  This section provides LPTIM Reading functions.
+      (+) Read the counter value.
+      (+) Read the period (Auto-reload) value.
+      (+) Read the pulse (Compare)value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function returns the current counter value.
+  * @param  hlptim: LPTIM handle
+  * @retval Counter value.
+  */
+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->CNT);
+}
+
+/**
+  * @brief  This function return the current Autoreload (Period) value.
+  * @param  hlptim: LPTIM handle
+  * @retval Autoreload value.
+  */
+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->ARR);
+}
+
+/**
+  * @brief  This function return the current Compare (Pulse) value.
+  * @param  hlptim: LPTIM handle
+  * @retval Compare value.
+  */
+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+{
+    /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  
+  return (hlptim->Instance->CMP);
+}
+
+/**
+  * @}
+  */
+
+
+
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ *  @brief  LPTIM  IRQ handler.
+ *
+@verbatim   
+  ==============================================================================
+                      ##### LPTIM IRQ handler  #####
+  ==============================================================================  
+[..]  This section provides LPTIM IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles LPTIM interrupt request.
+  * @param  hlptim: LPTIM handle
+  * @retval None
+  */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Compare match interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
+    {
+      /* Clear Compare match flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+      
+      /* Compare match Callback */
+      HAL_LPTIM_CompareMatchCallback(hlptim);      
+    }
+  }
+  
+  /* Autoreload match interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
+    {
+      /* Clear Autoreload match flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+      
+      /* Autoreload match Callback */
+      HAL_LPTIM_AutoReloadMatchCallback(hlptim);      
+    }
+  }
+  
+  /* Trigger detected interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
+    {
+      /* Clear Trigger detected flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+      
+      /* Trigger detected callback */
+      HAL_LPTIM_TriggerCallback(hlptim);      
+    }
+  }
+  
+  /* Compare write interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) !=RESET)
+    {
+      /* Clear Compare write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+      
+      /* Compare write Callback */
+      HAL_LPTIM_CompareWriteCallback(hlptim);      
+    }
+  }
+  
+  /* Autoreload write interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
+    {
+      /* Clear Autoreload write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+      
+      /* Autoreload write Callback */
+      HAL_LPTIM_AutoReloadWriteCallback(hlptim);      
+    }
+  }
+  
+  /* Direction counter changed from Down to Up interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
+    {
+      /* Clear Direction counter changed from Down to Up flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+      
+      /* Direction counter changed from Down to Up Callback */
+      HAL_LPTIM_DirectionUpCallback(hlptim);      
+    }
+  }
+  
+  /* Direction counter changed from Up to Down interrupt */
+  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+  {
+    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
+    {
+      /* Clear Direction counter changed from Up to Down flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+      
+      /* Direction counter changed from Up to Down Callback */
+      HAL_LPTIM_DirectionDownCallback(hlptim);      
+    }
+  }
+
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+}
+
+/**
+  * @brief  Compare match callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Autoreload match callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Trigger detected callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_TriggerCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Compare write callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Autoreload write callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Direction counter changed from Down to Up callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @brief  Direction counter changed from Up to Down callback in non blocking mode 
+  * @param  hlptim : LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+   */  
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group5
+ *  @brief   Peripheral State functions. 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the LPTIM state.
+  * @param  hlptim: LPTIM handle
+  * @retval HAL state
+  */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+{
+  return hlptim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template-c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template-c
new file mode 100755
index 0000000..0308a1b
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_msp_template-c
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_msp_template.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  *          This file template is located in the HAL folder and should be copied 
+  *          to the user folder.
+  *         
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    This file is eventually modified by the user.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_MSP
+  * @brief HAL MSP module.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the Global BSP.
+  * @param  None
+  * @retval None
+  */
+void HAL_MspInit(void)
+{
+  /* NOTE : This function is eventually modified by the user */ 
+}
+
+/**
+  * @brief  DeInitializes the Global MSP.
+  * @param  None  
+  * @retval None
+  */
+void HAL_MspDeInit(void)
+{
+  /* NOTE : This function is eventually modified by the user */
+}
+
+/**
+  * @brief  Initializes the PPP MSP.
+  * @param  None
+  * @retval None
+  */
+void HAL_PPP_MspInit(void)
+{
+  /* NOTE : This function is eventually modified by the user */ 
+}
+
+/**
+  * @brief  DeInitializes the PPP MSP.
+  * @param  None  
+  * @retval None
+  */
+void HAL_PPP_MspDeInit(void)
+{
+  /* NOTE : This function is eventually modified by the user */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c
new file mode 100755
index 0000000..9cf95a7
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c
@@ -0,0 +1,1431 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+        
+     (#) Fill parameters of Init structure in HCD handle
+  
+     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) 
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using 
+              (+++) __HAL_RCC_USB_CLK_ENABLE();
+           
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+    
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable HCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#ifdef HAL_PCD_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+/** @addtogroup PCD_Private
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BTABLE_ADDRESS                  (0x000U)  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @addtogroup PCD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PCD_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and create the associated handle.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{ 
+  uint32_t i = 0U;
+
+  uint32_t wInterrupt_Mask = 0U;
+  
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  if(hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+  
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
+ {
+   /* Init ep structure */
+   hpcd->IN_ep[i].is_in = 1U;
+   hpcd->IN_ep[i].num = i;
+   /* Control until ep is actvated */
+   hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
+   hpcd->IN_ep[i].maxpacket =  0U;
+   hpcd->IN_ep[i].xfer_buff = 0U;
+   hpcd->IN_ep[i].xfer_len = 0U;
+ }
+ 
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
+ {
+   hpcd->OUT_ep[i].is_in = 0U;
+   hpcd->OUT_ep[i].num = i;
+   /* Control until ep is activated */
+   hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
+   hpcd->OUT_ep[i].maxpacket = 0U;
+   hpcd->OUT_ep[i].xfer_buff = 0U;
+   hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+  
+ /* Init Device */
+ /*CNTR_FRES = 1*/
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+ 
+ /*CNTR_FRES = 0*/
+ hpcd->Instance->CNTR = 0U;
+ 
+ /*Clear pending interrupts*/
+ hpcd->Instance->ISTR = 0U;
+ 
+  /*Set Btable Adress*/
+ hpcd->Instance->BTABLE = BTABLE_ADDRESS;
+ 
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+   | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+ 
+  /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+ 
+ hpcd->USB_Address = 0U;
+ hpcd->State= HAL_PCD_STATE_READY;
+  
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable ==1)
+ {
+   HAL_PCDEx_ActivateLPM(hpcd);
+ }  
+ /* Activate Battery charging */
+ if (hpcd->Init.battery_charging_enable ==1)
+ {
+   HAL_PCDEx_ActivateBCD(hpcd);
+  }
+ 
+ return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral 
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if(hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+  
+  /* Stop Device */
+  HAL_PCD_Stop(hpcd);
+    
+  /* DeInit the low level hardware */
+  HAL_PCD_MspDeInit(hpcd);
+  
+  hpcd->State = HAL_PCD_STATE_RESET;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup PCD_Exported_Functions_Group2
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Start The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{ 
+  /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+  hpcd->Instance->BCDR |= USB_BCDR_DPPU;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop The USB OTG Device.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{ 
+  __HAL_LOCK(hpcd); 
+  
+    /* disable all interrupts and force USB reset */
+  hpcd->Instance->CNTR = USB_CNTR_FRES;
+  
+  /* clear interrupt status register */
+  hpcd->Instance->ISTR = 0U;
+  
+  /* switch-off device */
+  hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+  
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles PCD interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  uint32_t wInterrupt_Mask = 0U;
+  
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    PCD_EP_ISR_Handler(hpcd);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+    HAL_PCD_ResetCallback(hpcd);
+    HAL_PCD_SetAddress(hpcd, 0U);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);    
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+  {
+    
+    hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+    
+    /*set wInterrupt_Mask global variable*/
+    wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+      | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+    /*Set interrupt mask*/
+    hpcd->Instance->CNTR = wInterrupt_Mask;
+
+    /* enable L1REQ interrupt */ 
+    if (hpcd->Init.lpm_enable ==1)
+    {
+      wInterrupt_Mask |= USB_CNTR_L1REQM;
+      
+      /* Enable LPM support and enable ACK answer to LPM request*/
+      USB_TypeDef *USBx = hpcd->Instance;
+      hpcd->lpm_active = ENABLE;
+      hpcd->LPM_State = LPM_L0;
+      
+      USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
+      USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
+    } 
+    
+    HAL_PCD_ResumeCallback(hpcd);
+    
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);     
+  }
+  
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+  {    
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);  
+    
+    /* Force low-power mode in the macrocell */
+    hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+    hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+    
+    if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
+    {
+      HAL_PCD_SuspendCallback(hpcd);
+    }
+  }
+  
+    /* Handle LPM Interrupt */ 
+  if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);      
+    if( hpcd->LPM_State == LPM_L0)
+    {   
+      /* Force suspend and low-power mode before going to L1 state*/
+      hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+      hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+      
+      hpcd->LPM_State = LPM_L1;
+      hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ;  
+      HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+    }
+    else
+    {
+      HAL_PCD_SuspendCallback(hpcd);
+    }
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+  {
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 
+    HAL_PCD_SOFCallback(hpcd);
+  }
+
+  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+  {
+    /* clear ESOF flag in ISTR */
+    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 
+  }
+}
+
+/**
+  * @brief  Data out stage callbacks
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Data IN stage callbacks
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Start Of Frame callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  USB Reset callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+
+/**
+  * @brief  Suspend event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Resume event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO OUT callbacks
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Incomplete ISO IN  callbacks
+  * @param  hpcd: PCD handle
+  * @param  epnum: endpoint number
+  * @retval None
+  */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Connection event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Disconnection event callbacks
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+  
+
+/** @addtogroup PCD_Exported_Functions_Group3
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  
+  /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+  hpcd->Instance->BCDR |= USB_BCDR_DPPU;
+  
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd); 
+  
+  /* Disable DP Pull-Down bit*/
+   hpcd->Instance->BCDR &= ((uint16_t) ~(USB_BCDR_DPPU));
+  
+  __HAL_UNLOCK(hpcd); 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address 
+  * @param  hpcd: PCD handle
+  * @param  address: new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+   __HAL_LOCK(hpcd); 
+
+   if(address == 0U) 
+   {
+     /* set device address and enable function */
+     hpcd->Instance->DADDR = USB_DADDR_EF;
+   }
+   else /* USB Address will be applied later */
+   {
+     hpcd->USB_Address = address;
+   }
+
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  ep_mps: endpoint max packert size
+  * @param  ep_type: endpoint type   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  PCD_EPTypeDef *ep;
+  
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+  }
+  ep->num   = ep_addr & 0x7FU;
+  
+  ep->is_in = (0x80U & ep_addr) != 0U;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+  
+  __HAL_LOCK(hpcd); 
+
+/* initialize Endpoint */
+  switch (ep->type)
+  {
+  case PCD_EP_TYPE_CTRL:
+    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
+    break;
+  case PCD_EP_TYPE_BULK:
+    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
+    break;
+  case PCD_EP_TYPE_INTR:
+    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
+    break;
+  case PCD_EP_TYPE_ISOC:
+    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
+    break;
+  } 
+  
+  PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
+  
+  if (ep->doublebuffer == 0U) 
+  {
+    if (ep->is_in)
+    {
+      /*Set the endpoint Transmit buffer address */
+      PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      /* Configure NAK status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 
+    }
+    else
+    {
+      /*Set the endpoint Receive buffer address */
+      PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+      /*Set the endpoint Receive buffer counter*/
+      PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      /* Configure VALID status for the Endpoint*/
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+    }
+  }
+  /*Double Buffer*/
+  else
+  {
+    /*Set the endpoint as double buffered*/
+    PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
+    /*Set buffer address for double buffered mode*/
+    PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+    
+    if (ep->is_in==0U)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      
+      /* Reset value of the data toggle bits for the endpoint out*/
+      PCD_TX_DTOG(hpcd->Instance, ep->num);
+      
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_RX_DTOG(hpcd->Instance, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+    }
+  } 
+  
+  __HAL_UNLOCK(hpcd);   
+  return ret;
+}
+
+
+/**
+  * @brief  Deactivate an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{  
+  PCD_EPTypeDef *ep;
+  
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+  }
+  ep->num   = ep_addr & 0x7FU;
+  
+  ep->is_in = (0x80U & ep_addr) != 0U;
+  
+  __HAL_LOCK(hpcd); 
+
+  if (ep->doublebuffer == 0U) 
+  {
+    if (ep->is_in)
+    {
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); 
+    }
+    else
+    {
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+    }
+  }
+  /*Double Buffer*/
+  else
+  { 
+    if (ep->is_in==0U)
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      
+      /* Reset value of the data toggle bits for the endpoint out*/
+      PCD_TX_DTOG(hpcd->Instance, ep->num);
+      
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+    }
+    else
+    {
+      /* Clear the data toggle bits for the endpoint IN/OUT*/
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_RX_DTOG(hpcd->Instance, ep->num);
+      /* Configure DISABLE status for the Endpoint*/
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+    }
+  } 
+  
+  __HAL_UNLOCK(hpcd);   
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data  
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the reception buffer   
+  * @param  len: amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  
+ PCD_EPTypeDef *ep;
+  
+  ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & 0x7FU;
+
+  /* Multi packet transfer*/
+  if (ep->xfer_len > ep->maxpacket)
+  {
+    len=ep->maxpacket;
+    ep->xfer_len-=len; 
+  }
+  else
+  {
+    len=ep->xfer_len;
+    ep->xfer_len =0U;
+  }
+  
+  /* configure and validate Rx endpoint */
+  if (ep->doublebuffer == 0U) 
+  {
+    /*Set RX buffer count*/
+    PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
+  }
+  else
+  {
+    /*Set the Double buffer counter*/
+    PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+  } 
+  
+  PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval Data Size
+  */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
+}
+/**
+  * @brief  Send an amount of data  
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @param  pBuf: pointer to the transmission buffer   
+  * @param  len: amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+  uint16_t pmabuffer = 0U;
+    
+  ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;  
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & 0x7FU;
+
+  /*Multi packet transfer*/
+  if (ep->xfer_len > ep->maxpacket)
+  {
+    len=ep->maxpacket;
+    ep->xfer_len-=len; 
+  }
+  else
+  {  
+    len=ep->xfer_len;
+    ep->xfer_len =0U;
+  }
+  
+  /* configure and validate Tx endpoint */
+  if (ep->doublebuffer == 0U) 
+  {
+    PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
+    PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
+  }
+  else
+  {
+    /*Set the Double buffer counter */
+    PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+    
+    /*Write the data to the USB endpoint*/
+    if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
+    {
+      pmabuffer = ep->pmaaddr1;
+    }
+    else
+    {
+      pmabuffer = ep->pmaaddr0;
+    }
+    
+    PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
+    PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
+  }
+
+  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+   
+  __HAL_LOCK(hpcd); 
+   
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 1U;
+  ep->num   = ep_addr & 0x7FU;
+  ep->is_in = ((ep_addr & 0x80U) == 0x80U);
+  
+  if (ep->num == 0U)
+  {
+    /* This macro sets STALL status for RX & TX*/ 
+    PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); 
+  }
+  else
+  {
+    if (ep->is_in)
+    {
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); 
+    }
+    else
+    {
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
+    }
+  }
+  __HAL_UNLOCK(hpcd); 
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+  
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  ep->is_stall = 0U;
+  ep->num   = ep_addr & 0x7FU;
+  ep->is_in = ((ep_addr & 0x80U) == 0x80U);
+  
+  __HAL_LOCK(hpcd); 
+  
+  if (ep->is_in)
+  {
+    PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+    PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+  }
+  else
+  {
+    PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+    PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+  }
+  __HAL_UNLOCK(hpcd); 
+    
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd: PCD handle
+  * @param  ep_addr: endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{ 
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
+  * @param  hpcd: PCD handle
+  * @retval status
+*/
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  if (hpcd->Init.lpm_enable ==1)
+  {
+    /* Apply L1 Resume */
+    hpcd->Instance->CNTR |= USB_CNTR_L1RESUME;
+  }
+  else
+  {
+    /* Apply L2 Resume */
+    hpcd->Instance->CNTR |= USB_CNTR_RESUME;
+  }
+  return (HAL_OK);
+}
+
+/**
+  * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
+  * @param  hpcd: PCD handle
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  if (hpcd->Init.lpm_enable ==1)
+  {
+    /* Release L1 Resume */
+    hpcd->Instance->CNTR &= ~ USB_CNTR_L1RESUME;
+  }
+  else
+  {
+    /* Release L2 Resume */
+    hpcd->Instance->CNTR &= ~ USB_CNTR_RESUME;
+  }
+  return (HAL_OK);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup PCD_Exported_Functions_Group4
+ *  @brief   Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD state
+  * @param  hpcd: PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup PCD_Private
+  * @{
+  */
+
+
+/**
+  * @brief Copy a buffer from user memory area to packet memory area (PMA)
+  * @param   USBx: USB device
+  * @param   pbUsrBuf: pointer to user memory area.
+  * @param   wPMABufAddr: address into PMA.
+  * @param   wNBytes: no. of bytes to be copied.
+  * @retval None
+  */
+void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1U) >> 1U;
+  uint32_t i;
+  uint16_t temp1, temp2;
+  uint16_t *pdwVal;
+  pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U);
+
+  for (i = n; i != 0U; i--)
+  {
+    temp1 = (uint16_t) * pbUsrBuf;
+    pbUsrBuf++;
+    temp2 = temp1 | (uint16_t) * pbUsrBuf << 8U;
+    *pdwVal++ = temp2;
+    pbUsrBuf++;
+  }
+}
+
+/**
+  * @brief Copy a buffer from user memory area to packet memory area (PMA)
+  * @param   USBx: USB device
+  * @param   pbUsrBuf: pointer to user memory area.
+  * @param   wPMABufAddr: address into PMA.
+  * @param   wNBytes: no. of bytes to be copied.
+  * @retval None
+  */
+void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+  uint32_t n = (wNBytes + 1U) >> 1U;
+  uint32_t i;
+  uint16_t *pdwVal;
+  pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400U);
+  for (i = n; i != 0U; i--)
+  {
+    *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+    pbUsrBuf++;
+  }
+}
+/**
+  * @brief  This function handles PCD Endpoint interrupt request.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+  PCD_EPTypeDef *ep;
+  uint16_t count=0U;
+  uint8_t EPindex;
+  __IO uint16_t wIstr;  
+  __IO uint16_t wEPVal = 0U;
+  
+  /* stay in loop while pending interrupts */
+  while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
+  {
+    /* extract highest priority endpoint number */
+    EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+    
+    if (EPindex == 0U)
+    {
+      /* Decode and service control endpoint interrupt */
+      
+      /* DIR bit = origin of the interrupt */   
+      if ((wIstr & USB_ISTR_DIR) == 0U)
+      {
+        /* DIR = 0 */
+        
+        /* DIR = 0      => IN  int */
+        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+        ep = &hpcd->IN_ep[0];
+        
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+        ep->xfer_buff += ep->xfer_count;
+ 
+        /* TX COMPLETE */
+        HAL_PCD_DataInStageCallback(hpcd, 0U);
+        
+        
+        if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
+        {
+          hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+          hpcd->USB_Address = 0U;
+        }
+        
+      }
+      else
+      {
+        /* DIR = 1 */
+        
+        /* DIR = 1 & CTR_RX       => SETUP or OUT int */
+        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+        ep = &hpcd->OUT_ep[0];
+        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+        
+        if ((wEPVal & USB_EP_SETUP) != 0U)
+        {
+          /* Get SETUP Packet*/
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);       
+          /* SETUP bit kept frozen while CTR_RX = 1*/ 
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 
+          
+          /* Process SETUP Packet*/
+          HAL_PCD_SetupStageCallback(hpcd);
+        }
+        
+        else if ((wEPVal & USB_EP_CTR_RX) != 0U)
+        {
+          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+          /* Get Control Data OUT Packet*/
+          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          
+          if (ep->xfer_count != 0U)
+          {
+            PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+            ep->xfer_buff+=ep->xfer_count;
+          }
+          
+          /* Process Control Data OUT Packet*/
+           HAL_PCD_DataOutStageCallback(hpcd, 0U);
+          
+          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+        }
+      }
+    }
+    else
+    {
+      
+      /* Decode and service non control endpoints interrupt  */
+      
+      /* process related endpoint register */
+      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+      if ((wEPVal & USB_EP_CTR_RX) != 0U)
+      {  
+        /* clear int flag */
+        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
+        ep = &hpcd->OUT_ep[EPindex];
+        
+        /* OUT double Buffering*/
+        if (ep->doublebuffer == 0U)
+        {
+          count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+          if (count != 0U)
+          {
+            PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+          }
+        }
+        else
+        {
+          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+          {
+            /*read from endpoint BUF0Addr buffer*/
+            count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+            if (count != 0U)
+            {
+              PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+            }
+          }
+          else
+          {
+            /*read from endpoint BUF1Addr buffer*/
+            count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+            if (count != 0U)
+            {
+              PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+            }
+          }
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);  
+        }
+        /*multi-packet on the NON control OUT endpoint*/
+        ep->xfer_count+=count;
+        ep->xfer_buff+=count;
+       
+        if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
+        {
+          /* RX COMPLETE */
+          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+        }
+        else
+        {
+          HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+        }
+        
+      } /* if((wEPVal & EP_CTR_RX) */
+      
+      if ((wEPVal & USB_EP_CTR_TX) != 0U)
+      {
+        ep = &hpcd->IN_ep[EPindex];
+        
+        /* clear int flag */
+        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
+        
+        /* IN double Buffering*/
+        if (ep->doublebuffer == 0U)
+        {
+          ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+          if (ep->xfer_count != 0U)
+          {
+            PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+          }
+        }
+        else
+        {
+          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+          {
+            /*read from endpoint BUF0Addr buffer*/
+            ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+            if (ep->xfer_count != 0U)
+            {
+              PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+            }
+          }
+          else
+          {
+            /*read from endpoint BUF1Addr buffer*/
+            ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+            if (ep->xfer_count != 0U)
+            {
+              PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+            }
+          }
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);  
+        }
+        /*multi-packet on the NON control IN endpoint*/
+        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+        ep->xfer_buff+=ep->xfer_count;
+       
+        /* Zero Length Packet? */
+        if (ep->xfer_len == 0U)
+        {
+          /* TX COMPLETE */
+          HAL_PCD_DataInStageCallback(hpcd, ep->num);
+        }
+        else
+        {
+          HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+        }
+      } 
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_PCD_MODULE_ENABLED */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c
new file mode 100755
index 0000000..99036a7
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PCD HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Configururation of the PMA for EP
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+#ifdef HAL_PCD_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @brief PCDEx HAL module driver
+  * @{
+  */
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup PCDEx__Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                 ##### Peripheral extended features functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure PMA for EP
+  * @param  hpcd : Device instance
+  * @param  ep_addr: endpoint address
+  * @param  ep_kind: endpoint Kind
+  *                  USB_SNG_BUF: Single Buffer used
+  *                  USB_DBL_BUF: Double Buffer used
+  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  *                   this parameter is 16-bit value providing the address
+  *                   in PMA allocated to endpoint.
+  *                   In case of double buffer endpoint this parameter
+  *                   is a 32-bit value providing the endpoint buffer 0 address
+  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
+  *                   in the MSB part of 32-bit value.
+  * @retval : status
+  */
+
+
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
+                        uint16_t ep_addr,
+                        uint16_t ep_kind,
+                        uint32_t pmaadress)
+
+{
+  PCD_EPTypeDef *ep;
+  
+  /* initialize ep structure*/
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+  
+  /* Here we check if the endpoint is single or double Buffer*/
+  if (ep_kind == PCD_SNG_BUF)
+  {
+    /*Single Buffer*/
+    ep->doublebuffer = 0U;
+    /*Configure te PMA*/
+    ep->pmaadress = (uint16_t)pmaadress;
+  }
+  else /*USB_DBL_BUF*/
+  {
+    /*Double Buffer Endpoint*/
+    ep->doublebuffer = 1U;
+    /*Configure the PMA*/
+    ep->pmaaddr0 =  pmaadress & 0xFFFFU;
+    ep->pmaaddr1 =  (pmaadress & 0xFFFF0000U) >> 16U;
+  }
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = ENABLE;
+  
+  USBx->BCDR |= (USB_BCDR_BCDEN);
+  /* Enable DCD : Data Contact Detect */
+  USBx->BCDR |= (USB_BCDR_DCDEN);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = DISABLE;
+  
+  USBx->BCDR &= ~(USB_BCDR_BCDEN);
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+   
+  /* Wait Detect flag or a timeout is happen*/
+  while ((USBx->BCDR & USB_BCDR_DCDET) == 0)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > 1000)
+    {
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+      return;
+    }
+  }
+
+  HAL_Delay(300);
+  
+  /* Data Pin Contact ? Check Detect flag */
+  if (USBx->BCDR & USB_BCDR_DCDET)
+  {
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+  }   
+  /* Primary detection: checks if connected to Standard Downstream Port  
+  (without charging capability) */
+  USBx->BCDR &= ~(USB_BCDR_DCDEN);
+  USBx->BCDR |= (USB_BCDR_PDEN);
+  HAL_Delay(300);
+  
+  /* If Charger detect ? */
+  if (USBx->BCDR & USB_BCDR_PDET)
+  {
+    /* Start secondary detection to check connection to Charging Downstream 
+    Port or Dedicated Charging Port */
+    USBx->BCDR &= ~(USB_BCDR_PDEN);
+    USBx->BCDR |= (USB_BCDR_SDEN);
+    HAL_Delay(300);
+    
+    /* If CDP ? */
+    if (USBx->BCDR & USB_BCDR_SDET)
+    {
+      /* Dedicated Downstream Port DCP */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+    }
+    else
+    {
+      /* Charging Downstream Port CDP */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+    }
+  }
+  else
+  {
+    /* Standard Downstream Port */
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+  }
+  /* Battery Charging capability discovery finished 
+  Start Enumeration*/
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+
+  USB_TypeDef *USBx = hpcd->Instance;
+  hpcd->lpm_active = ENABLE;
+  hpcd->LPM_State = LPM_L0;
+  
+  USBx->LPMCSR |= (USB_LPMCSR_LMPEN);
+  USBx->LPMCSR |= (USB_LPMCSR_LPMACK);
+    
+ 
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_TypeDef *USBx = hpcd->Instance; 
+  
+  hpcd->lpm_active = DISABLE;
+  
+  USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN);
+  USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_PCD_MODULE_ENABLED */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
new file mode 100755
index 0000000..d368aed
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c
@@ -0,0 +1,523 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The RNG HAL driver can be used as follows:
+    
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro.  
+          in HAL_RNG_MspInit().
+      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+      (#) Wait until the 32 bit Random Number Generator contains a valid 
+          random data using (polling/interrupt) mode.   
+      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+
+#if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) ||  defined (STM32L063xx) || \
+    defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) ||  defined (STM32L083xx)
+
+/** @addtogroup RNG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private Defines -----------------------------------------------------------*/
+/** @addtogroup RNG_Private
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     1000U
+/**
+  * @}
+  */ 
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters 
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP
+      (+) DeInitialize RNG MSP 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the RNG peripheral and creates the associated handle.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+  
+  __HAL_LOCK(hrng);
+  
+  if(hrng->State == HAL_RNG_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+  
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+  
+  __HAL_UNLOCK(hrng);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the RNG peripheral. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Disable the RNG Peripheral */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+  
+  /* Clear RNG interrupt status flags */
+  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+  
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+  
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspDeInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+ *  @brief   Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request 
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Generates a 32-bit random number.
+  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
+  *         is automatically cleared.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @param  random32bit: pointer to generated random number variable if successful.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+  uint32_t tickstart = 0U;    
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng); 
+  
+  /* Check RNG peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+  
+    /* Check if data register contains valid random data */
+    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+      {    
+        hrng->State = HAL_RNG_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+      
+        return HAL_TIMEOUT;
+      } 
+    }
+  
+    /* Get a 32bit Random number */
+    hrng->RandomNumber = hrng->Instance->DR;
+    *random32bit = hrng->RandomNumber;
+  
+    hrng->State = HAL_RNG_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+
+  return status;
+}
+
+/**
+  * @brief  Generates a 32-bit random number in interrupt mode.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+  
+  /* Check RNG peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+    __HAL_RNG_ENABLE_IT(hrng);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    status = HAL_ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handles RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User has 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
+  *         The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.  
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  /* RNG clock error interrupt occurred */
+  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+  { 
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+  
+    HAL_RNG_ErrorCallback(hrng);
+    
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
+    
+  }
+  
+  /* Check RNG data ready interrupt occurred */    
+  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+    
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
+    hrng->RandomNumber = hrng->Instance->DR;
+    
+    if(hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY; 
+      
+      /* Data Ready callback */ 
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+    } 
+  }
+} 
+
+/**
+  * @brief  return generated random number in polling mode (Obsolete).
+  *         Use HAL_RNG_GenerateRandomNumber() API instead.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval random value
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+  {
+    return hrng->RandomNumber; 
+  }
+  else
+  {
+    return 0U;
+  }
+}
+
+
+/**
+  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
+  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+  * @param  hrng: RNG handle
+  * @retval 32-bit random number
+  */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  uint32_t random32bit = 0U;
+  
+  /* Process locked */
+  __HAL_LOCK(hrng);
+  
+  /* Change RNG peripheral state */  
+  hrng->State = HAL_RNG_STATE_BUSY;  
+  
+  /* Get a 32bit Random number */ 
+  random32bit = hrng->Instance->DR;
+  
+  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+  __HAL_RNG_ENABLE_IT(hrng); 
+  
+  /* Return the 32 bit random number */   
+  return random32bit;
+}
+
+
+
+/**
+  * @brief  Read latest generated random number. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval random value
+  */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  return(hrng->RandomNumber);
+}
+
+/**
+  * @brief  Data Ready callback in non-blocking mode. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure..
+  * @param  random32bit: generated random value
+  * @retval None
+  */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  RNG error callbacks.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ErrorCallback must be implemented in the user file.
+   */
+}
+ 
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the RNG state.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+  return hrng->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /*  if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) ||  defined (STM32L063xx) || \
+           defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) ||  defined (STM32L083xx)         */
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c
new file mode 100755
index 0000000..9df3f37
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c
@@ -0,0 +1,2291 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smartcard.c
+  * @author  MCD Application Team
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SMARTCARD peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The SMARTCARD HAL driver can be used as follows:
+
+    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+    (#) Associate a USART to the SMARTCARD handle hsmartcard.
+    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+             and HAL_SMARTCARD_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+             and HAL_SMARTCARD_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+        error enabling or disabling in the hsmartcard handle Init structure.
+
+    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+        in the hsmartcard handle AdvancedInit structure.
+
+    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMARTCARD_MspInit() API.
+        [..]
+        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+    [..]
+    [..] Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** SMARTCARD HAL driver macros list ***
+     ========================================
+     [..]
+       Below the list of most used macros in SMARTCARD HAL driver.
+
+       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+     [..]
+       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARD SMARTCARD
+  * @brief HAL SMARTCARD module driver
+  * @{
+  */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT               1000U     /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
+
+#define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))       /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  associated to the SmartCard.
+  (+) These parameters can be configured:
+      (++) Baud Rate
+      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+      (++) Receiver/transmitter modes
+      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+      (++) Prescaler value
+      (++) Guard bit time
+      (++) NACK enabling or disabling on transmission error
+
+  (+) The following advanced features can be configured as well:
+      (++) TX and/or RX pin level inversion
+      (++) data logical level inversion
+      (++) RX and TX pins swap
+      (++) RX overrun detection disabling
+      (++) DMA disabling on RX error
+      (++) MSB first on communication line
+      (++) Time out enabling (and if activated, timeout value)
+      (++) Block length
+      (++) Auto-retry counter
+  [..]
+  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  The USART frame format is given in the following table:
+
+    Table 1. USART frame format.
+    +---------------------------------------------------------------+        
+    | M1M0 bits |  PCE bit  |            USART frame                |        
+    |-----------------------|---------------------------------------|        
+    |     01    |    1      |    | SB | 8 bit data | PB | STB |     |        
+    +---------------------------------------------------------------+        
+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMARTCARD mode according to the specified
+  *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmartcard->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_SMARTCARD_MspInit(hsmartcard);
+  }
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral to set smartcard mode */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* In SmartCard mode, the following bits must be kept cleared:
+  - LINEN in the USART_CR2 register,
+  - HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* set the USART in SMARTCARD mode */
+  SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+  /* Set the SMARTCARD Communication parameters */
+  if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+  {
+    SMARTCARD_AdvFeatureConfig(hsmartcard);
+  }
+
+  if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Enable the Peripheral */
+  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+  return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD peripheral.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  WRITE_REG(hsmartcard->Instance->CR1, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR2, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR3, 0x0);
+  WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
+  WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
+
+  /* DeInit the low level hardware */
+  HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
+  hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+  *  @brief   SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+  [..]
+    Smartcard is a single wire half duplex communication protocol.
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard. The USART should be configured as:
+    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+  [..]
+    (+) There are two modes of transfer:
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: The communication is performed using Interrupts
+             or DMA, the relevant API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+             error is detected.
+
+    (+) Blocking mode APIs are :
+        (++) HAL_SMARTCARD_Transmit()
+        (++) HAL_SMARTCARD_Receive()
+
+    (+) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_SMARTCARD_Transmit_IT()
+        (++) HAL_SMARTCARD_Receive_IT()
+        (++) HAL_SMARTCARD_IRQHandler()
+
+    (+) Non Blocking mode functions with DMA are :
+        (++) HAL_SMARTCARD_Transmit_DMA()
+        (++) HAL_SMARTCARD_Receive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SMARTCARD_TxCpltCallback()
+        (++) HAL_SMARTCARD_RxCpltCallback()
+        (++) HAL_SMARTCARD_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_SMARTCARD_Abort()
+        (+) HAL_SMARTCARD_AbortTransmit()
+        (+) HAL_SMARTCARD_AbortReceive()
+        (+) HAL_SMARTCARD_Abort_IT()
+        (+) HAL_SMARTCARD_AbortTransmit_IT()
+        (+) HAL_SMARTCARD_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_SMARTCARD_AbortCpltCallback()
+        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @param  Timeout  Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+    
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+    while(hsmartcard->TxXferCount > 0U)
+    {
+      hsmartcard->TxXferCount--;
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+    }
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+    if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+    {
+      /* Disable the Peripheral first to update modes */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+      /* Enable the Peripheral */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    }
+    
+    /* At end of Tx process, restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0;
+
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Check the remain data to be received */
+    while(hsmartcard->RxXferCount > 0U)
+    {
+      hsmartcard->RxXferCount--;
+
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FFU);
+    }
+
+    /* At end of Rx process, restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+    /* Set the SMARTCARD error callback */
+    hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the SMARTCARD transmit DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the UART Error Interrupt: (Frame error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
+  *         the received data contain the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+    /* Set the SMARTCARD DMA error callback */
+    hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  hsmartcard->TxXferCount = 0; 
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hsmartcard->TxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* SMARTCARD Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        hsmartcard->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* SMARTCARD Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        hsmartcard->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hsmartcard->TxXferCount = 0; 
+    hsmartcard->RxXferCount = 0;
+
+    /* Reset errorCode */
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+    hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+        hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hsmartcard->TxXferCount = 0; 
+
+      /* Restore hsmartcard->gState to Ready */
+      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hsmartcard->TxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+    /* Restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+        hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hsmartcard->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+      /* Restore hsmartcard->RxState to Ready */
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hsmartcard->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle SMARTCARD interrupt requests.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == RESET)
+  {
+    /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      SMARTCARD_Receive_IT(hsmartcard);
+      /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(hsmartcard->Instance->CR3);
+  if(   (errorflags != RESET) 
+     && (    ((cr3its & USART_CR3_EIE) != RESET)
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+  {
+    /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
+
+    /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+
+    /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+    }
+
+    /* Call SMARTCARD Error Call back function if need be --------------------------*/
+    if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        SMARTCARD_Receive_IT(hsmartcard);
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      if (   ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+          || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if(hsmartcard->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+              hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      /* other error type to be considered as blocking :
+          - Frame error in Transmission
+      */
+      else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+      {
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+        SMARTCARD_EndTxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Tx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+          /* Abort the SMARTCARD DMA Tx channel */
+          if(hsmartcard->hdmatx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA TX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+              hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+  if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+  {
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+    __HAL_UNLOCK(hsmartcard);
+    HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+    /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+     * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+    __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    SMARTCARD_Transmit_IT(hsmartcard);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+  if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+  {
+    SMARTCARD_EndTransmit_IT(hsmartcard);
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD error callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Receive Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   SMARTCARD State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of SmartCard
+    handle and also return Peripheral Errors occurred during communication process
+     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+         of the SMARTCARD peripheral.
+     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMARTCARD handle state.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle state
+  */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Return SMARTCARD handle state */
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = hsmartcard->gState;
+  temp2 = hsmartcard->RxState;
+
+  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the SMARTCARD handle error code.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  return hsmartcard->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+  * @{
+  */
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpreg                          = 0x00000000U;
+  SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret                    = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+  assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+  assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+  assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+  assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+  assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+  assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+  assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+  assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+  assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+   * Oversampling is forced to 16 (OVER8 = 0).
+   * Configure the Parity and Mode:
+   *  set PS bit according to hsmartcard->Init.Parity value
+   *  set TE and RE bits according to hsmartcard->Init.Mode value */
+  tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+  /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor 
+     the bidirectional line to detect a NACK signal in case of parity error. 
+     Therefore, the receiver block must be enabled as well (RE bit must be set). */
+  if((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+  {
+    tmpreg |= USART_CR1_RE;   
+  }
+  tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = hsmartcard->Init.StopBits;
+  /* Synchronous mode is activated by default */
+  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+  tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+  tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+  MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+   * - one-bit sampling method versus three samples' majority rule
+   *   according to hsmartcard->Init.OneBitSampling
+   * - NACK transmission in case of parity error according
+   *   to hsmartcard->Init.NACKEnable
+   * - autoretry counter according to hsmartcard->Init.AutoRetryCount     */
+  tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+  tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+  MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+  MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+  /*-------------------------- USART RTOR Configuration ----------------------*/
+  tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+  if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+  {
+    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+    tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
+  }
+  MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+  switch (clocksource)
+  {
+    case SMARTCARD_CLOCKSOURCE_PCLK1:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PCLK2:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_HSI:
+      hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_SYSCLK:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_LSE:
+      hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+  }
+
+}
+
+/**
+  * @brief Check the SMARTCARD Idle State.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the SMARTCARD ErrorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the SMARTCARD states */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMARTCARD Communication Timeout.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  Flag Specifies the SMARTCARD flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+        hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmartcard);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Tx process, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  DMA SMARTCARD transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->TxXferCount = 0;
+
+  /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+  in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+  /* Enable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+}
+
+/**
+  * @brief  DMA SMARTCARD receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+
+  /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+     in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  if (  (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    hsmartcard->TxXferCount = 0;
+    SMARTCARD_EndTxTransfer(hsmartcard);
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  if (  (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    hsmartcard->RxXferCount = 0;
+    SMARTCARD_EndRxTransfer(hsmartcard);
+  }
+
+  hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+  hsmartcard->TxXferCount = 0;
+
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  hsmartcard->TxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+  hsmartcard->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief Send an amount of data in non-blocking mode.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Tx process is ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    if(hsmartcard->TxXferCount == 0U)
+    {
+      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the SMARTCARD Transmit Complete Interrupt */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
+
+      return HAL_OK;
+    }
+    else
+    {
+      hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
+      hsmartcard->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable the SMARTCARD Transmit Complete Interrupt */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+  if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+  {
+    /* Disable the Peripheral first to update modes */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+  }
+  
+  /* Tx process is ended, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Rx process is ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFFU);
+
+    if(--hsmartcard->RxXferCount == 0U)
+    {
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+      /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+      if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+      {
+        /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+      }
+
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c
new file mode 100755
index 0000000..14b99f3
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard_ex.c
@@ -0,0 +1,207 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smartcard_ex.c
+  * @author  MCD Application Team
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides extended firmware functions to manage the following
+  *          functionalities of the SmartCard.
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  =============================================================================
+               ##### SMARTCARD peripheral extended features  #####
+  =============================================================================
+  [..]
+  The Extended SMARTCARD HAL driver can be used as follows:
+
+    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+  * @brief SMARTCARD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @brief    Extended control functions
+  *
+@verbatim
+  ===============================================================================
+                      ##### Peripheral Control functions #####
+  ===============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the SMARTCARD.
+     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Update on the fly the SMARTCARD block length in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param BlockLength: SMARTCARD block length (8-bit long at most)
+  * @retval None
+  */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+  * @brief Update on the fly the receiver timeout value in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+  * @brief Enable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Set the USART RTOEN bit */
+    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Disable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Clear the USART RTOEN bit */
+    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c
new file mode 100755
index 0000000..0ad8200
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c
@@ -0,0 +1,2161 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_smbus.c
+  * @author  MCD Application Team
+  * @brief   SMBUS HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the System Management Bus (SMBus) peripheral,
+  *          based on I2C principles of operation :
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The SMBUS HAL driver can be used as follows:
+
+    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+        SMBUS_HandleTypeDef  hsmbus;
+
+    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+        (##) Enable the SMBUSx interface clock
+        (##) SMBUS pins configuration
+            (+++) Enable the clock for the SMBUS GPIOs
+            (+++) Configure SMBUS pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the SMBUSx interrupt priority
+            (+++) Enable the NVIC SMBUS IRQ Channel
+
+    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+    (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+      (++) The associated previous transfer callback is called at the end of abort process
+      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+      (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
+      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Alert Error Code using function HAL_SMBUS_GetError()
+      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Error Code using function HAL_SMBUS_GetError()
+
+     *** SMBUS HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in SMBUS HAL driver.
+
+      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
+      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
+      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
+      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
+      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
+      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
+
+     [..]
+       (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUS SMBUS
+  * @brief SMBUS HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)      /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
+#define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
+#define MAX_NBYTE_SIZE      255U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the SMBUSx peripheral:
+
+      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Bus Timeout
+        (++) Analog Filer mode
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+        (++) Packet Error Check mode
+        (++) Peripheral mode
+
+
+      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+          of the selected SMBUSx peripheral.
+
+      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+          HAL_SMBUS_ConfigDigitalFilter().
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMBUS according to the specified parameters
+  *         in the SMBUS_InitTypeDef and initialize the associated handle.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the SMBUS handle allocation */
+  if (hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+  assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+  assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+  assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+  assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+  assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+  assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+  assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+  assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+  assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmbus->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_SMBUS_MspInit(hsmbus);
+  }
+
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+  /* Disable the selected SMBUS peripheral */
+  __HAL_SMBUS_DISABLE(hsmbus);
+
+  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+  /* Configure SMBUSx: Frequency range */
+  hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+  /* Configure SMBUSx: Bus Timeout  */
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+  hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+  /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+  /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+  hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  if (hsmbus->Init.OwnAddress1 != 0U)
+  {
+    if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+    {
+      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+    }
+    else /* SMBUS_ADDRESSINGMODE_10BIT */
+    {
+      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+    }
+  }
+
+  /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+  /* Configure SMBUSx: Addressing Master mode */
+  if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+  {
+    hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+  /* AUTOEND and NACK bit will be manage during Transfer process */
+  hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+  /* Configure SMBUSx: Dual mode and Own Address2 */
+  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+
+  /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+  /* Configure SMBUSx: Generalcall and NoStretch mode */
+  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+
+  /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
+  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+      && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+  {
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+  }
+
+  /* Enable the selected SMBUS peripheral */
+  __HAL_SMBUS_ENABLE(hsmbus);
+
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+  hsmbus->State = HAL_SMBUS_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SMBUS peripheral.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the SMBUS handle allocation */
+  if (hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
+
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+  /* Disable the SMBUS Peripheral Clock */
+  __HAL_SMBUS_DISABLE(hsmbus);
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_SMBUS_MspDeInit(hsmbus);
+
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
+  hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Configure Analog noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
+  *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Reset ANOFF bit */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hsmbus->Instance->CR1 |= AnalogFilter;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure Digital noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Get the old register value */
+    tmpreg = hsmbus->Instance->CR1;
+
+    /* Reset I2C DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+    /* Store the new register value */
+    hsmbus->Instance->CR1 = tmpreg;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the SMBUS data
+    transfers.
+
+    (#) Blocking mode function to check if device is ready for usage is :
+        (++) HAL_SMBUS_IsDeviceReady()
+
+    (#) There is only one mode of transfer:
+       (++) Non-Blocking mode : The communication is performed using Interrupts.
+            These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated SMBUS IRQ when using Interrupt mode.
+
+    (#) Non-Blocking mode functions with Interrupt are :
+        (++) HAL_SMBUS_Master_Transmit_IT()
+        (++) HAL_SMBUS_Master_Receive_IT()
+        (++) HAL_SMBUS_Slave_Transmit_IT()
+        (++) HAL_SMBUS_Slave_Receive_IT()
+        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+        (++) HAL_SMBUS_DisableListen_IT()
+        (++) HAL_SMBUS_EnableAlert_IT()
+        (++) HAL_SMBUS_DisableAlert_IT()
+
+    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+        (++) HAL_SMBUS_MasterTxCpltCallback()
+        (++) HAL_SMBUS_MasterRxCpltCallback()
+        (++) HAL_SMBUS_SlaveTxCpltCallback()
+        (++) HAL_SMBUS_SlaveRxCpltCallback()
+        (++) HAL_SMBUS_AddrCallback()
+        (++) HAL_SMBUS_ListenCpltCallback()
+        (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if (hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+    {
+      SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+      }
+
+      /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      {
+        hsmbus->XferSize--;
+        hsmbus->XferCount--;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if (hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+    {
+      SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master/host SMBUS process communication with Interrupt.
+  * @note   This abort can be called only if state is ready
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    /* Keep the same state as previous */
+    /* to perform as well the call of the corresponding end of transfer callback */
+    if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    }
+    else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Wrong usage of abort function */
+      /* This function should be used only in case of abort monitored by master device */
+      return HAL_ERROR;
+    }
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+    }
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+    {
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      /* Set NBYTE to transmit */
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+      /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+      {
+        hsmbus->XferSize--;
+        hsmbus->XferCount--;
+      }
+    }
+
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferSize = Size;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    /* Set NBYTE to receive */
+    /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+    /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+    /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+    /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+    if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+    {
+      SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+    }
+
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+  /* Enable the Address Match interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Disable the Address Match interrupt */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+  /* Clear ALERT flag */
+  __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+  /* Enable Alert Interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+  /* Disable Alert Interrupt */
+  SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if target device is ready for communication.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shift at right before call interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  __IO uint32_t SMBUS_Trials = 0U;
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+      while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+          {
+            /* Device is ready */
+            hsmbus->State = HAL_SMBUS_STATE_READY;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hsmbus);
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+        /* Device is ready */
+        hsmbus->State = HAL_SMBUS_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (SMBUS_Trials++ == Trials)
+      {
+        /* Generate Stop */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }
+    }
+    while (SMBUS_Trials < Trials);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_TIMEOUT;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  Handle SMBUS event interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint32_t tmpisrvalue = 0U;
+
+  /* Use a local variable to store the current ISR flags */
+  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+  tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+
+  /* SMBUS in mode Transmitter ---------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+  {
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+    /* Master mode selected */
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      SMBUS_Master_ISR(hsmbus);
+    }
+  }
+
+  /* SMBUS in mode Receiver ----------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+  {
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+    /* Master mode selected */
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      SMBUS_Master_ISR(hsmbus);
+    }
+  }
+
+  /* SMBUS in mode Listener Only --------------------------------------------------*/
+  if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+      && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+  {
+    if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+    {
+      SMBUS_Slave_ISR(hsmbus);
+    }
+  }
+}
+
+/**
+  * @brief  Handle SMBUS error interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  SMBUS_ITErrorHandler(hsmbus);
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read)
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SMBUS error callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMBUS handle state.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL state
+  */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Return SMBUS handle state */
+  return hsmbus->State;
+}
+
+/**
+* @brief  Return the SMBUS error code.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *              the configuration information for the specified SMBUS.
+* @retval SMBUS Error Code
+*/
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+  return hsmbus->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ *  @brief   Data transfers Private functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint16_t DevAddress;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Call the Error callback to inform upper layer */
+    HAL_SMBUS_ErrorCallback(hsmbus);
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  {
+    /* Check and treat errors if errors occurs during STOP process */
+    SMBUS_ITErrorHandler(hsmbus);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+      /* Disable the selected SMBUS peripheral */
+      __HAL_SMBUS_DISABLE(hsmbus);
+
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* REenable the selected SMBUS peripheral */
+      __HAL_SMBUS_ENABLE(hsmbus);
+
+      HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+    }
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      /* Store Last receive data if any */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+        if ((hsmbus->XferSize > 0U))
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+    }
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR */
+    hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+  {
+    if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+    {
+      DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+        hsmbus->XferSize = MAX_NBYTE_SIZE;
+      }
+      else
+      {
+        hsmbus->XferSize = hsmbus->XferCount;
+        SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+        /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+        if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+    }
+    else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+        }
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+        }
+      }
+    }
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+  {
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Specific use case for Quick command */
+      if (hsmbus->pBuffPtr == NULL)
+      {
+        /* Generate a Stop command */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+      }
+      /* Call TxCpltCallback() if no stop mode is set */
+      else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* No Generate Stop, to permit restart mode */
+        /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+        }
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint8_t TransferDirection = 0U;
+  uint16_t SlaveAddrCode = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Check that SMBUS transfer finished */
+    /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+    }
+    else
+    {
+      /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Set HAL State to "Idle" State, mean to LISTEN state */
+      /* So reset Slave Busy state */
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+      /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Error callback to inform upper layer */
+      HAL_SMBUS_ErrorCallback(hsmbus);
+    }
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+  {
+    TransferDirection = SMBUS_GET_DIR(hsmbus);
+    SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+
+    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+    /* Other ADDRInterrupt will be treat in next Listen usecase */
+    __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Call Slave Addr callback */
+    HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+  }
+  else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+  {
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      /* Read data from RXDR */
+      (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+      hsmbus->XferSize--;
+      hsmbus->XferCount--;
+
+      if (hsmbus->XferCount == 1U)
+      {
+        /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+        /* or only the last Byte of Transfer */
+        /* So reset the RELOAD bit mode */
+        hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+        SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      else if (hsmbus->XferCount == 0U)
+      {
+        /* Last Byte is received, disable Interrupt */
+        SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+        /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+        hsmbus->PreviousState = hsmbus->State;
+        hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        /* Call the Rx complete callback to inform upper layer of the end of receive process */
+        HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+      }
+      else
+      {
+        /* Set Reload for next Bytes */
+        SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+
+        /* Ack last Byte Read */
+        hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+      }
+    }
+    else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+      {
+        if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+        {
+          SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+          hsmbus->XferSize = MAX_NBYTE_SIZE;
+        }
+        else
+        {
+          hsmbus->XferSize = hsmbus->XferCount;
+          SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+          /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+          /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+          if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+          {
+            hsmbus->XferSize--;
+            hsmbus->XferCount--;
+          }
+        }
+      }
+    }
+  }
+  else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hsmbus->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+      hsmbus->XferCount--;
+      hsmbus->XferSize--;
+    }
+
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Last Byte is Transmitted */
+      /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+      HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+    }
+  }
+
+  /* Check if STOPF is set */
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+  {
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Store Last receive data if any */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+        if ((hsmbus->XferSize > 0U))
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable RX and TX Interrupts */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+      /* Disable ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+      /* Disable Address Acknowledge */
+      hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear ADDR flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+      hsmbus->XferOptions = 0U;
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+      HAL_SMBUS_ListenCpltCallback(hsmbus);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+  {
+    /* Enable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Enable ADDR, STOP interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of SMBUS interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
+  {
+    /* Disable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Disable TC, STOP, NACK, TXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOPI, NACKI */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Disable TC, STOP, NACK, RXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+        && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOPI, NACKI */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Enable ADDR, STOP interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+    if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SMBUS interrupts error handler.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
+  uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+
+  /* SMBUS Bus error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+  }
+
+  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+  }
+
+  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+  }
+
+  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+    /* Clear TIMEOUT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+  }
+
+  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+    /* Clear ALERT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+  }
+
+  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+  if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+    /* Clear PEC error flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+  }
+
+  /* Call the Error Callback in case of Error detected */
+  if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+  {
+    /* Do not Reset the HAL state in case of ALERT error */
+    if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+    {
+      if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+          || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+      {
+        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+        /* keep HAL_SMBUS_STATE_LISTEN if set */
+        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+      }
+    }
+
+    /* Call the Error callback to inform upper layer */
+    HAL_SMBUS_ErrorCallback(hsmbus);
+  }
+}
+
+/**
+  * @brief  Handle SMBUS Communication Timeout.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  Flag Specifies the SMBUS flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait until flag is set */
+  if (Status == RESET)
+  {
+    while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        {
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+        {
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hsmbus SMBUS handle.
+  * @param  DevAddress specifies the slave address to be programmed.
+  * @param  Size specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the SMBUS START condition generation.
+  *   This parameter can be one or a combination  of the following values:
+  *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+  *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+  *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+  * @param  Request New state of the SMBUS START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+  assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP  | I2C_CR2_PECBYTE)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to SMBUS_FIRST_FRAME                  */
+  if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition      */
+  /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+  /* it request implicitly to generate a restart condition             */
+  /* then generate a stop condition at the end of transfer             */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition               */
+  /* then generate a stop condition at the end of transfer               */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c
new file mode 100755
index 0000000..3487ad0
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tsc.c
@@ -0,0 +1,817 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_tsc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Touch Sensing Controller (TSC) peripheral:
+  *           + Initialization and DeInitialization
+  *           + Channel IOs, Shield IOs and Sampling IOs configuration
+  *           + Start and Stop an acquisition
+  *           + Read acquisition result
+  *           + Interrupts and flags management
+  *         
+  @verbatim
+================================================================================
+                       ##### TSC specific features #####
+================================================================================
+  [..]
+  (#) Proven and robust surface charge transfer acquisition principle
+    
+  (#) Supports up to 3 capacitive sensing channels per group
+    
+  (#) Capacitive sensing channels can be acquired in parallel offering a very good
+      response time
+      
+  (#) Spread spectrum feature to improve system robustness in noisy environments
+   
+  (#) Full hardware management of the charge transfer acquisition sequence
+   
+  (#) Programmable charge transfer frequency
+   
+  (#) Programmable sampling capacitor I/O pin
+   
+  (#) Programmable channel I/O pin
+   
+  (#) Programmable max count value to avoid long acquisition when a channel is faulty
+   
+  (#) Dedicated end of acquisition and max count error flags with interrupt capability
+   
+  (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+      components
+   
+  (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+   
+                          ##### How to use this driver #####
+================================================================================
+  [..]
+    (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
+
+    (#) GPIO pins configuration
+      (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
+      (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+           and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+           using HAL_GPIO_Init() function.
+      (++) Configure the alternate function on all the TSC pins using HAL_xxxx() function.
+
+    (#) Interrupts configuration
+      (++) Configure the NVIC (if the interrupt model is used) using HAL_xxx() function.
+
+    (#) TSC configuration
+      (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+  *** Acquisition sequence ***
+  ===================================
+  [..]
+    (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+    (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+        of the sampling capacitor and electrodes design.
+    (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+    (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+        If the synchronized mode is selected, the acquisition will start as soon as the signal
+        is received on the synchro pin.
+    (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+        HAL_TSC_GetState() function or using WFI instruction for example.
+    (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+    (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+      
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx)
+#include "stm32l0xx_hal.h"
+
+#ifdef HAL_TSC_MODULE_ENABLED
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TSC
+  * @brief HAL TSC module driver
+  * @{
+  */
+
+/** @addtogroup TSC_Private TSC Private
+  * @{
+  */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+static uint32_t TSC_extract_groups(uint32_t iomask);
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */
+/** @addtogroup TSC_Exported_Functions TSC Exported Functions
+  * @{
+  */ 
+
+/** @addtogroup HAL_TSC_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the TSC.
+      (+) De-initialize the TSC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TSC peripheral according to the specified parameters 
+  *         in the TSC_InitTypeDef structure.           
+  * @param  htsc: TSC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+{
+  /* Check TSC handle allocation */
+  if (htsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+  assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+  assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+  assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+  assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+  assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+  assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+  assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+  assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+  assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+  if(htsc->State == HAL_TSC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htsc->Lock = HAL_UNLOCKED;
+  }
+
+  /* Initialize the TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+
+  /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+  HAL_TSC_MspInit(htsc);
+
+  /*--------------------------------------------------------------------------*/  
+  /* Set TSC parameters */
+
+  /* Enable TSC */
+  htsc->Instance->CR = TSC_CR_TSCE;
+  
+  /* Set all functions */
+  htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+                         htsc->Init.CTPulseLowLength |
+                         (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
+                         htsc->Init.SpreadSpectrumPrescaler |
+                         htsc->Init.PulseGeneratorPrescaler |
+                         htsc->Init.MaxCountValue |
+                         htsc->Init.SynchroPinPolarity |
+                         htsc->Init.AcquisitionMode);
+
+  /* Spread spectrum */
+  if (htsc->Init.SpreadSpectrum == ENABLE)
+  {
+    htsc->Instance->CR |= TSC_CR_SSE;
+  }
+  
+  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+  htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+  /* Set channel and shield IOs */
+  htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+  
+  /* Set sampling IOs */
+  htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+  
+  /* Set the groups to be acquired */
+  htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+  
+  /* Clear interrupts */
+  htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
+  
+  /* Clear flags */
+  htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+  /*--------------------------------------------------------------------------*/
+  
+  /* Initialize the TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the TSC peripheral registers to their default reset values.
+  * @param  htsc: TSC handle  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+{
+  /* Check TSC handle allocation */
+  if (htsc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+   
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+ 
+  /* DeInit the low level hardware */
+  HAL_TSC_MspDeInit(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TSC MSP.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.  
+  * @retval None
+  */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_MspInit could be implemented in the user file.
+   */ 
+}
+
+/**
+  * @brief  DeInitializes the TSC MSP.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.  
+  * @retval None
+  */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_MspDeInit could be implemented in the user file.
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_TSC_Exported_Functions_Group2
+ *  @brief    IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### IO Operation functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start acquisition in polling mode.
+      (+) Start acquisition in interrupt mode.
+      (+) Stop conversion in polling mode.
+      (+) Stop conversion in interrupt mode.
+      (+) Get group acquisition status.
+      (+) Get group acquisition value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the acquisition.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+
+  /* Clear interrupts */
+  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+  
+  /* Launch the acquisition */
+  __HAL_TSC_START_ACQ(htsc);
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the interrupt and starts the acquisition
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_BUSY;
+  
+  /* Enable end of acquisition interrupt */
+  __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+  /* Enable max count error interrupt (optional) */
+  if (htsc->Init.MaxCountInterrupt == ENABLE)
+  {
+    __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+  }
+  else
+  {
+    __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+  }
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Set touch sensing IOs not acquired to the specified IODefaultMode */
+  if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+  
+  /* Launch the acquisition */
+  __HAL_TSC_START_ACQ(htsc);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the acquisition previously launched in polling mode
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Stop the acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+
+  /* Set touch sensing IOs in low power mode (output push-pull) */
+  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the acquisition previously launched in interrupt mode
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Stop the acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+  
+  /* Set touch sensing IOs in low power mode (output push-pull) */
+  __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  
+  /* Disable interrupts */
+  __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+  /* Clear flags */
+  __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+  
+  /* Change TSC state */
+  htsc->State = HAL_TSC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the acquisition status for a group
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  gx_index: Index of the group
+  * @retval Group status
+  */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+  /* Return the group status */ 
+  return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+  * @brief  Gets the acquisition measure for a group
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  gx_index: Index of the group
+  * @retval Acquisition measure
+  */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{       
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+  /* Return the group acquisition counter */ 
+  return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+  * @}
+  */
+  
+/** @addtogroup HAL_TSC_Exported_Functions_Group3
+ *  @brief    Peripheral Control functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure TSC IOs
+      (+) Discharge TSC IOs
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures TSC IOs
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  config: pointer to the configuration structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ 
+  /* Process locked */
+  __HAL_LOCK(htsc);
+
+  /* Stop acquisition */
+  __HAL_TSC_STOP_ACQ(htsc);
+
+  /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+  htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+  /* Set channel and shield IOs */
+  htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+  
+  /* Set sampling IOs */
+  htsc->Instance->IOSCR = config->SamplingIOs;
+  
+  /* Set groups to be acquired */
+  htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+    
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Discharge TSC IOs
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @param  choice: enable or disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
+{       
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  if (choice == ENABLE)
+  {
+    __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+  }
+  else
+  {
+    __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  /* Return the group acquisition counter */ 
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_TSC_Exported_Functions_Group4
+ *  @brief   State functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### State functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Get TSC state.
+      (+) Poll for acquisition completed.
+      (+) Handles TSC interrupt request.
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TSC state
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL state
+  */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+  
+  if (htsc->State == HAL_TSC_STATE_BUSY)
+  {
+    /* Check end of acquisition flag */
+    if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+    {
+      /* Check max count error flag */
+      if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+      {
+        /* Change TSC state */
+        htsc->State = HAL_TSC_STATE_ERROR;
+      }
+      else
+      {
+        /* Change TSC state */
+        htsc->State = HAL_TSC_STATE_READY;
+      }
+    }
+  }
+  
+  /* Return TSC state */
+  return htsc->State;
+}
+
+/**
+  * @brief  Start acquisition and wait until completion
+  * @note   There is no need of a timeout parameter as the max count error is already
+  *         managed by the TSC peripheral.
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(htsc);
+  
+  /* Check end of acquisition */
+  while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+  {
+    /* The timeout (max count error) is managed by the TSC peripheral itself. */
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(htsc);
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles TSC interrupt request  
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
+{
+  /* Check the parameters */
+  assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+  /* Check if the end of acquisition occured */
+  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+  {
+    /* Clear EOA flag */
+    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+  }
+  
+  /* Check if max count error occured */
+  if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+  {
+    /* Clear MCE flag */
+    __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+    /* Change TSC state */
+    htsc->State = HAL_TSC_STATE_ERROR;
+    /* Conversion completed callback */
+    HAL_TSC_ErrorCallback(htsc);
+  }
+  else
+  {
+    /* Change TSC state */
+    htsc->State = HAL_TSC_STATE_READY;
+    /* Conversion completed callback */
+    HAL_TSC_ConvCpltCallback(htsc);
+  }
+}
+
+/**
+  * @brief  Acquisition completed callback in non blocking mode 
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Error callback in non blocking mode
+  * @param  htsc: pointer to a TSC_HandleTypeDef structure that contains
+  *         the configuration information for the specified TSC.
+  * @retval None
+  */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TSC_ErrorCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup TSC_Private
+  * @{
+  */
+
+/**
+  * @brief  Utility function used to set the acquired groups mask
+  * @param  iomask: Channels IOs mask
+  * @retval Acquired groups mask
+  */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+  uint32_t groups = 0U;
+  uint32_t idx;
+  
+  for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
+  {
+    if ((iomask & ((uint32_t)0x0FU << (idx * 4U))) != RESET)
+    {
+      groups |= ((uint32_t)1U << idx);
+    }
+  }
+  
+  return groups;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+#endif /* HAL_TSC_MODULE_ENABLED */
+#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c
old mode 100644
new mode 100755
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c
new file mode 100755
index 0000000..944c1cb
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c
@@ -0,0 +1,2420 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_usart.c
+  * @author  MCD Application Team
+  * @brief   USART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+  *          Peripheral (USART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+      The USART HAL driver can be used as follows:
+
+      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+          (++) Enable the USARTx interface clock.
+          (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure these USART pins as alternate function pull-up.
+          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+            (++) USART interrupts handling:
+              -@@-   The specific USART interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+          flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
+
+      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+               by calling the customized HAL_USART_MspInit(&husart) API.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USART USART
+  * @brief HAL USART Synchronous module driver
+  * @{
+  */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+  * @{
+  */
+#define USART_DUMMY_DATA          ((uint16_t) 0xFFFFU)           /*!< USART transmitted dummy data                     */
+#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000U)             /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))    /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+                                              USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+  * @{
+  */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USART
+    in asynchronous and in synchronous modes.
+      (+) For the asynchronous mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) USART polarity
+        (++) USART phase
+        (++) USART LastBit
+        (++) Receiver/transmitter modes
+
+    [..]
+    The HAL_USART_Init() function follows the USART  synchronous configuration
+    procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible USART formats are listed in the 
+  following table.
+  
+    Table 1. USART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the USART mode according to the specified
+  *         parameters in the USART_InitTypeDef and initialize the associated handle.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  if(husart->State == HAL_USART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    husart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_USART_MspInit(husart);
+  }
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_USART_DISABLE(husart);
+
+  /* Set the Usart Communication parameters */
+  if (USART_SetConfig(husart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register
+  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+  husart->Instance->CR2 &= ~USART_CR2_LINEN;
+  husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+  /* Enable the Peripheral */
+  __HAL_USART_ENABLE(husart);
+
+  /* TEACK and/or REACK to check before moving husart->State to Ready */
+  return (USART_CheckIdleState(husart));
+}
+
+/**
+  * @brief  DeInitialize the USART peripheral.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if(husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  husart->Instance->CR1 = 0x0U;
+  husart->Instance->CR2 = 0x0U;
+  husart->Instance->CR3 = 0x0U;
+
+  /* DeInit the low level hardware */
+  HAL_USART_MspDeInit(husart);
+
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+  husart->State = HAL_USART_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the USART MSP.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the USART MSP.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+  * @brief    USART Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART synchronous
+    data transfers.
+
+    [..] The USART supports master mode only: it cannot receive or send data related to an input
+         clock (SCLK is always an output).
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (++) HAL_USART_Transmit()in simplex mode
+        (++) HAL_USART_Receive() in full duplex receive only
+        (++) HAL_USART_TransmitReceive() in full duplex mode
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (++) HAL_USART_Transmit_IT()in simplex mode
+        (++) HAL_USART_Receive_IT() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+        (++) HAL_USART_IRQHandler()
+
+    (#) No-Blocking mode API's  with DMA are :
+        (++) HAL_USART_Transmit_DMA()in simplex mode
+        (++) HAL_USART_Receive_DMA() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+        (++) HAL_USART_DMAPause()
+        (++) HAL_USART_DMAResume()
+        (++) HAL_USART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (++) HAL_USART_TxCpltCallback()
+        (++) HAL_USART_RxCpltCallback()
+        (++) HAL_USART_TxHalfCpltCallback()
+        (++) HAL_USART_RxHalfCpltCallback()
+        (++) HAL_USART_ErrorCallback()
+        (++) HAL_USART_TxRxCpltCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_USART_Abort()
+        (+) HAL_USART_Abort_IT()
+
+    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+        (+) HAL_USART_AbortCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Simplex send an amount of data in blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData Pointer to data buffer.
+  * @param  Size Amount of data to be sent.
+  * @param  Timeout Timeout duration.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pTxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* Check the remaining data to be sent */
+    while(husart->TxXferCount > 0U)
+    {
+      husart->TxXferCount--;
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+        pTxData += 2U;
+      }
+      else
+      {
+        husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
+      }
+    }
+
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note  To receive synchronous data, dummy data are simultaneously transmitted.
+  * @param husart USART handle.
+  * @param pRxData Pointer to data buffer.
+  * @param Size Amount of data to be received.
+  * @param Timeout Timeout duration.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pRxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* as long as data have to be received */
+    while(husart->RxXferCount > 0U)
+    {
+      husart->RxXferCount--;
+
+      /* Wait until TXE flag is set to send dummy byte in order to generate the
+      * clock for the slave to send data.
+       * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+       * can be written for all the cases. */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
+
+      /* Wait for RXNE Flag */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pRxData ;
+        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+        pRxData +=2U;
+      }
+      else
+      {
+        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of Rx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send and Receive an amount of data in blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.
+  * @param  Size amount of data to be sent (same amount to be received).
+  * @param  Timeout Timeout duration.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint16_t* tmp;
+  uint16_t uhMask;
+  uint32_t tickstart = 0;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* Check the remain data to be sent */
+    while(husart->TxXferCount > 0U)
+    {
+      husart->TxXferCount--;
+      husart->RxXferCount--;
+
+      /* Wait until TXE flag is set to send data */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pTxData;
+        husart->Instance->TDR = (*tmp & uhMask);
+        pTxData += 2U;
+      }
+      else
+      {
+        husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+      }
+
+      /* Wait for RXNE Flag */
+      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) pRxData ;
+        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+        pRxData +=2U;
+      }
+      else
+      {
+        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+      }
+    }
+
+    /* At end of TxRx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL ) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pTxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+    are not managed by the USART Transmit Process to avoid the overrun interrupt
+    when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+    to benefit for the frame error and noise interrupts the usart mode should be
+    configured only for transmit "USART_MODE_TX" */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Transmit Data Register Empty Interrupt */
+    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL ) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pRxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error and Data Register not empty Interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Send dummy byte in order to generate the clock for the Slave to send the next data */
+    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    {
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
+    }
+    else
+    {
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send and Receive an amount of data in interrupt mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.                         
+  * @param  Size amount of data to be sent (same amount to be received).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
+{
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+    /* Enable the USART Transmit Data Register Empty Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL ) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pTxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Set the USART DMA transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART transmit DMA channel */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   When the USART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.  
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  /* Check that a Rx process is not already ongoing */
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pRxData == NULL ) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if((((uint32_t)pRxData)&1) != 0)
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pRxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA channel */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA channel: the transmit channel is used in order
+       to generate in the non-blocking mode the clock to the slave device,
+       this mode isn't a simplex receive mode but a full-duplex receive mode */
+    tmp = (uint32_t*)&pRxData;
+    /* Set the USART DMA Tx Complete and Error callback to Null */
+    husart->hdmatx->XferErrorCallback = NULL;
+    husart->hdmatx->XferHalfCpltCallback = NULL;
+    husart->hdmatx->XferCpltCallback = NULL;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer.
+  * @param  pRxData pointer to RX data buffer.
+  * @param  Size amount of data to be received/sent.
+  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
+  *         (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
+  *         use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  if(husart->State == HAL_USART_STATE_READY)
+  {
+    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter 
+       should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be 
+       handled through a u16 cast. */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      if(((((uint32_t)pTxData)&1) != 0) || ((((uint32_t)pRxData)&1) != 0))
+      {
+        return  HAL_ERROR;
+      }
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Set the USART DMA Rx transfer complete callback */
+    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+    /* Set the USART DMA Tx transfer complete callback */
+    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+    /* Set the USART DMA Half transfer complete callback */
+    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+    /* Set the USART DMA Tx transfer error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Set the USART DMA Rx transfer error callback */
+    husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+    /* Enable the USART receive DMA channel */
+    tmp = (uint32_t*)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+    /* Enable the USART transmit DMA channel */
+    tmp = (uint32_t*)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+    /* Clear the TC flag in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Pause the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
+      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
+  {
+    /* Disable the USART DMA Tx request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+  else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+           (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+  {
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      /* Disable the USART DMA Tx request */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+    }
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Disable the USART DMA Rx request */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Enable the USART DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+  else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+           (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the USART DMA Rx request  before the DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Enable the USART DMA Tx request */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: 
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of 
+     the stream and the corresponding call back is executed. */
+
+  /* Disable the USART Tx/Rx DMA requests */
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+  /* Abort the USART DMA tx channel */
+  if(husart->hdmatx != NULL)
+  {
+    HAL_DMA_Abort(husart->hdmatx);
+  }
+  /* Abort the USART DMA rx channel */
+  if(husart->hdmarx != NULL)
+  {
+    HAL_DMA_Abort(husart->hdmarx);
+  }
+
+  USART_EndTransfer(husart);
+  husart->State = HAL_USART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the USART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      husart->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmatx);
+    }
+  }
+
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(husart->hdmarx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      husart->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  husart->TxXferCount = 0; 
+  husart->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(husart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+    }
+    else
+    {
+      husart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(husart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+    }
+    else
+    {
+      husart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the USART DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at USART level */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(husart->hdmatx != NULL)
+    {
+      /* USART Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+      {
+        husart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(husart->hdmarx != NULL)
+    {
+      /* USART Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+      {
+        husart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    husart->TxXferCount = 0; 
+    husart->RxXferCount = 0;
+
+    /* Reset errorCode */
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+    /* Restore husart->State to Ready */
+    husart->State  = HAL_USART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_USART_AbortCpltCallback(husart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle USART interrupt request.
+  * @param  husart USART handle.
+  * @retval None
+  */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+  uint32_t isrflags   = READ_REG(husart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(husart->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == RESET)
+  {
+    /* USART in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      if(husart->State == HAL_USART_STATE_BUSY_RX)
+      {
+        USART_Receive_IT(husart);
+      }
+      else
+      {
+        USART_TransmitReceive_IT(husart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  cr3its = READ_REG(husart->Instance->CR3);
+  if(   (errorflags != RESET)
+     && (   ((cr3its & USART_CR3_EIE) != RESET)
+         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+  {
+    /* USART parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_PE;
+    }
+
+    /* USART frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_FE;
+    }
+
+    /* USART noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_NE;
+    }
+
+    /* USART Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_ORE;
+    }
+
+    /* Call USART Error Call back function if need be --------------------------*/
+    if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+    {
+      /* USART in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        if(husart->State == HAL_USART_STATE_BUSY_RX)
+        {
+          USART_Receive_IT(husart);
+        }
+        else
+        {
+          USART_TransmitReceive_IT(husart);
+        }
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
+          (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the USART state ready to be able to start again the process,
+           Disable Interrupts, and disable DMA requests, if ongoing */
+        USART_EndTransfer(husart);
+
+        /* Disable the USART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+          /* Abort the USART DMA Tx channel */
+          if(husart->hdmatx != NULL)
+          {
+            /* Set the USART Tx DMA Abort callback to NULL : no callback
+               executed at end of DMA abort procedure */
+            husart->hdmatx->XferAbortCallback = NULL;
+            
+            /* Abort DMA TX */
+            HAL_DMA_Abort_IT(husart->hdmatx);
+          }
+
+          /* Abort the USART DMA Rx channel */
+          if(husart->hdmarx != NULL)
+          {
+            /* Set the USART Rx DMA Abort callback : 
+               will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+              husart->hdmarx->XferAbortCallback(husart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_USART_ErrorCallback(husart);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_USART_ErrorCallback(husart);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_USART_ErrorCallback(husart);
+        husart->ErrorCode = HAL_USART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+
+  /* USART in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      USART_Transmit_IT(husart);
+    }
+    else
+    {
+      USART_TransmitReceive_IT(husart);
+    }
+    return;
+  }
+
+  /* USART in mode Transmitter (transmission end) -----------------------------*/
+  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    USART_EndTransmit_IT(husart);
+    return;
+  }
+
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxRxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief USART error callback.
+  * @param husart: USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  USART Abort Complete callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ *  @brief   USART Peripheral State and Error functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the USART handle state
+      (+) Return the USART handle error code
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief Return the USART handle state.
+  * @param husart : pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle state
+  */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+  return husart->State;
+}
+
+/**
+  * @brief Return the USART error code.
+  * @param husart : pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle Error Code
+  */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+  return husart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+  * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  DMA USART transmit process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    husart->TxXferCount = 0U;
+
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+         in the USART CR3 register */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+    }
+  }
+  /* DMA Circular mode */
+  else
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+    HAL_USART_TxCpltCallback(husart);
+   }
+ }
+}
+
+/**
+  * @brief  DMA USART transmit process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+  * @brief  DMA USART receive process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+  {
+    husart->RxXferCount = 0;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+       in USART CR3 register */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    /* similarly, disable the DMA TX transfer that was started to provide the
+       clock to the slave device */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+      HAL_USART_RxCpltCallback(husart);
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+      HAL_USART_TxRxCpltCallback(husart);
+    }
+    husart->State= HAL_USART_STATE_READY;
+  }
+  /* DMA circular mode */
+  else
+  {
+    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+      HAL_USART_RxCpltCallback(husart);
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+      HAL_USART_TxRxCpltCallback(husart);
+    }
+  }    
+
+}
+
+/**
+  * @brief  DMA USART receive process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+  * @brief DMA USART communication error callback.
+  * @param  hdma: DMA handle.
+  * @retval None
+  */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+  husart->RxXferCount = 0;
+  husart->TxXferCount = 0;
+  USART_EndTransfer(husart);
+
+  husart->ErrorCode |= HAL_USART_ERROR_DMA;
+  husart->State= HAL_USART_STATE_READY;
+
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+  husart->RxXferCount = 0;
+  husart->TxXferCount = 0;
+
+  HAL_USART_ErrorCallback(husart);
+}
+
+/**
+  * @brief  DMA USART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+  
+  husart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(husart->hdmarx != NULL)
+  {
+    if(husart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0;
+  husart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+  * @brief  DMA USART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+  
+  husart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(husart->hdmatx != NULL)
+  {
+    if(husart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0;
+  husart->RxXferCount = 0;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+  * @brief  Handle USART Communication Timeout.
+  * @param  husart USART handle.
+  * @param  Flag Specifies the USART flag to check.
+  * @param  Status the Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+        husart->State= HAL_USART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(husart);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure the USART peripheral.
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpreg                      = 0x0U;
+  USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret                = HAL_OK;
+  uint16_t brrtemp                     = 0x0000U;
+  uint16_t usartdiv                    = 0x0000U;
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+  assert_param(IS_USART_PARITY(husart->Init.Parity));
+  assert_param(IS_USART_MODE(husart->Init.Mode));
+
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+   /* Clear M, PCE, PS, TE and RE bits and configure
+   *  the USART Word Length, Parity and Mode:
+   *  set the M bits according to husart->Init.WordLength value
+   *  set PCE and PS bits according to husart->Init.Parity value
+   *  set TE and RE bits according to husart->Init.Mode value 
+   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8)  */
+  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*---------------------------- USART CR2 Configuration ---------------------*/
+  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
+   * set CPOL bit according to husart->Init.CLKPolarity value
+   * set CPHA bit according to husart->Init.CLKPhase value
+   * set LBCL bit according to husart->Init.CLKLastBit value
+   * set STOP[13:12] bits according to husart->Init.StopBits value */
+  tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+  tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* no CR3 register configuration                                            */
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */ 
+  USART_GETCLOCKSOURCE(husart, clocksource);
+  switch (clocksource)
+  {
+    case USART_CLOCKSOURCE_PCLK1:
+      usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_PCLK2:
+      usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_HSI:
+      usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_SYSCLK:
+      usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_LSE:
+      usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
+      break;
+    case USART_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+  
+  brrtemp = usartdiv & 0xFFF0U;
+  brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+  husart->Instance->BRR = brrtemp;
+
+  return ret;
+}
+
+/**
+  * @brief Check the USART Idle State.
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the USART ErrorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the USART state*/
+  husart->State= HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp = 0U;
+
+  /* Check that a Tx process is ongoing */
+  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    if(husart->TxXferCount == 0U)
+    {
+      /* Disable the USART Transmit data register empty interrupt */
+      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        tmp = (uint16_t*) husart->pTxBuffPtr;
+        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+        husart->pTxBuffPtr += 2U;
+      }
+      else
+      {
+        husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
+      }
+
+      husart->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Wraps up transmission in non-blocking mode.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+  /* Disable the USART Transmit Complete Interrupt */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+  /* Tx process is ended, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+
+  HAL_USART_TxCpltCallback(husart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @param  husart USART handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+  uint16_t uhMask = husart->Mask;
+
+  if(husart->State == HAL_USART_STATE_BUSY_RX)
+  {
+
+    if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      tmp = (uint16_t*) husart->pRxBuffPtr;
+      *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+      husart->pRxBuffPtr += 2U;
+    }
+    else
+    {
+      *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+    }
+    /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+    husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
+
+    if(--husart->RxXferCount == 0U)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore husart->State to Ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      HAL_USART_RxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_TransmitReceive_IT().
+  * @param husart: USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+  uint16_t* tmp;
+  uint16_t uhMask = husart->Mask;
+
+  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  {
+
+    if(husart->TxXferCount != 0x00U)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+      {
+        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+        {
+          tmp = (uint16_t*) husart->pTxBuffPtr;
+          husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
+          husart->pTxBuffPtr += 2U;
+        }
+        else
+        {
+          husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+        }
+        husart->TxXferCount--;
+
+        /* Check the latest data transmitted */
+        if(husart->TxXferCount == 0U)
+        {
+           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+        }
+      }
+    }
+
+    if(husart->RxXferCount != 0x00U)
+    {
+      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+      {
+        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+        {
+          tmp = (uint16_t*) husart->pRxBuffPtr;
+          *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+          husart->pRxBuffPtr += 2U;
+        }
+        else
+        {
+          *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+        }
+        husart->RxXferCount--;
+      }
+    }
+
+    /* Check the latest data received */
+    if(husart->RxXferCount == 0U)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore husart->State to Ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      HAL_USART_TxRxCpltCallback(husart);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c
new file mode 100755
index 0000000..77d6ad4
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_wwdg.c
@@ -0,0 +1,320 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_wwdg.c
+  * @author  MCD Application Team
+  * @brief   WWDG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Window Watchdog (WWDG) peripheral:
+  *           + Initialization and Configuration function
+  *           + IO operation functions
+  @verbatim
+  ==============================================================================
+                      ##### WWDG specific features #####
+  ==============================================================================
+  [..]
+    Once enabled the WWDG generates a system reset on expiry of a programmed
+    time period, unless the program refreshes the counter (T[6;0] downcounter)
+    before reaching 0x3F value (i.e. a reset is generated when the counter
+    value rolls over from 0x40 to 0x3F).
+
+    (+) An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This
+        implies that the counter must be refreshed in a limited window.
+
+    (+) Once enabled the WWDG cannot be disabled except by a system reset.
+
+    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has 
+        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
+
+    (+) The WWDG downcounter input clock is derived from the APB clock divided
+        by a programmable prescaler.
+
+    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
+
+    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
+        where T[5;0] are the lowest 6 bits of downcounter.
+
+    (+) WWDG Counter refresh is allowed between the following limits :
+        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
+        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
+
+    (+) Min-max timeout value @32 MHz(PCLK1): ~128.0 us / ~65.54 ms
+
+    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety 
+        operations or data logging must be performed before the actual reset is
+        generated. When the downcounter reaches the value 0x40, an EWI interrupt
+        is generated and the corresponding interrupt service routine (ISR) can 
+        be used to trigger specific actions (such as communications or data 
+        logging), before resetting the device.
+        In some applications, the EWI interrupt can be used to manage a software
+        system check and/or system recovery/graceful degradation, without 
+        generating a WWDG reset. In this case, the corresponding interrupt 
+        service routine (ISR) should reload the WWDG counter to avoid the WWDG 
+        reset, then trigger the required actions.
+        Note:When the EWI interrupt cannot be served, e.g. due to a system lock 
+        in a higher priority task, the WWDG reset will eventually be generated.
+
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the WWDG counter either continues to work normally or stops, depending 
+        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+
+    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup 
+        Interrupt mode using using HAL_WWDG_Init() function.
+        This enables WWDG peripheral and the downcounter starts downcounting 
+        from given counter value.
+        Init function can be called again to modify all watchdog parameters, 
+        however if EWI mode has been set once, it can't be clear until next 
+        reset.
+
+    (+) The application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset using
+        HAL_WWDG_Refresh() function. This operation must occur only when
+        the counter is lower than the window value already programmed.
+
+    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when 
+        the counter reaches 0x40. User can add his own code in weak function 
+        HAL_WWDG_EarlyWakeupCallback().
+
+     *** WWDG HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in WWDG HAL driver.
+
+      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+  * @brief WWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+          ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]  
+    This section provides functions allowing to:
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check the WWDG handle allocation */
+  if(hwwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+  /* Set WWDG Prescaler and Window */
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions 
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================  
+  [..]
+    This section provides functions allowing to:
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Write to WWDG CR the WWDG Counter value to refresh with */
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with 
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check if Early Wakeup Interrupt is enable */
+  if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+  {
+    /* Check if WWDG Early Wakeup Interrupt occurred */
+    if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+    {
+      /* Clear the WWDG Early Wakeup flag */
+      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+      /* Early Wakeup callback */ 
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
+    }
+  }
+}
+
+
+/**
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c
new file mode 100755
index 0000000..966a5f2
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_adc.c
@@ -0,0 +1,658 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_adc.c
+  * @author  MCD Application Team
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_adc.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          APB prescaler 16, ADC prescaler 4.                                */
+/*        - ADC clock from asynchronous clock (HSI) with prescaler 1,         */
+/*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
+/*          CPU clock frequency max 32MHz, HSI frequency 16MHz: ratio 2.      */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          ((uint32_t) 512U * 16U * 4U)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
+  (   ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
+  )
+
+#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)                         \
+  (   ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH)                   \
+   || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW)                    \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_CLOCK(__CLOCK__)                                             \
+  (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC)                                      \
+  )
+
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
+  (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
+   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF)                              \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF)                     \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM21_CH2)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM22_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
+  (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  
+  /* Force reset of ADC clock (core clock) */
+  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
+  
+  /* Release reset of ADC clock (core clock) */
+  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
+  
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+  
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()":                                           */
+  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*    - Set ADC clock (conversion clock)                                  */
+    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+  /* Set ADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+  
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+  
+  __IO uint32_t timeout_cpu_cycles = 0U;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  
+  /* Disable ADC instance if not already disabled.                            */
+  if(LL_ADC_IsEnabled(ADCx) == 1U)
+  {
+    /* Set ADC group regular trigger source to SW start to ensure to not      */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+    
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
+    {
+      if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+    
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
+    {
+      if(timeout_cpu_cycles-- == 0U)
+      {
+        /* Time-out error */
+        status = ERROR;
+      }
+    }
+    
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+    
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
+    {
+      if(timeout_cpu_cycles-- == 0U)
+      {
+        /* Time-out error */
+        status = ERROR;
+      }
+    }
+  }
+  
+  /* Check whether ADC state is compliant with expected state */
+  if(READ_BIT(ADCx->CR,
+              (  ADC_CR_ADSTP | ADC_CR_ADSTART
+               | ADC_CR_ADDIS | ADC_CR_ADEN   )
+             )
+     == 0U)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (  LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_AWD1 )
+             );
+    
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (  LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_AWD1 )
+           );
+    
+    /* Reset register CR */
+    /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
+    /* "read-set": no direct reset applicable.                                */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
+    
+    /* Reset register CFGR1 */
+    CLEAR_BIT(ADCx->CFGR1,
+              (  ADC_CFGR1_AWDCH   | ADC_CFGR1_AWDEN  | ADC_CFGR1_AWDSGL  | ADC_CFGR1_DISCEN
+               | ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD
+               | ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES
+               | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN                     )
+             );
+    
+    /* Reset register CFGR2 */
+    /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
+    /*       already done above.                                              */
+    CLEAR_BIT(ADCx->CFGR2,
+              (  ADC_CFGR2_CKMODE
+               | ADC_CFGR2_TOVS   | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR
+               | ADC_CFGR2_OVSE   | ADC_CFGR2_CKMODE                )
+             );
+    
+    /* Reset register SMPR */
+    CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
+
+    /* Reset register TR */
+    MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
+    
+    /* Reset register CHSELR */
+#if defined(ADC_CCR_VLCDEN)
+    CLEAR_BIT(ADCx->CHSELR,
+              (  ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+               | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+               | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
+               | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
+               | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0 )
+             );
+#else
+    CLEAR_BIT(ADCx->CHSELR,
+              (  ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17
+               | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+               | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
+               | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
+               | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0 )
+             );
+#endif
+    
+    /* Reset register DR */
+    /* bits in access mode read only, no direct reset applicable */
+    
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
+    
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 serie, if several ADC instances are available   */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular sequencer:
+  *            map channel on rank corresponding to channel number.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  
+  assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
+  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+  assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if(LL_ADC_IsEnabled(ADCx) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_RES
+               | ADC_CFGR1_ALIGN
+               | ADC_CFGR1_WAIT
+               | ADC_CFGR1_AUTOFF
+              ,
+                 ADC_InitStruct->Resolution
+               | ADC_InitStruct->DataAlignment
+               | ADC_InitStruct->LowPowerMode
+              );
+    
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+  /* Set ADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  ADC_InitStruct->Clock         = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+  
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular sequencer:
+  *            map channel on rank corresponding to channel number.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if(LL_ADC_IsEnabled(ADCx) == 0U)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
+    /*       setting of trigger source to SW start.                           */
+    MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_EXTSEL
+               | ADC_CFGR1_EXTEN
+               | ADC_CFGR1_DISCEN
+               | ADC_CFGR1_CONT
+               | ADC_CFGR1_DMAEN
+               | ADC_CFGR1_DMACFG
+               | ADC_CFGR1_OVRMOD
+              ,
+                 ADC_REG_InitStruct->TriggerSource
+               | ADC_REG_InitStruct->SequencerDiscont
+               | ADC_REG_InitStruct->ContinuousMode
+               | ADC_REG_InitStruct->DMATransfer
+               | ADC_REG_InitStruct->Overrun
+              );
+
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+  /* Set ADC_REG_InitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
+  /*       setting of trigger source to SW start.                             */
+  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
+  ADC_REG_InitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c
new file mode 100755
index 0000000..4777f01
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_comp.c
@@ -0,0 +1,323 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_comp.c
+  * @author  MCD Application Team
+  * @brief   COMP LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_comp.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of COMP hierarchical scope:          */
+/* COMP instance.                                                             */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
+  (   ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
+   || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER)                    \
+  )
+
+#if defined (STM32L011xx) || defined (STM32L021xx)
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+       (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1                              \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO6)                         \
+      )                                                                        \
+  )
+#else
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+       (__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1                              \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO4)                         \
+       || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO5)                         \
+      )                                                                        \
+  )
+#endif
+
+/* Note: On this STM32 serie, comparator input minus parameters are           */
+/*       the different depending on COMP instances.                           */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (((__COMP_INSTANCE__) == COMP1)                                              \
+    ? (                                                                        \
+          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                  \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                  \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                       \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+          ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                   \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                  \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                  \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                       \
+       || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                       \
+      )                                                                        \
+  )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
+  (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
+   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected COMP instance
+  *         to their default reset values.
+  * @note   If comparator is locked, de-initialization by software is
+  *         not possible.
+  *         The only way to unlock the comparator is a device hardware reset.
+  * @param  COMPx COMP instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are de-initialized
+  *          - ERROR: COMP registers are not de-initialized
+  */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+  
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       COMP instance must not be locked.                                  */
+  if(LL_COMP_IsLocked(COMPx) == 0U)
+  {
+    if(COMPx == COMP1)
+    {
+      CLEAR_BIT(COMPx->CSR,
+                (  COMP_CSR_COMP1EN
+                 | COMP_CSR_COMP1INNSEL
+                 | COMP_CSR_COMP1WM
+                 | COMP_CSR_COMP1LPTIM1IN1
+                 | COMP_CSR_COMP1POLARITY
+                 | COMP_CSR_COMP1LOCK
+                ) 
+               );
+    }
+    else
+    {
+      CLEAR_BIT(COMPx->CSR,
+                (  COMP_CSR_COMP2EN
+                 | COMP_CSR_COMP2SPEED
+                 | COMP_CSR_COMP2INNSEL
+                 | COMP_CSR_COMP2INPSEL
+                 | COMP_CSR_COMP2LPTIM1IN2
+                 | COMP_CSR_COMP2LPTIM1IN1
+                 | COMP_CSR_COMP2POLARITY
+                 | COMP_CSR_COMP2LOCK
+                ) 
+               );
+    }
+
+  }
+  else
+  {
+    /* Comparator instance is locked: de-initialization by software is         */
+    /* not possible.                                                           */
+    /* The only way to unlock the comparator is a device hardware reset.       */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of COMP instance.
+  * @note   This function configures features of the selected COMP instance.
+  *         Some features are also available at scope COMP common instance
+  *         (common to several COMP instances).
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  COMPx COMP instance
+  * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are initialized
+  *          - ERROR: COMP registers are not initialized
+  */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+  if(COMPx == COMP2)
+  {
+    assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+    assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+  }
+  assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+  assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+  
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       COMP instance must not be locked.                                  */
+  if(LL_COMP_IsLocked(COMPx) == 0U)
+  {
+    /* Configuration of comparator instance :                                 */
+    /*  - PowerMode                                                           */
+    /*  - InputPlus                                                           */
+    /*  - InputMinus                                                          */
+    /*  - OutputPolarity                                                      */
+    /* Note: Connection switch is applicable only to COMP instance COMP1,     */
+    /*       therefore is COMP2 is selected the equivalent bit is             */
+    /*       kept unmodified.                                                 */
+    if(COMPx == COMP1)
+    {
+      MODIFY_REG(COMPx->CSR,
+                 ( COMP_CSR_COMP1INNSEL
+                  | COMP_CSR_COMP1POLARITY
+                 ) 
+                ,
+                 (  COMP_InitStruct->InputMinus
+                  | COMP_InitStruct->OutputPolarity
+                 ) 
+                );
+    }
+    else
+    {
+      MODIFY_REG(COMPx->CSR,
+                 (  COMP_CSR_COMP2SPEED       
+                  | COMP_CSR_COMP2INPSEL      
+                  | COMP_CSR_COMP2INNSEL      
+                  | COMP_CSR_COMP2POLARITY
+                 ) 
+                ,
+                 (  COMP_InitStruct->PowerMode
+                  | COMP_InitStruct->InputPlus
+                  | COMP_InitStruct->InputMinus
+                  | COMP_InitStruct->OutputPolarity
+                 ) 
+                );
+    }
+
+  }
+  else
+  {
+    /* Initialization error: COMP instance is locked.                         */
+    status = ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+  * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  /* Set COMP_InitStruct fields to default values */
+  COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_MEDIUMSPEED;
+  COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
+  COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
+  COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c
new file mode 100755
index 0000000..3baa92f
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_crc.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize CRC registers (Registers restored to their default values).
+  * @param  CRCx CRC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRC registers are de-initialized
+  *          - ERROR: CRC registers are not de-initialized
+  */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+  if (CRCx == CRC)
+  {
+    /* Force CRC reset */
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+    /* Release CRC reset */
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (CRC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c
new file mode 100755
index 0000000..0a9f9b9
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crs.c
@@ -0,0 +1,102 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   CRS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_crs.h"
+#include "stm32l0xx_ll_bus.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRS_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes CRS peripheral registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRS registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_CRS_DeInit(void)
+{
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
+
+  return  SUCCESS;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+  
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c
new file mode 100755
index 0000000..9e75d91
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dac.c
@@ -0,0 +1,282 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_dac.c
+  * @author  MCD Application Team
+  * @brief   DAC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_dac.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (DAC1)
+
+/** @addtogroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+  * @{
+  */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
+  (                                                                            \
+      ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
+   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
+  )
+#else
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
+  (                                                                            \
+   ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                     \
+  )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
+  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_CH3)                       \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM21_TRGO)                     \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
+  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
+  (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
+   || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
+  )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
+  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
+   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected DAC instance
+  *         to their default reset values.
+  * @param  DACx DAC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+  
+  /* Force reset of DAC clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+  
+  /* Release reset of DAC clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+  
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of DAC instance.
+  * @note   The setting of these parameters by function @ref LL_DAC_Init()
+  *         is conditioned to DAC state:
+  *         DAC instance must be disabled.
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *         
+  *         (1) On this STM32 serie, parameter not available on all devices.
+  *             Refer to device datasheet for channels availability.
+  * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are initialized
+  *          - ERROR: DAC registers are not initialized
+  */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+  assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+  assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+  assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+  assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+  if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+  {
+    assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+  }
+  
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       DAC instance must be disabled.                                     */
+  if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+  {
+    /* Configuration of DAC channel:                                          */
+    /*  - TriggerSource                                                       */
+    /*  - WaveAutoGeneration                                                  */
+    /*  - OutputBuffer                                                        */
+    if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+    {
+      MODIFY_REG(DACx->CR,
+                 (  DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                  | DAC_CR_MAMP1
+                  | DAC_CR_BOFF1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                ,
+                 (  DAC_InitStruct->TriggerSource
+                  | DAC_InitStruct->WaveAutoGeneration
+                  | DAC_InitStruct->WaveAutoGenerationConfig
+                  | DAC_InitStruct->OutputBuffer
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+    else
+    {
+      MODIFY_REG(DACx->CR,
+                 (  DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                  | DAC_CR_BOFF1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                ,
+                 (  DAC_InitStruct->TriggerSource
+                  | LL_DAC_WAVE_AUTO_GENERATION_NONE
+                  | DAC_InitStruct->OutputBuffer
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+  }
+  else
+  {
+    /* Initialization error: DAC instance is not disabled.                    */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+  * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  /* Set DAC_InitStruct fields to default values */
+  DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
+  DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+  /* Note: Parameter discarded if wave auto generation is disabled,           */
+  /*       set anyway to its default value.                                   */
+  DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+  DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c
new file mode 100755
index 0000000..77742c9
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c
@@ -0,0 +1,395 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_dma.h"
+#include "stm32l0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
+
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_1)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_2)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_3)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_4)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_5)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_6)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_7)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_8)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_9)  || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_10) || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_11) || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_12) || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_13) || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_14) || \
+                                                 ((__VALUE__) == LL_DMA_REQUEST_15))
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA1_Channel6) && defined (DMA1_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#elif defined (DMA1_Channel6)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_6))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                            ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif /* DMA1_Channel6 && DMA1_Channel7 */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6 (*)
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *         @arg @ref LL_DMA_CHANNEL_ALL
+  *
+  *         (*) value not defined in all devices
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
+
+  if (Channel == LL_DMA_CHANNEL_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+#if defined(DMA2)
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+#endif
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+    /* Disable the selected DMAx_Channely */
+    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+    /* Reset DMAx_Channely control register */
+    LL_DMA_WriteReg(tmp, CCR, 0U);
+
+    /* Reset DMAx_Channely remaining bytes register */
+    LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+    /* Reset DMAx_Channely peripheral address register */
+    LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+    /* Reset DMAx_Channely memory address register */
+    LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+    /* Reset Request register field for DMAx Channel */
+    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
+
+    if (Channel == LL_DMA_CHANNEL_1)
+    {
+      /* Reset interrupt pending bits for DMAx Channel1 */
+      LL_DMA_ClearFlag_GI1(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_2)
+    {
+      /* Reset interrupt pending bits for DMAx Channel2 */
+      LL_DMA_ClearFlag_GI2(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_3)
+    {
+      /* Reset interrupt pending bits for DMAx Channel3 */
+      LL_DMA_ClearFlag_GI3(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_4)
+    {
+      /* Reset interrupt pending bits for DMAx Channel4 */
+      LL_DMA_ClearFlag_GI4(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_5)
+    {
+      /* Reset interrupt pending bits for DMAx Channel5 */
+      LL_DMA_ClearFlag_GI5(DMAx);
+    }
+
+#if defined(DMA1_Channel6)
+    else if (Channel == LL_DMA_CHANNEL_6)
+    {
+      /* Reset interrupt pending bits for DMAx Channel6 */
+      LL_DMA_ClearFlag_GI6(DMAx);
+    }
+#endif
+#if defined(DMA1_Channel7)
+    else if (Channel == LL_DMA_CHANNEL_7)
+    {
+      /* Reset interrupt pending bits for DMAx Channel7 */
+      LL_DMA_ClearFlag_GI7(DMAx);
+    }
+#endif
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6 (*)
+  *         @arg @ref LL_DMA_CHANNEL_7 (*)
+  *
+  *         (*) value not defined in all devices
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+  /*---------------------------- DMAx CCR Configuration ------------------------
+   * Configure DMAx_Channely: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+   * - Mode:           DMA_CCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+   * - Priority:               DMA_CCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
+                        DMA_InitStruct->Mode                   | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
+                        DMA_InitStruct->Priority);
+
+  /*-------------------------- DMAx CMAR Configuration -------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx CPAR Configuration -------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx CNDTR Configuration -----------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData: DMA_CNDTR_NDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMAx CSELR Configuration -----------------------
+   * Configure the peripheral base address with parameter :
+   * - PeriphRequest: DMA_CSELR[31:0] bits
+   */
+  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
+  DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c
new file mode 100755
index 0000000..c326279
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c
@@ -0,0 +1,230 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are de-initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_DeInit(void)
+{
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR,   0x3F840000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(PR,    0x007BFFFFU);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are initialized
+  *          - ERROR: not applicable
+  */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        default:
+          status = ERROR;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+  }
+  /* DISABLE LineCommand */
+  else
+  {
+    /* De-configure EXTI Lines in range from 0 to 31 */
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c
new file mode 100755
index 0000000..1819911
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c
@@ -0,0 +1,281 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_gpio.h"
+#include "stm32l0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOH)
+  else if (GPIOx == GPIOH)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOH);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOH);
+  }
+#endif /* GPIOH */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos     = 0x00000000U;
+  uint32_t currentpin = 0x00000000U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  /* pinpos = 0; useless as already done in default initialization */
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+    if (currentpin)
+    {
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Speed mode configuration */
+        if (currentpin < LL_GPIO_PIN_8)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+    }
+    pinpos++;
+  }
+
+  if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+  {
+    /* Check Output mode parameters */
+    assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+    /* Output mode configuration*/
+    LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+  }
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c
new file mode 100755
index 0000000..c17c264
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c
@@ -0,0 +1,255 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_i2c.h"
+#include "stm32l0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
+                                                 ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the I2C registers to their default reset values.
+  * @param  I2Cx I2C Instance.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are de-initialized
+  *          - ERROR: I2C registers are not de-initialized
+  */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+  }
+#if defined(I2C2)
+  else if (I2Cx == I2C2)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+  }
+#endif
+#if defined(I2C3)
+  else if (I2Cx == I2C3)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+  }
+#endif
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+  * @param  I2Cx I2C Instance.
+  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  /* Check the I2C parameters from I2C_InitStruct */
+  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+  /* Disable the selected I2Cx Peripheral */
+  LL_I2C_Disable(I2Cx);
+
+  /*---------------------------- I2Cx CR1 Configuration ------------------------
+   * Configure the analog and digital noise filters with parameters :
+   * - AnalogFilter: I2C_CR1_ANFOFF bit
+   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+   */
+  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+  /*---------------------------- I2Cx TIMINGR Configuration --------------------
+   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+   */
+  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+  /* Enable the selected I2Cx Peripheral */
+  LL_I2C_Enable(I2Cx);
+
+  /*---------------------------- I2Cx OAR1 Configuration -----------------------
+   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
+   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
+   */
+  LL_I2C_DisableOwnAddress1(I2Cx);
+  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+  /* OwnAdress1 == 0 is reserved for General Call address */
+  if (I2C_InitStruct->OwnAddress1 != 0U)
+  {
+    LL_I2C_EnableOwnAddress1(I2Cx);
+  }
+
+  /*---------------------------- I2Cx MODE Configuration -----------------------
+  * Configure I2Cx peripheral mode with parameter :
+   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+   */
+  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+  /*---------------------------- I2Cx CR2 Configuration ------------------------
+   * Configure the ACKnowledge or Non ACKnowledge condition
+   * after the address receive match code or next received byte with parameter :
+   * - TypeAcknowledge: I2C_CR2_NACK bit
+   */
+  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
+  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval None
+  */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Set I2C_InitStruct fields to default values */
+  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
+  I2C_InitStruct->Timing          = 0U;
+  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct->DigitalFilter   = 0U;
+  I2C_InitStruct->OwnAddress1     = 0U;
+  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c
new file mode 100755
index 0000000..33055e8
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lptim.c
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_lptim.c
+  * @author  MCD Application Team
+  * @brief   LPTIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_lptim.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2)
+
+/** @addtogroup LPTIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+                                       || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
+                                          || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+                                   || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+                                          || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set LPTIMx registers to their reset values.
+  * @param  LPTIMx LP Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx registers are de-initialized
+  *          - ERROR: invalid LPTIMx instance
+  */
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx)); 
+ 
+  if (LPTIMx == LPTIM1)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);  
+  } 
+#if defined(LPTIM2)
+  else if (LPTIMx == LPTIM2)
+  { 
+    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
+  }
+#endif
+  else
+  {
+    result = ERROR;
+  }
+  
+  return result;
+}
+
+/**
+  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
+  *         value.
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval None
+  */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  /* Set the default configuration */
+  LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+  LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
+  LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+  LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
+  * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+  * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+  * @param  LPTIMx LP Timer Instance
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx instance has been initialized
+  *          - ERROR: LPTIMx instance hasn't been initialized
+  */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+{
+  ErrorStatus result = SUCCESS;
+  
+  /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled 
+     (ENABLE bit is reset to 0).
+  */
+  if (LL_LPTIM_IsEnabled(LPTIMx))
+  {
+    result = ERROR;
+  }
+  else
+  {
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx)); 
+  assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+  assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+  assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+  
+  /* Set CKSEL bitfield according to ClockSource value */
+  /* Set PRESC bitfield according to Prescaler value */
+  /* Set WAVE bitfield according to Waveform value */
+  /* Set WAVEPOL bitfield according to Polarity value */
+  MODIFY_REG(LPTIMx->CFGR, 
+             (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), 
+             LPTIM_InitStruct->ClockSource | \
+             LPTIM_InitStruct->Prescaler | \
+             LPTIM_InitStruct->Waveform | \
+             LPTIM_InitStruct->Polarity);
+  }
+
+  return result;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (LPTIM1) || defined (LPTIM2) */
+
+/**
+  * @}
+  */
+  
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c
new file mode 100755
index 0000000..41d900e
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c
@@ -0,0 +1,257 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_lpuart.c
+  * @author  MCD Application Team
+  * @brief   LPUART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_lpuart.h"
+#include "stm32l0xx_ll_rcc.h"
+#include "stm32l0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @addtogroup LPUART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of LPUART registers                  */
+
+/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
+/*              value :                                                       */
+/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
+/*                - LPUART_BRR register value should be >= 0x300              */
+/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
+/*              Baudrate specified by the user should belong to [8, 10600000].*/
+#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 10600000U) && ((__BAUDRATE__) >= 8U))
+
+#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
+                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
+
+#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
+                                     || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
+                                     || ((__VALUE__) == LL_LPUART_PARITY_ODD))
+
+#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
+                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
+                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
+
+#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
+                                       || ((__VALUE__) == LL_LPUART_STOPBITS_2))
+
+#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
+                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPUART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize LPUART registers (Registers restored to their default values).
+  * @param  LPUARTx LPUART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+
+  /* Force reset of LPUART peripheral */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1);
+
+  /* Release reset of LPUART peripheral */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1);
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize LPUART registers according to the specified
+  *         parameters in LPUART_InitStruct.
+  * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
+  *         LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  LPUARTx LPUART Instance
+  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *         that contains the configuration information for the specified LPUART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+  *          - ERROR: Problem occurred during LPUART Registers initialization
+  */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
+  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
+  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
+  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+  /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+  {
+    /*---------------------------- LPUART CR1 Configuration -----------------------
+     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
+     */
+    MODIFY_REG(LPUARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
+
+    /*---------------------------- LPUART CR2 Configuration -----------------------
+     * Configure LPUARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
+     */
+    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
+
+    /*---------------------------- LPUART CR3 Configuration -----------------------
+     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
+     */
+    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- LPUART BRR Configuration -----------------------
+     * Retrieve Clock frequency used for LPUART Peripheral
+     */
+    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+
+    /* Configure the LPUART Baud Rate :
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (LPUART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_LPUART_SetBaudRate(LPUARTx,
+                            periphclk,
+                            LPUART_InitStruct->BaudRate);
+    }
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
+  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  /* Set LPUART_InitStruct fields to default values */
+  LPUART_InitStruct->BaudRate            = 9600U;
+  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
+  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
+  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
+  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
+  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (LPUART1) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c
new file mode 100755
index 0000000..5a958de
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c
@@ -0,0 +1,101 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_pwr.h"
+#include "stm32l0xx_ll_bus.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PWR_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the PWR registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PWR registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_PWR_DeInit(void)
+{
+  /* Force reset of PWR clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  /* Release reset of PWR clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined(PWR) */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c
new file mode 100755
index 0000000..8800614
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c
@@ -0,0 +1,650 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_rcc.h"
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+#elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+#endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */
+
+#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
+
+#if defined(RCC_CCIPR_I2C3SEL) 
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+#endif /* RCC_CCIPR_I2C3SEL */
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)
+
+#if defined(USB)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Reset the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *         - MSI  ON and used as system clock source
+  *         - HSE, HSI and PLL OFF
+  *         - AHB, APB1 and APB2 prescaler set to 1.
+  *         - CSS, MCO OFF
+  *         - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *         - Peripheral clocks
+  *         - LSI, LSE and RTC clocks
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RCC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RCC_DeInit(void)
+{
+  uint32_t vl_mask = 0U;
+
+  /* Set MSION bit */
+  LL_RCC_MSI_Enable();
+
+  /* Insure MSIRDY bit is set before writing default MSIRANGE value */
+  while (LL_RCC_MSI_IsReady() == 0U)
+  {
+    __NOP();
+  }
+
+  /* Set MSIRANGE default value */
+  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
+  /* Set MSITRIM bits to the reset value*/
+  LL_RCC_MSI_SetCalibTrimming(0U);
+
+  /* Set HSITRIM bits to the reset value*/
+  LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+  /* Reset SW, HPRE, PPRE and MCOSEL bits */
+  vl_mask = 0xFFFFFFFFU;
+  CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
+  LL_RCC_WriteReg(CFGR, vl_mask);
+
+  /* Reset HSI, HSE, PLL */
+  vl_mask = LL_RCC_ReadReg(CR);
+#if defined(RCC_CR_HSIOUTEN)  	
+  CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
+                     RCC_CR_HSEON | RCC_CR_PLLON); 
+#else
+  CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
+                     RCC_CR_HSEON | RCC_CR_PLLON); 
+#endif					 
+  LL_RCC_WriteReg(CR, vl_mask);
+  /* Delay after an RCC peripheral clock */
+  vl_mask = LL_RCC_ReadReg(CR);
+
+  /* Reset HSEBYP bit */
+  LL_RCC_HSE_DisableBypass();
+
+  /* Set RCC_CR_RTCPRE to 0b00*/
+  CLEAR_BIT(vl_mask, RCC_CR_RTCPRE); 
+  LL_RCC_WriteReg(CR, vl_mask);
+
+  /* Reset CFGR register */
+  LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+#if defined(RCC_HSI48_SUPPORT)
+  /* Reset CRRCR register */
+  LL_RCC_WriteReg(CRRCR, 0x00000000U);
+
+  /* Disable HSI48 */
+  LL_RCC_HSI48_Disable();
+
+#endif /*RCC_HSI48_SUPPORT*/
+
+  /* Disable all interrupts */
+  LL_RCC_WriteReg(CIER, 0x00000000U);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is MSI, function returns values based on MSI clock(*)
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on 
+  *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note   (*) MSI clock depends on the selected MSI range but the real value
+  *             may vary depending on the variations in voltage and temperature. 
+  * @note   (**) HSI_VALUE is a defined constant but the real value may vary 
+  *              depending on the variations in voltage and temperature.
+  * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
+  *               HSE_VALUE is same as the real frequency of the crystal used.
+  *               Otherwise, this function may have wrong result.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+  *         must be called to update structure fields. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval USART clock frequency (in Hz)
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+#if defined(RCC_CCIPR_USART1SEL)
+  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+  {
+    /* USART1CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
+      default:
+        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /* RCC_CCIPR_USART1SEL  */
+
+#if defined(RCC_CCIPR_USART2SEL)
+  if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+  {
+    /* USART2CLK clock frequency */
+    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+    {
+      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+        usart_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          usart_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          usart_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
+      default:
+        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /* RCC_CCIPR_USART2SEL */
+
+  return usart_frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices
+  * @retval I2C clock frequency (in Hz)
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  /* I2C1 CLK clock frequency */
+  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+  {
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+
+#if defined(RCC_CCIPR_I2C3SEL)
+  /* I2C3 CLK clock frequency */
+  if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+  {
+    switch (LL_RCC_GetI2CClockSource(I2CxSource))
+    {
+      case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+        i2c_frequency = RCC_GetSystemClockFreq();
+        break;
+
+      case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          i2c_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
+      default:
+        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+#endif /*RCC_CCIPR_I2C3SEL*/
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return LPUARTx clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval LPUART clock frequency (in Hz)
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
+
+  /* LPUART1CLK clock frequency */
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
+      lpuart_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
+      if (LL_RCC_HSI_IsReady())
+      {
+        lpuart_frequency = HSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
+      if (LL_RCC_LSE_IsReady())
+      {
+        lpuart_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
+    default:
+      lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+      break;
+  }
+
+  return lpuart_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
+  {
+    /* LPTIM1CLK clock frequency */
+    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+    {
+      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
+        if (LL_RCC_LSI_IsReady())
+        {
+          lptim_frequency = LSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
+        if (LL_RCC_HSI_IsReady())
+        {
+          lptim_frequency = HSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
+        if (LL_RCC_LSE_IsReady())
+        {
+          lptim_frequency = LSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
+      default:
+        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+        break;
+    }
+  }
+
+  return lptim_frequency;
+}
+
+#if defined(USB)
+/**
+  * @brief  Return USBx clock frequency
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval USB clock frequency (in Hz)
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
+  *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+  */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+  /* USBCLK clock frequency */
+  switch (LL_RCC_GetUSBClockSource(USBxSource))
+  {
+    case LL_RCC_USB_CLKSOURCE_PLL:        /* PLL clock used as USB clock source */
+      if (LL_RCC_PLL_IsReady())
+      {
+        usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_HSI48:      /* HSI48 clock used as USB clock source */
+    default:
+      if (LL_RCC_HSI48_IsReady())
+      {
+        usb_frequency = HSI48_VALUE;
+      }
+      break;
+  }
+
+  return usb_frequency;
+}
+#endif /* USB */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return SYSTEM clock frequency
+  * @retval SYSTEM clock frequency (in Hz)
+  */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
+      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
+      frequency = HSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
+      frequency = RCC_PLL_GetFreqDomain_SYS();
+      break;
+
+    default:
+      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PLL clock frequency used for system domain
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+  uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
+
+  /* Get PLL source */
+  pllsource = LL_RCC_PLL_GetMainSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:       /* HSI used as PLL clock source */
+      pllinputfreq = HSI_VALUE;
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */
+      pllinputfreq = HSE_VALUE;
+      break;
+
+    default:
+      pllinputfreq = HSI_VALUE;
+      break;
+  }
+  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c
new file mode 100755
index 0000000..1a62a32
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_rng.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize RNG registers (Registers restored to their default values).
+  * @param  RNGx RNG Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+
+  /* Enable RNG reset state */
+  LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
+
+  /* Release RNG from reset state */
+  LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
+
+  return (SUCCESS);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (RNG) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c
new file mode 100755
index 0000000..2f976ec
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rtc.c
@@ -0,0 +1,895 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_rtc.c
+  * @author  MCD Application Team
+  * @brief   RTC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_rtc.h"
+#include "stm32l0xx_ll_cortex.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+  * @{
+  */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
+#define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= (uint32_t)0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= (uint32_t)0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are de-initialized
+  *          - ERROR: RTC registers are not de-initialized
+  */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Reset TR, DR and CR registers */
+    LL_RTC_WriteReg(RTCx, TR,       0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+    LL_RTC_WriteReg(RTCx, WUTR,     RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+    LL_RTC_WriteReg(RTCx, DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+    /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+    LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
+#else
+    LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+    LL_RTC_WriteReg(RTCx, PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+    LL_RTC_WriteReg(RTCx, ALRMAR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMBR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, SHIFTR,   0x00000000U);
+    LL_RTC_WriteReg(RTCx, CALR,     0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
+    LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
+
+    /* Reset ISR register and exit initialization mode */
+    LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
+
+    /* Reset Tamper and alternate functions configuration register */
+    LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
+
+    /* Reset Option register */
+    LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
+
+    /* Wait till the RTC RSF flag is set */
+    status = LL_RTC_WaitForSynchro(RTCx);
+  }
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters
+  *         in RTC_InitStruct.
+  * @param  RTCx RTC Instance
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in
+  *         initialization mode only.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized
+  */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Set Hour Format */
+    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+    /* Configure Synchronous and Asynchronous prescaler factor */
+    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  /* Set RTC_InitStruct fields to default values */
+  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
+  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+    }
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+    }
+    else
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTC);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+  RTC_TimeStruct->Hours      = 0U;
+  RTC_TimeStruct->Minutes    = 0U;
+  RTC_TimeStruct->Seconds    = 0U;
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Day register is configured
+  *          - ERROR: RTC Day register is not configured
+  */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+  {
+    RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+  }
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+  }
+  else
+  {
+    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+  }
+  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+    }
+    else
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTC);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+  RTC_DateStruct->Day     = 1U;
+  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
+  RTC_DateStruct->Year    = 0U;
+}
+
+/**
+  * @brief  Set the RTC Alarm A.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMA registers are configured
+  *          - ERROR: ALARMA registers are not configured
+  */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMA_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMA_EnableWeekday(RTCx);
+    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the RTC Alarm B.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (@ref LL_RTC_ALMB_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMB registers are configured
+  *          - ERROR: ALARMB registers are not configured
+  */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMB_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMB_EnableWeekday(RTCx);
+    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp = 0U;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Check if the Initialization mode is set */
+  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+  {
+    /* Set the Initialization mode */
+    LL_RTC_EnableInitMode(RTCx);
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout --;
+      }
+      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Exit the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts
+  *         counting after 4 RTCCLK cycles.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC exited from in Init mode
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable initialization mode */
+  LL_RTC_DisableInitMode(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp = 0U;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Clear RSF flag */
+  LL_RTC_ClearFlag_RS(RTCx);
+
+  /* Wait the registers to be synchronised */
+  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+  while ((timeout != 0U) && (tmp != 0U))
+  {
+    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+    {
+      timeout--;
+    }
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    if (timeout == 0U)
+    {
+      status = ERROR;
+    }
+  }
+
+  if (status != ERROR)
+  {
+    timeout = RTC_SYNCHRO_TIMEOUT;
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout--;
+      }
+      tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c
new file mode 100755
index 0000000..c196690
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c
@@ -0,0 +1,532 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_spi.c
+  * @author  MCD Application Team
+  * @brief   SPI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_spi.h"
+#include "stm32l0xx_ll_bus.h"
+#include "stm32l0xx_ll_rcc.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2)
+
+/** @addtogroup SPI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+  * @{
+  */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
+                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
+                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
+                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
+                                            SPI_CR1_BIDIMODE)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  * @{
+  */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
+                                              || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
+                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+                                || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
+                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+                                    || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+                                 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+                               || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+                               || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+                                    || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+                                          || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+  if (SPIx == SPI1)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    status = SUCCESS;
+  }
+#endif /* SPI1 */
+#if defined(SPI2)
+  if (SPIx == SPI2)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    status = SUCCESS;
+  }
+#endif /* SPI2 */
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the SPI Instance SPIx*/
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+  /* Check the SPI parameters from SPI_InitStruct*/
+  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx CR1 Configuration ------------------------
+     * Configure SPIx CR1 with parameters:
+     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+     * - Master/Slave Mode:  SPI_CR1_MSTR bit
+     * - DataWidth:          SPI_CR1_DFF bit
+     * - ClockPolarity:      SPI_CR1_CPOL bit
+     * - ClockPhase:         SPI_CR1_CPHA bit
+     * - NSS management:     SPI_CR1_SSM bit
+     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+     * - BitOrder:           SPI_CR1_LSBFIRST bit
+     * - CRCCalculation:     SPI_CR1_CRCEN bit
+     */
+    MODIFY_REG(SPIx->CR1,
+               SPI_CR1_CLEAR_MASK,
+               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
+               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+    /*---------------------------- SPIx CR2 Configuration ------------------------
+     * Configure SPIx CR2 with parameters:
+     * - NSS management:     SSOE bit
+     */
+    MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
+
+    /*---------------------------- SPIx CRCPR Configuration ----------------------
+     * Configure SPIx CRCPR with parameters:
+     * - CRCPoly:            CRCPOLY[15:0] bits
+     */
+    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+    {
+      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+    }
+    status = SUCCESS;
+  }
+
+#if defined (SPI_I2S_SUPPORT)
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * whose fields will be set to default values.
+  * @retval None
+  */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  /* Set SPI_InitStruct fields to default values */
+  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct->CRCPoly           = 7U;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+  * @{
+  */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
+                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
+                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK               0x0002U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+  * @{
+  */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
+                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
+                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
+                                       || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
+                                       || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
+                                       || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
+                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
+                                       || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
+                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+                                       || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
+                                       && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+                                       || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+                                           || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2S_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI/I2S registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_DeInit(SPIx);
+}
+
+/**
+  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are Initialized
+  *          - ERROR: SPI registers are not Initialized
+  */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+  uint32_t tmp = 0U;
+  LL_RCC_ClocksTypeDef rcc_clocks;
+  uint32_t sourceclock = 0U;
+  ErrorStatus status = ERROR;
+
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx I2SCFGR Configuration --------------------
+     * Configure SPIx I2SCFGR with parameters:
+     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
+     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+     */
+
+    /* Write to SPIx I2SCFGR */
+    MODIFY_REG(SPIx->I2SCFGR,
+               I2S_I2SCFGR_CLEAR_MASK,
+               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+               SPI_I2SCFGR_I2SMOD);
+
+    /*---------------------------- SPIx I2SPR Configuration ----------------------
+     * Configure SPIx I2SPR with parameters:
+     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
+     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+     */
+
+    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
+     */
+    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+    {
+      /* Check the frame length (For the Prescaler computing)
+       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+       */
+      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+      {
+        /* Packet length is 32 bits */
+        packetlength = 2U;
+      }
+
+      /* I2S Clock source is System clock: Get System Clock frequency */
+      LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+      /* Get the source clock value: based on System Clock value */
+      sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+      /* Compute the Real divider depending on the MCLK output state with a floating point */
+      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+      {
+        /* MCLK output is enabled */
+        tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+      else
+      {
+        /* MCLK output is disabled */
+        tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+
+      /* Remove the floating point */
+      tmp = tmp / 10U;
+
+      /* Check the parity of the divider */
+      i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+      /* Compute the i2sdiv prescaler */
+      i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+      i2sodd = (uint16_t)(i2sodd << 8U);
+    }
+
+    /* Test if the divider is 1 or 0 or greater than 0xFF */
+    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+    {
+      /* Set the default values */
+      i2sdiv = 2U;
+      i2sodd = 0U;
+    }
+
+    /* Write to SPIx I2SPR register the computed value */
+    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+    status = SUCCESS;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
+  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
+  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
+  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
+  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
+  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
+}
+
+/**
+  * @brief  Set linear and parity prescaler.
+  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+  /* Write to SPIx I2SPR */
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
new file mode 100755
index 0000000..00fd420
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
@@ -0,0 +1,864 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_tim.h"
+#include "stm32l0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
+
+/** @addtogroup TIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+                                   || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+                                      || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                               || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+  * @{
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set TIMx registers to their reset values.
+  * @param  TIMx Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: invalid TIMx instance
+  */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+
+  if (TIMx == TIM2)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+  }
+#if defined(TIM3)
+  else if (TIMx == TIM3)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+  }
+#endif /* TIM3 */
+#if defined(TIM6)
+  else if (TIMx == TIM6)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+  }
+#endif /* TIM6 */
+#if defined(TIM7)
+  else if (TIMx == TIM7)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+  }
+#endif /* TIM7 */
+  else if (TIMx == TIM21)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21);
+  }
+#if defined(TIM22)
+  else if (TIMx == TIM22)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22);
+  }
+#endif /* TIM22 */
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the time base unit configuration data structure
+  *         to their default values.
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+  * @retval None
+  */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
+  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct->Autoreload        = (uint32_t)0xFFFFFFFFU;
+  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+}
+
+/**
+  * @brief  Configure the TIMx time base unit.
+  * @param  TIMx Timer Instance
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  uint32_t tmpcr1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+  }
+
+  /* Write to TIMx CR1 */
+  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+  /* Set the Autoreload value */
+  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+  /* Set the Prescaler value */
+  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter value (if applicable) immediately */
+  LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx output channel configuration data
+  *         structure to their default values.
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
+  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
+  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+}
+
+/**
+  * @brief  Configure the TIMx output channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = OC1Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = OC2Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = OC3Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = OC4Config(TIMx, TIM_OC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the TIMx input channel configuration data
+  *         structure to their default values.
+  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the TIMx input channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = IC1Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = IC2Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = IC3Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = IC4Config(TIMx, TIM_IC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Fills each TIM_EncoderInitStruct field with its default value
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+  * @retval None
+  */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  /* Set the default configuration */
+  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
+  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the encoder interface of the timer instance.
+  * @param  TIMx Timer Instance
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Configure TI1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure TI2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Set encoder mode */
+  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ *  @brief   Private functions
+  * @{
+  */
+/**
+  * @brief  Configure the TIMx output channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+  /* Set the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2 = 0U;
+  uint32_t tmpccer = 0U;
+  uint32_t tmpcr2 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+
+/**
+  * @brief  Configure the TIMx input channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC3E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+  return SUCCESS;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
new file mode 100755
index 0000000..e442a67
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
@@ -0,0 +1,433 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_usart.h"
+#include "stm32l0xx_ll_rcc.h"
+#include "stm32l0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                    || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                       || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                      || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+#if defined(USART1)
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+#endif /* USART1 */
+#if defined(USART1)
+  else if (USARTx == USART2)
+#else
+  if (USARTx == USART2)
+#endif
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+#if defined(USART4)
+  else if (USARTx == USART4)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
+  }
+#endif /* USART4 */
+#if defined(USART5)
+  else if (USARTx == USART5)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
+  }
+#endif /* USART5 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+#if (defined(USART4) || defined(USART5))
+  LL_RCC_ClocksTypeDef RCC_Clocks;
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration -----------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration -----------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration -----------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration -----------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+#if defined(USART1)
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+    }
+#endif /* USART1 */
+#if defined(USART1)
+    else if (USARTx == USART2)
+#else
+    if (USARTx == USART2)
+#endif
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+    }
+#if defined(USART4)
+    else if (USARTx == USART4)
+    {
+      /* USART4 clock is PCLK1 */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+    }
+#endif /* USART4 */
+#if defined(USART5)
+    else if (USARTx == USART5)
+    {
+      /* USART5 clock is PCLK1 */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+    }
+#endif /* USART5 */
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+    }
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR2 Configuration -----------------------*/
+    /* If Clock signal has to be output */
+    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+    {
+      /* Deactivate Clock signal delivery :
+       * - Disable Clock Output:        USART_CR2_CLKEN cleared
+       */
+      LL_USART_DisableSCLKOutput(USARTx);
+    }
+    else
+    {
+      /* Ensure USART instance is USART capable */
+      assert_param(IS_USART_INSTANCE(USARTx));
+
+      /* Check clock related parameters */
+      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+      /*---------------------------- USART CR2 Configuration -----------------------
+       * Configure USARTx CR2 (Clock signal related bits) with parameters:
+       * - Enable Clock Output:         USART_CR2_CLKEN set
+       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+       */
+      MODIFY_REG(USARTx->CR2,
+                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+    }
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                               whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART4 || USART5 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
new file mode 100755
index 0000000..d0aa593
--- /dev/null
+++ b/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
@@ -0,0 +1,575 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_ll_rcc.h"
+#include "stm32l0xx_ll_utils.h"
+#include "stm32l0xx_ll_system.h"
+#include "stm32l0xx_ll_pwr.h"
+
+/** @addtogroup STM32L0xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#define UTILS_MAX_FREQUENCY_SCALE1  ((uint32_t)32000000U)        /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  ((uint32_t)16000000U)        /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3  ((uint32_t)4000000U)         /*!< Maximum frequency for system clock at power scale3, in Hz */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_OUTPUT_SCALE1  ((uint32_t)96000000U)        /*!< Frequency max for PLLVCO output at power scale1, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_SCALE2  ((uint32_t)48000000U)        /*!< Frequency max for PLLVCO output at power scale2, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_SCALE3  ((uint32_t)24000000U)        /*!< Frequency max for PLLVCO output at power scale3, in Hz  */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN     ((uint32_t)1000000U)         /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     ((uint32_t)24000000U)        /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY1_FREQ  ((uint32_t)16000000U)        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE2_LATENCY1_FREQ  ((uint32_t)8000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE3_LATENCY1_FREQ  ((uint32_t)2000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_16) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_24) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_32) \
+                                          || ((__VALUE__) == LL_RCC_PLL_MUL_48))
+
+#define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \
+                                             ((__VALUE__) == LL_RCC_PLL_DIV_4))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \
+                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \
+                                             ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3)))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                             ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)))
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  HCLKFrequency HCLK frequency in Hz
+  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if (Delay < LL_MAX_DELAY)
+  {
+    Delay++;
+  }
+
+  while (Delay)
+  {
+    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      Delay--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +----------------------------------------------------------------+
+             (++) |  Wait states  |                HCLK clock frequency (MHz)      |
+             (++) |               |------------------------------------------------|
+             (++) |   (Latency)   |            voltage range       | voltage range |
+             (++) |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
+             (++) |               |----------------|---------------|---------------|
+             (++) |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
+             (++) |-------------- |----------------|---------------|---------------|
+             (++) |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
+             (++) |---------------|----------------|---------------|---------------|
+             (++) |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
+             (++) +----------------------------------------------------------------+
+  @endinternal
+  * @{
+  */
+
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @retval None
+  */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = HCLKFrequency;
+}
+
+/**
+  * @brief  This function configures system clock with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv)
+  *         - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding
+  *           - 96 MHz as PLLVCO when the product is in range 1,
+  *           - 48 MHz as PLLVCO when the product is in range 2,
+  *           - 24 MHz when the product is in range 3
+  * @note   FLASH latency can be modified through this function. 
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check if one of the PLL is enabled */
+  if (UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if (LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv)
+  *         - PLLMul: The application software must set correctly the PLL multiplication factor to avoid exceeding
+  *           - 96 MHz as PLLVCO when the product is in range 1,
+  *           - 48 MHz as PLLVCO when the product is in range 2,
+  *           - 24 MHz when the product is in range 3
+  * @note   FLASH latency can be modified through this function. 
+  * @param  HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check if one of the PLL is enabled */
+  if (UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if (LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+      /* Configure PLL */
+      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+            voltage range.
+  * @param  Frequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
+{
+  ErrorStatus status = SUCCESS;
+
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+
+  /* Frequency cannot be equal to 0 */
+  if (Frequency == 0U)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if (Frequency > UTILS_SCALE1_LATENCY1_FREQ)
+      {
+        /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */
+     }
+    else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+    {
+      if (Frequency > UTILS_SCALE2_LATENCY1_FREQ)
+      {
+        /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */
+    }
+    else
+    {
+      if (Frequency > UTILS_SCALE3_LATENCY1_FREQ)
+      {
+        /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      /* else HCLK < 4MHz default LL_FLASH_LATENCY_0 0WS */
+    }
+
+    LL_FLASH_SetLatency(latency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+       memory by reading the FLASH_ACR register */
+    if (LL_FLASH_GetLatency() != latency)
+    {
+      status = ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
+  assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+
+  /* Check different PLL parameters according to RM                          */
+  /* The application software must set correctly the PLL multiplication factor to avoid exceeding
+     96 MHz as PLLVCO when the product is in range 1,
+     48 MHz as PLLVCO when the product is in range 2,
+     24 MHz when the product is in range 3. */
+  pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_POSITION_PLLMUL]);
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+  /* The application software must set correctly the PLL multiplication factor to avoid exceeding 
+     maximum frequency 32000000 in range 1 */
+  pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_POSITION_PLLDIV)+1U);
+  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PLL modification can be done
+  *          - ERROR: PLL is busy
+  */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if PLL is busy*/
+  if (LL_RCC_PLL_IsReady() != 0U)
+  {
+    /* PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t hclk_frequency = 0U;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+  /* Calculate HCLK frequency */
+  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if (SystemCoreClock < hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = UTILS_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if (status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL_Enable();
+    while (LL_RCC_PLL_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APB1 & APB2 prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (SystemCoreClock > hclk_frequency)
+  {
+    /* Set FLASH latency to lowest latency */
+    status = UTILS_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update SystemCoreClock variable */
+  if (status == SUCCESS)
+  {
+    LL_SetSystemCoreClock(hclk_frequency);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/main.h b/Inc/main.h
old mode 100644
new mode 100755
diff --git a/Middlewares/Third_Party/Lora/Utilities/utilities.h b/Middlewares/Third_Party/Lora/Utilities/utilities.h
index 5c1b582..a1385bb 100755
--- a/Middlewares/Third_Party/Lora/Utilities/utilities.h
+++ b/Middlewares/Third_Party/Lora/Utilities/utilities.h
@@ -62,6 +62,12 @@ Maintainer: Miguel Luis and Gregory Cristian
 
 #include "hw_conf.h"
 
+// this should not be needed here :/
+#ifndef ARM_MATH_CM0
+#define ARM_MATH_CM0
+#endif
+
+#include "arm_math.h"
 
 /* BACKUP_PRIMASK MUST be implemented at the begining of the funtion 
    that implement a critical section                        
@@ -112,7 +118,7 @@ typedef uint32_t TimerTime_t;
  * \param [in]  value  Value to find least significant index
  * \retval bitIndex    Index of least significat bit at one
  */
-__STATIC_INLINE uint8_t __ffs( uint32_t value )
+static inline uint8_t __ffs( uint32_t value )
 {
     return( uint32_t )( 32 - __CLZ( value & ( -value ) ) );
 }
diff --git a/NUCLEO-L073RZ.xml b/NUCLEO-L073RZ.xml
old mode 100644
new mode 100755
diff --git a/STM32L073RZTx_FLASH.ld b/STM32L073RZTx_FLASH.ld
old mode 100644
new mode 100755
diff --git a/Src/main.c b/Src/main.c
index 505f3fd..4e811e8 100755
--- a/Src/main.c
+++ b/Src/main.c
@@ -112,6 +112,10 @@ static void LoraTxData(lora_AppData_t *AppData, FunctionalState *IsTxConfirmed);
 /* call back when LoRa has received a frame*/
 static void LoraRxData(lora_AppData_t *AppData);
 
+uint8_t HW_GetBatteryLevel(void) {
+	return 254;
+}
+
 /* Private variables ---------------------------------------------------------*/
 /* load call backs*/
 static LoRaMainCallback_t LoRaMainCallbacks = {HW_GetBatteryLevel,
@@ -120,11 +124,6 @@ static LoRaMainCallback_t LoRaMainCallbacks = {HW_GetBatteryLevel,
                                                LoraTxData,
                                                LoraRxData};
 
-/*!
- * Specifies the state of the application LED
- */
-static uint8_t AppLedStateOn = RESET;
-
 
 #ifdef USE_B_L072Z_LRWAN1
 /*!
@@ -146,6 +145,7 @@ static LoRaParam_t LoRaParamInit = {TX_ON_TIMER,
 
 /* Private functions ---------------------------------------------------------*/
 
+
 /**
   * @brief  Main program
   * @param  None
@@ -175,6 +175,7 @@ int main(void)
 
 	/* main loop*/
 	while (1) {
+
 		/* run the LoRa class A state machine*/
 		lora_fsm();
 
@@ -196,6 +197,7 @@ int main(void)
 static void LoraTxData(lora_AppData_t *AppData, FunctionalState *IsTxConfirmed)
 {
 	/* USER CODE BEGIN 3 */
+	PRINTF("Lora TX");
 
 	AppData->Port = LORAWAN_APP_PORT;
 
@@ -211,6 +213,8 @@ static void LoraTxData(lora_AppData_t *AppData, FunctionalState *IsTxConfirmed)
 static void LoraRxData(lora_AppData_t *AppData)
 {
 	/* USER CODE BEGIN 4 */
+	PRINTF("Lora RX");
+
 	switch (AppData->Port) {
 		case LORAWAN_APP_PORT:
 
diff --git a/Src/stm32l0xx_hw.c b/Src/stm32l0xx_hw.c
index 7f6d5d9..1efc12d 100755
--- a/Src/stm32l0xx_hw.c
+++ b/Src/stm32l0xx_hw.c
@@ -112,7 +112,7 @@ void HW_Init( void )
     NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x3000 );
 #endif
 
-    HW_AdcInit( );
+   // HW_AdcInit( );
 
     Radio.IoInit( );
     
diff --git a/Src/system_stm32l0xx.c b/Src/system_stm32l0xx.c
new file mode 100755
index 0000000..9ec790e
--- /dev/null
+++ b/Src/system_stm32l0xx.c
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l0xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+   
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 2000000U;
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{    
+/*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100U;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+ 
+  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+  
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+  /*!< Disable all interrupts */
+  RCC->CIER = 0x00000000U;
+  
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+    case 0x04U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0CU:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18U)];
+      plldiv = (plldiv >> 22U) + 1U;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/junk/gpio.c b/junk/gpio.c
old mode 100644
new mode 100755
diff --git a/junk/gpio.h b/junk/gpio.h
old mode 100644
new mode 100755
diff --git a/junk/i2c.c b/junk/i2c.c
old mode 100644
new mode 100755
diff --git a/junk/i2c.h b/junk/i2c.h
old mode 100644
new mode 100755
diff --git a/junk/main.c b/junk/main.c
old mode 100644
new mode 100755
diff --git a/junk/rtc.c b/junk/rtc.c
old mode 100644
new mode 100755
diff --git a/junk/rtc.h b/junk/rtc.h
old mode 100644
new mode 100755
diff --git a/junk/spi.c b/junk/spi.c
old mode 100644
new mode 100755
diff --git a/junk/spi.h b/junk/spi.h
old mode 100644
new mode 100755
diff --git a/junk/stm32l0xx_hal_conf.h b/junk/stm32l0xx_hal_conf.h
old mode 100644
new mode 100755
diff --git a/junk/stm32l0xx_hal_msp.c-mx b/junk/stm32l0xx_hal_msp.c-mx
old mode 100644
new mode 100755
diff --git a/junk/stm32l0xx_it.c-mx b/junk/stm32l0xx_it.c-mx
old mode 100644
new mode 100755
diff --git a/junk/stm32l0xx_it.h b/junk/stm32l0xx_it.h
old mode 100644
new mode 100755
diff --git a/junk/system_stm32l0xx.c- b/junk/system_stm32l0xx.c-
old mode 100644
new mode 100755
diff --git a/junk/usart.c b/junk/usart.c
old mode 100644
new mode 100755
diff --git a/junk/usart.h b/junk/usart.h
old mode 100644
new mode 100755
diff --git a/mx.scratch b/mx.scratch
old mode 100644
new mode 100755
diff --git a/proj Debug.cfg b/proj Debug.cfg
old mode 100644
new mode 100755
diff --git a/proj.ioc b/proj.ioc
old mode 100644
new mode 100755
diff --git a/startup/startup_stm32l073xx.s b/startup/startup_stm32l073xx.s
old mode 100644
new mode 100755