electro
/
spd-lorabees
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
B3M38SPD seminar project - beehive monitor with LoRa reporting
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
7 Commits
1 Branch
0 Tags
15 MiB
Tag: Branch: Tree: 173dd90528
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '173dd90528'
${ noResults }
spd-lorabees/build/stm32l0xx_hal_pwr.lst

2042 lines
133 KiB
Raw Normal View History Unescape

got the voc sensor to do something
7 years ago
ARM GAS /tmp/ccnH7zer.s page 1
1 .cpu cortex-m0plus
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 0
10 .eabi_attribute 18, 4
11 .file "stm32l0xx_hal_pwr.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_PWR_DeInit,"ax",%progbits
16 .align 1
17 .global HAL_PWR_DeInit
18 .syntax unified
19 .code 16
20 .thumb_func
21 .fpu softvfp
23 HAL_PWR_DeInit:
24 .LFB39:
25 .file 1 "./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c"
1:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
2:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ******************************************************************************
3:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @file stm32l0xx_hal_pwr.c
4:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @author MCD Application Team
5:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief PWR HAL module driver.
6:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
7:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This file provides firmware functions to manage the following
8:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
9:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + Initialization/de-initialization functions
10:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * + Peripheral Control functions
11:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
12:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ******************************************************************************
13:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @attention
14:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
15:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
16:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
17:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Redistribution and use in source and binary forms, with or without modification,
18:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * are permitted provided that the following conditions are met:
19:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 1. Redistributions of source code must retain the above copyright notice,
20:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * this list of conditions and the following disclaimer.
21:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 2. Redistributions in binary form must reproduce the above copyright notice,
22:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * this list of conditions and the following disclaimer in the documentation
23:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * and/or other materials provided with the distribution.
24:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors
25:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * may be used to endorse or promote products derived from this software
26:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * without specific prior written permission.
27:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
28:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ARM GAS /tmp/ccnH7zer.s page 2
34:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
39:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ******************************************************************************
40:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
41:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
42:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
43:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #include "stm32l0xx_hal.h"
44:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
45:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
46:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup STM32L0xx_HAL_Driver
47:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
48:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
49:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
50:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR
51:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
52:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
53:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
54:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Private
55:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
56:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
57:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
58:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
59:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
60:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
61:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_MODE_IT ((uint32_t)0x00010000U)
62:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_MODE_EVT ((uint32_t)0x00020000U)
63:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
64:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
65:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
66:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @}
67:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
68:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
69:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
70:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @}
71:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
72:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
73:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
74:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions
75:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
76:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
77:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
78:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group1
79:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
80:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
81:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @verbatim
82:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ===============================================================================
83:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
84:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ===============================================================================
85:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
86:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @endverbatim
87:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
88:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
89:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
90:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
ARM GAS /tmp/ccnH7zer.s page 3
91:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
92:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
93:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
94:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
95:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
26 .loc 1 95 0
27 .cfi_startproc
28 @ args = 0, pretend = 0, frame = 0
29 @ frame_needed = 0, uses_anonymous_args = 0
30 @ link register save eliminated.
96:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
31 .loc 1 96 0
32 0000 054B ldr r3, .L2
33 0002 996A ldr r1, [r3, #40]
34 0004 8022 movs r2, #128
35 0006 5205 lsls r2, r2, #21
36 0008 0A43 orrs r2, r1
37 000a 9A62 str r2, [r3, #40]
97:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
38 .loc 1 97 0
39 000c 9A6A ldr r2, [r3, #40]
40 000e 0349 ldr r1, .L2+4
41 0010 0A40 ands r2, r1
42 0012 9A62 str r2, [r3, #40]
98:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
43 .loc 1 98 0
44 @ sp needed
45 0014 7047 bx lr
46 .L3:
47 0016 C046 .align 2
48 .L2:
49 0018 00100240 .word 1073876992
50 001c FFFFFFEF .word -268435457
51 .cfi_endproc
52 .LFE39:
54 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
55 .align 1
56 .global HAL_PWR_EnableBkUpAccess
57 .syntax unified
58 .code 16
59 .thumb_func
60 .fpu softvfp
62 HAL_PWR_EnableBkUpAccess:
63 .LFB40:
99:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
100:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
101:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @}
102:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
103:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
104:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group2
105:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Low Power modes configuration functions
106:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
107:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @verbatim
108:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
109:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ===============================================================================
110:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ##### Peripheral Control functions #####
111:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ===============================================================================
ARM GAS /tmp/ccnH7zer.s page 4
112:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
113:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Backup domain ***
114:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =========================
115:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
116:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
117:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** registers) is protected against possible unwanted
118:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** write accesses.
119:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
120:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
121:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
122:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
123:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
124:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** PVD configuration ***
125:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =========================
126:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
127:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a
128:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
129:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD can use an external input analog voltage (PVD_IN) which is compared
130:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
131:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
132:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
133:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
134:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI
135:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through
136:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
137:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode.
138:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
139:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** WakeUp pin configuration ***
140:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================================
141:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
142:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
143:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges.
144:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) There are two WakeUp pins:
145:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 1 on PA.00.
146:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 2 on PC.13.
147:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** WakeUp Pin 3 on PE.06 .
148:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
149:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
150:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
151:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
152:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ================================================
153:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
154:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The main internal regulator can be configured to have a tradeoff between
155:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** performance and power consumption when the device does not operate at
156:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
157:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** macro which configures the two VOS bits in PWR_CR register:
158:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mod
159:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 32 MHz.
160:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mod
161:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 16 MHz.
162:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mod
163:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the System frequency can go up to 4.2 MHz.
164:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
165:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Refer to the datasheets for more details.
166:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
167:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low Power modes configuration ***
168:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =====================================
ARM GAS /tmp/ccnH7zer.s page 5
169:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
170:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The device features 5 low-power modes:
171:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Low power run mode: regulator in low power mode, limited clock frequency,
172:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** limited number of peripherals running.
173:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running.
174:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
175:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** limited number of peripherals running, regulator in low power mode.
176:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
177:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Standby mode: VCORE domain powered off
178:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
179:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low power run mode ***
180:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =========================
181:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
182:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To further reduce the consumption when the system is in Run mode, the regulator can be
183:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** configured in low power mode. In this mode, the system frequency should not exceed
184:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** MSI frequency range1.
185:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Low power run mode, all I/O pins keep the same state as in Run mode.
186:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
187:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry:
188:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) VCORE in range2
189:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1.
190:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
191:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function.
192:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit:
193:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunM
194:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function.
195:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Increase the system frequency if needed.
196:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
197:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Sleep mode ***
198:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ==================
199:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
200:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry:
201:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
202:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions with
203:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
204:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
205:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
206:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit:
207:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
208:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was
209:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the MCU exits Sleep mode as soon as an event occurs.
210:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
211:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Low power sleep mode ***
212:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ============================
213:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
214:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry:
215:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGUL
216:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions with
217:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
218:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
219:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_AC
220:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** This reduces power consumption but increases the wake-up time.
221:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
222:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit:
223:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrup
224:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** acknowledged by the nested vectored interrupt controller (NVIC) can wake up the devic
225:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** from Low power sleep mode. If the WFE instruction was used to enter Low power sleep m
ARM GAS /tmp/ccnH7zer.s page 6
226:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the MCU exits Sleep mode as soon as an event occurs.
227:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
228:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Stop mode ***
229:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =================
230:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
231:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
232:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** clock gating. The voltage regulator can be configured either in normal or low-power mode.
233:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
234:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
235:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To get the lowest consumption in Stop mode, the internal Flash memory also enters low
236:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** power mode. When the Flash memory is in power-down mode, an additional startup delay is
237:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** incurred when waking up from Stop mode.
238:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
239:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** sensor can be switched off before entering Stop mode. They can be switched on again by
240:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** software after exiting Stop mode using the ULP bit in the PWR_CR register.
241:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** In Stop mode, all I/O pins keep the same state as in Run mode.
242:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
243:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry:
244:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode
245:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function with:
246:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Main regulator ON.
247:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) Low Power regulator ON.
248:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
249:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
250:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit:
251:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC
252:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
253:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** register
254:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
255:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Standby mode ***
256:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** ====================
257:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
258:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based on the
259:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is
260:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
261:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** also switched off. SRAM and register contents are lost except for the RTC registers, RTC
262:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** backup registers and Standby circuitry.
263:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
264:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
265:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** sensor can be switched off before entering the Standby mode. They can be switched
266:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** on again by software after exiting the Standby mode.
267:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function.
268:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
269:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Entry:
270:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
271:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Exit:
272:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
273:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
274:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
275:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
276:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** =============================================
277:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** [..]
278:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
279:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
280:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
281:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
282:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop mode
ARM GAS /tmp/ccnH7zer.s page 7
283:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
284:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
285:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function.
286:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
287:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
288:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and RTC_AlarmCmd() functions.
289:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
290:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** is necessary to:
291:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
292:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function.
293:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
294:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function.
295:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to detect the tamper or time stamp event using the
296:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
297:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions.
298:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
299:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
300:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** or Event modes) using the EXTI_Init() function.
301:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
302:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConf
303:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
304:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
305:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Standby mode
306:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
307:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
308:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
309:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and RTC_AlarmCmd() functions.
310:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
311:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** is necessary to:
312:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
313:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** function.
314:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to detect the tamper or time stamp event using the
315:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
316:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** functions.
317:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
318:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
319:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConf
320:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
321:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
322:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
323:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
324:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** event, it is necessary to:
325:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
326:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
327:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
328:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
329:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** @endverbatim
330:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @{
331:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
332:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
333:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
334:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
335:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * backup data registers ).
336:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
337:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
338:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
339:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
ARM GAS /tmp/ccnH7zer.s page 8
340:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
341:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
64 .loc 1 341 0
65 .cfi_startproc
66 @ args = 0, pretend = 0, frame = 0
67 @ frame_needed = 0, uses_anonymous_args = 0
68 @ link register save eliminated.
342:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable access to RTC and backup registers */
343:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
69 .loc 1 343 0
70 0000 034A ldr r2, .L5
71 0002 1168 ldr r1, [r2]
72 0004 8023 movs r3, #128
73 0006 5B00 lsls r3, r3, #1
74 0008 0B43 orrs r3, r1
75 000a 1360 str r3, [r2]
344:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
76 .loc 1 344 0
77 @ sp needed
78 000c 7047 bx lr
79 .L6:
80 000e C046 .align 2
81 .L5:
82 0010 00700040 .word 1073770496
83 .cfi_endproc
84 .LFE40:
86 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
87 .align 1
88 .global HAL_PWR_DisableBkUpAccess
89 .syntax unified
90 .code 16
91 .thumb_func
92 .fpu softvfp
94 HAL_PWR_DisableBkUpAccess:
95 .LFB41:
345:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
346:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
347:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables access to the backup domain
348:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Applies to RTC registers, RTC backup data registers.
349:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
350:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
351:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
352:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
353:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
354:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
96 .loc 1 354 0
97 .cfi_startproc
98 @ args = 0, pretend = 0, frame = 0
99 @ frame_needed = 0, uses_anonymous_args = 0
100 @ link register save eliminated.
355:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable access to RTC and backup registers */
356:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
101 .loc 1 356 0
102 0000 024A ldr r2, .L8
103 0002 1368 ldr r3, [r2]
104 0004 0249 ldr r1, .L8+4
105 0006 0B40 ands r3, r1
ARM GAS /tmp/ccnH7zer.s page 9
106 0008 1360 str r3, [r2]
357:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
107 .loc 1 357 0
108 @ sp needed
109 000a 7047 bx lr
110 .L9:
111 .align 2
112 .L8:
113 000c 00700040 .word 1073770496
114 0010 FFFEFFFF .word -257
115 .cfi_endproc
116 .LFE41:
118 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits
119 .align 1
120 .global HAL_PWR_ConfigPVD
121 .syntax unified
122 .code 16
123 .thumb_func
124 .fpu softvfp
126 HAL_PWR_ConfigPVD:
127 .LFB42:
358:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
359:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
360:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
361:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
362:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * information for the PVD.
363:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for
364:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each
365:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * detection level.
366:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
367:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
368:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
369:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
128 .loc 1 369 0
129 .cfi_startproc
130 @ args = 0, pretend = 0, frame = 0
131 @ frame_needed = 0, uses_anonymous_args = 0
132 @ link register save eliminated.
133 .LVL0:
370:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */
371:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
372:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
373:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
374:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */
375:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
134 .loc 1 375 0
135 0000 1C4A ldr r2, .L15
136 0002 1368 ldr r3, [r2]
137 0004 E021 movs r1, #224
138 0006 8B43 bics r3, r1
139 0008 0168 ldr r1, [r0]
140 000a 0B43 orrs r3, r1
141 000c 1360 str r3, [r2]
376:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
377:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */
378:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
142 .loc 1 378 0
ARM GAS /tmp/ccnH7zer.s page 10
143 000e 1A4B ldr r3, .L15+4
144 0010 5968 ldr r1, [r3, #4]
145 0012 1A4A ldr r2, .L15+8
146 0014 1140 ands r1, r2
147 0016 5960 str r1, [r3, #4]
379:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT();
148 .loc 1 379 0
149 0018 1968 ldr r1, [r3]
150 001a 1140 ands r1, r2
151 001c 1960 str r1, [r3]
380:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
152 .loc 1 380 0
153 001e D968 ldr r1, [r3, #12]
154 0020 1140 ands r1, r2
155 0022 D960 str r1, [r3, #12]
381:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
156 .loc 1 381 0
157 0024 9968 ldr r1, [r3, #8]
158 0026 0A40 ands r2, r1
159 0028 9A60 str r2, [r3, #8]
382:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
383:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure interrupt mode */
384:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
160 .loc 1 384 0
161 002a 4368 ldr r3, [r0, #4]
162 002c DB03 lsls r3, r3, #15
163 002e 05D5 bpl .L11
385:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
386:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT();
164 .loc 1 386 0
165 0030 114A ldr r2, .L15+4
166 0032 1168 ldr r1, [r2]
167 0034 8023 movs r3, #128
168 0036 5B02 lsls r3, r3, #9
169 0038 0B43 orrs r3, r1
170 003a 1360 str r3, [r2]
171 .L11:
387:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
388:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
389:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure event mode */
390:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
172 .loc 1 390 0
173 003c 4368 ldr r3, [r0, #4]
174 003e 9B03 lsls r3, r3, #14
175 0040 05D5 bpl .L12
391:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
392:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
176 .loc 1 392 0
177 0042 0D4A ldr r2, .L15+4
178 0044 5168 ldr r1, [r2, #4]
179 0046 8023 movs r3, #128
180 0048 5B02 lsls r3, r3, #9
181 004a 0B43 orrs r3, r1
182 004c 5360 str r3, [r2, #4]
183 .L12:
393:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
394:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
ARM GAS /tmp/ccnH7zer.s page 11
395:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Configure the edge */
396:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
184 .loc 1 396 0
185 004e 4368 ldr r3, [r0, #4]
186 0050 DB07 lsls r3, r3, #31
187 0052 05D5 bpl .L13
397:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
398:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
188 .loc 1 398 0
189 0054 084A ldr r2, .L15+4
190 0056 9168 ldr r1, [r2, #8]
191 0058 8023 movs r3, #128
192 005a 5B02 lsls r3, r3, #9
193 005c 0B43 orrs r3, r1
194 005e 9360 str r3, [r2, #8]
195 .L13:
399:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
400:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
401:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
196 .loc 1 401 0
197 0060 4368 ldr r3, [r0, #4]
198 0062 9B07 lsls r3, r3, #30
199 0064 05D5 bpl .L10
402:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
403:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
200 .loc 1 403 0
201 0066 044A ldr r2, .L15+4
202 0068 D168 ldr r1, [r2, #12]
203 006a 8023 movs r3, #128
204 006c 5B02 lsls r3, r3, #9
205 006e 0B43 orrs r3, r1
206 0070 D360 str r3, [r2, #12]
207 .L10:
404:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
405:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
208 .loc 1 405 0
209 @ sp needed
210 0072 7047 bx lr
211 .L16:
212 .align 2
213 .L15:
214 0074 00700040 .word 1073770496
215 0078 00040140 .word 1073808384
216 007c FFFFFEFF .word -65537
217 .cfi_endproc
218 .LFE42:
220 .section .text.HAL_PWR_EnablePVD,"ax",%progbits
221 .align 1
222 .global HAL_PWR_EnablePVD
223 .syntax unified
224 .code 16
225 .thumb_func
226 .fpu softvfp
228 HAL_PWR_EnablePVD:
229 .LFB43:
406:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
407:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
ARM GAS /tmp/ccnH7zer.s page 12
408:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD).
409:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
410:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
411:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void)
412:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
230 .loc 1 412 0
231 .cfi_startproc
232 @ args = 0, pretend = 0, frame = 0
233 @ frame_needed = 0, uses_anonymous_args = 0
234 @ link register save eliminated.
413:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable the power voltage detector */
414:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PVDE);
235 .loc 1 414 0
236 0000 024A ldr r2, .L18
237 0002 1368 ldr r3, [r2]
238 0004 1021 movs r1, #16
239 0006 0B43 orrs r3, r1
240 0008 1360 str r3, [r2]
415:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
241 .loc 1 415 0
242 @ sp needed
243 000a 7047 bx lr
244 .L19:
245 .align 2
246 .L18:
247 000c 00700040 .word 1073770496
248 .cfi_endproc
249 .LFE43:
251 .section .text.HAL_PWR_DisablePVD,"ax",%progbits
252 .align 1
253 .global HAL_PWR_DisablePVD
254 .syntax unified
255 .code 16
256 .thumb_func
257 .fpu softvfp
259 HAL_PWR_DisablePVD:
260 .LFB44:
416:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
417:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
418:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD).
419:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
420:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
421:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void)
422:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
261 .loc 1 422 0
262 .cfi_startproc
263 @ args = 0, pretend = 0, frame = 0
264 @ frame_needed = 0, uses_anonymous_args = 0
265 @ link register save eliminated.
423:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable the power voltage detector */
424:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
266 .loc 1 424 0
267 0000 024A ldr r2, .L21
268 0002 1368 ldr r3, [r2]
269 0004 1021 movs r1, #16
270 0006 8B43 bics r3, r1
271 0008 1360 str r3, [r2]
ARM GAS /tmp/ccnH7zer.s page 13
425:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
272 .loc 1 425 0
273 @ sp needed
274 000a 7047 bx lr
275 .L22:
276 .align 2
277 .L21:
278 000c 00700040 .word 1073770496
279 .cfi_endproc
280 .LFE44:
282 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
283 .align 1
284 .global HAL_PWR_EnableWakeUpPin
285 .syntax unified
286 .code 16
287 .thumb_func
288 .fpu softvfp
290 HAL_PWR_EnableWakeUpPin:
291 .LFB45:
426:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
427:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
428:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
429:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
430:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
431:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1
432:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2
433:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
434:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
435:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
436:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
437:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
292 .loc 1 437 0
293 .cfi_startproc
294 @ args = 0, pretend = 0, frame = 0
295 @ frame_needed = 0, uses_anonymous_args = 0
296 @ link register save eliminated.
297 .LVL1:
438:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameter */
439:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
440:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Enable the EWUPx pin */
441:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
298 .loc 1 441 0
299 0000 024A ldr r2, .L24
300 0002 5368 ldr r3, [r2, #4]
301 0004 1843 orrs r0, r3
302 .LVL2:
303 0006 5060 str r0, [r2, #4]
442:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
304 .loc 1 442 0
305 @ sp needed
306 0008 7047 bx lr
307 .L25:
308 000a C046 .align 2
309 .L24:
310 000c 00700040 .word 1073770496
311 .cfi_endproc
312 .LFE45:
ARM GAS /tmp/ccnH7zer.s page 14
314 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
315 .align 1
316 .global HAL_PWR_DisableWakeUpPin
317 .syntax unified
318 .code 16
319 .thumb_func
320 .fpu softvfp
322 HAL_PWR_DisableWakeUpPin:
323 .LFB46:
443:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
444:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
445:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
446:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
447:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
448:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1
449:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2
450:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only.
451:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
452:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
453:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
454:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
324 .loc 1 454 0
325 .cfi_startproc
326 @ args = 0, pretend = 0, frame = 0
327 @ frame_needed = 0, uses_anonymous_args = 0
328 @ link register save eliminated.
329 .LVL3:
455:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameter */
456:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
457:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Disable the EWUPx pin */
458:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
330 .loc 1 458 0
331 0000 024A ldr r2, .L27
332 0002 5368 ldr r3, [r2, #4]
333 0004 8343 bics r3, r0
334 0006 5360 str r3, [r2, #4]
459:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
335 .loc 1 459 0
336 @ sp needed
337 0008 7047 bx lr
338 .L28:
339 000a C046 .align 2
340 .L27:
341 000c 00700040 .word 1073770496
342 .cfi_endproc
343 .LFE46:
345 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
346 .align 1
347 .global HAL_PWR_EnterSLEEPMode
348 .syntax unified
349 .code 16
350 .thumb_func
351 .fpu softvfp
353 HAL_PWR_EnterSLEEPMode:
354 .LFB47:
460:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
461:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
ARM GAS /tmp/ccnH7zer.s page 15
462:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Sleep mode.
463:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
464:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in SLEEP mode.
465:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
466:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
467:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
468:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
469:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
470:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * the interrupt wake up source.
471:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
472:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
473:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
474:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
475:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
476:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
477:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
355 .loc 1 477 0
356 .cfi_startproc
357 @ args = 0, pretend = 0, frame = 0
358 @ frame_needed = 0, uses_anonymous_args = 0
359 .LVL4:
360 0000 10B5 push {r4, lr}
361 .LCFI0:
362 .cfi_def_cfa_offset 8
363 .cfi_offset 4, -8
364 .cfi_offset 14, -4
365 .LVL5:
478:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** uint32_t tmpreg = 0U;
479:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */
480:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
481:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
482:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
483:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select the regulator state in Sleep mode ---------------------------------*/
484:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tmpreg = PWR->CR;
366 .loc 1 484 0
367 0002 094A ldr r2, .L33
368 0004 1368 ldr r3, [r2]
369 .LVL6:
485:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
486:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
487:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
370 .loc 1 487 0
371 0006 0324 movs r4, #3
372 0008 A343 bics r3, r4
373 .LVL7:
488:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
489:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set LPSDSR bit according to PWR_Regulator value */
490:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(tmpreg, Regulator);
374 .loc 1 490 0
375 000a 1843 orrs r0, r3
376 .LVL8:
491:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
492:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Store the new value */
493:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** PWR->CR = tmpreg;
377 .loc 1 493 0
378 000c 1060 str r0, [r2]
494:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
ARM GAS /tmp/ccnH7zer.s page 16
495:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
496:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
379 .loc 1 496 0
380 000e 074A ldr r2, .L33+4
381 0010 1369 ldr r3, [r2, #16]
382 0012 0420 movs r0, #4
383 .LVL9:
384 0014 8343 bics r3, r0
385 0016 1361 str r3, [r2, #16]
386 .LVL10:
497:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
498:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
499:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
387 .loc 1 499 0
388 0018 0129 cmp r1, #1
389 001a 03D0 beq .L32
390 .LBB20:
391 .LBB21:
392 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V4.30
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 20. October 2015
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
8:Drivers/CMSIS/Include/cmsis_gcc.h ****
9:Drivers/CMSIS/Include/cmsis_gcc.h **** All rights reserved.
10:Drivers/CMSIS/Include/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without
11:Drivers/CMSIS/Include/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met:
12:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright
13:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright
15:Drivers/CMSIS/Include/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the
16:Drivers/CMSIS/Include/cmsis_gcc.h **** documentation and/or other materials provided with the distribution.
17:Drivers/CMSIS/Include/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used
18:Drivers/CMSIS/Include/cmsis_gcc.h **** to endorse or promote products derived from this software without
19:Drivers/CMSIS/Include/cmsis_gcc.h **** specific prior written permission.
20:Drivers/CMSIS/Include/cmsis_gcc.h **** *
21:Drivers/CMSIS/Include/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22:Drivers/CMSIS/Include/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23:Drivers/CMSIS/Include/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24:Drivers/CMSIS/Include/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25:Drivers/CMSIS/Include/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26:Drivers/CMSIS/Include/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27:Drivers/CMSIS/Include/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28:Drivers/CMSIS/Include/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29:Drivers/CMSIS/Include/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30:Drivers/CMSIS/Include/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31:Drivers/CMSIS/Include/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE.
32:Drivers/CMSIS/Include/cmsis_gcc.h **** ---------------------------------------------------------------------------*/
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h ****
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
37:Drivers/CMSIS/Include/cmsis_gcc.h ****
38:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
ARM GAS /tmp/ccnH7zer.s page 17
39:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined ( __GNUC__ )
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
45:Drivers/CMSIS/Include/cmsis_gcc.h ****
46:Drivers/CMSIS/Include/cmsis_gcc.h ****
47:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
48:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
49:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
50:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
51:Drivers/CMSIS/Include/cmsis_gcc.h **** */
52:Drivers/CMSIS/Include/cmsis_gcc.h ****
53:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
54:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
55:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
56:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
57:Drivers/CMSIS/Include/cmsis_gcc.h **** */
58:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
59:Drivers/CMSIS/Include/cmsis_gcc.h **** {
60:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
61:Drivers/CMSIS/Include/cmsis_gcc.h **** }
62:Drivers/CMSIS/Include/cmsis_gcc.h ****
63:Drivers/CMSIS/Include/cmsis_gcc.h ****
64:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
65:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
66:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
67:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
68:Drivers/CMSIS/Include/cmsis_gcc.h **** */
69:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
70:Drivers/CMSIS/Include/cmsis_gcc.h **** {
71:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
72:Drivers/CMSIS/Include/cmsis_gcc.h **** }
73:Drivers/CMSIS/Include/cmsis_gcc.h ****
74:Drivers/CMSIS/Include/cmsis_gcc.h ****
75:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
76:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register
77:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register.
78:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value
79:Drivers/CMSIS/Include/cmsis_gcc.h **** */
80:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
81:Drivers/CMSIS/Include/cmsis_gcc.h **** {
82:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
83:Drivers/CMSIS/Include/cmsis_gcc.h ****
84:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
85:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
86:Drivers/CMSIS/Include/cmsis_gcc.h **** }
87:Drivers/CMSIS/Include/cmsis_gcc.h ****
88:Drivers/CMSIS/Include/cmsis_gcc.h ****
89:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
90:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register
91:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register.
92:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set
93:Drivers/CMSIS/Include/cmsis_gcc.h **** */
94:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
95:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccnH7zer.s page 18
96:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
97:Drivers/CMSIS/Include/cmsis_gcc.h **** }
98:Drivers/CMSIS/Include/cmsis_gcc.h ****
99:Drivers/CMSIS/Include/cmsis_gcc.h ****
100:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
101:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register
102:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
103:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value
104:Drivers/CMSIS/Include/cmsis_gcc.h **** */
105:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
106:Drivers/CMSIS/Include/cmsis_gcc.h **** {
107:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
108:Drivers/CMSIS/Include/cmsis_gcc.h ****
109:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
110:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
111:Drivers/CMSIS/Include/cmsis_gcc.h **** }
112:Drivers/CMSIS/Include/cmsis_gcc.h ****
113:Drivers/CMSIS/Include/cmsis_gcc.h ****
114:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
115:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register
116:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register.
117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value
118:Drivers/CMSIS/Include/cmsis_gcc.h **** */
119:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
120:Drivers/CMSIS/Include/cmsis_gcc.h **** {
121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
122:Drivers/CMSIS/Include/cmsis_gcc.h ****
123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
125:Drivers/CMSIS/Include/cmsis_gcc.h **** }
126:Drivers/CMSIS/Include/cmsis_gcc.h ****
127:Drivers/CMSIS/Include/cmsis_gcc.h ****
128:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
129:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register
130:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
131:Drivers/CMSIS/Include/cmsis_gcc.h ****
132:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
133:Drivers/CMSIS/Include/cmsis_gcc.h **** */
134:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
135:Drivers/CMSIS/Include/cmsis_gcc.h **** {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
137:Drivers/CMSIS/Include/cmsis_gcc.h ****
138:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
139:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
140:Drivers/CMSIS/Include/cmsis_gcc.h **** }
141:Drivers/CMSIS/Include/cmsis_gcc.h ****
142:Drivers/CMSIS/Include/cmsis_gcc.h ****
143:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
144:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer
145:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
146:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value
147:Drivers/CMSIS/Include/cmsis_gcc.h **** */
148:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
149:Drivers/CMSIS/Include/cmsis_gcc.h **** {
150:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result;
151:Drivers/CMSIS/Include/cmsis_gcc.h ****
152:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
ARM GAS /tmp/ccnH7zer.s page 19
153:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h ****
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
158:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer
159:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
160:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
161:Drivers/CMSIS/Include/cmsis_gcc.h **** */
162:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
163:Drivers/CMSIS/Include/cmsis_gcc.h **** {
164:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
165:Drivers/CMSIS/Include/cmsis_gcc.h **** }
166:Drivers/CMSIS/Include/cmsis_gcc.h ****
167:Drivers/CMSIS/Include/cmsis_gcc.h ****
168:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
169:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer
170:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
171:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value
172:Drivers/CMSIS/Include/cmsis_gcc.h **** */
173:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
174:Drivers/CMSIS/Include/cmsis_gcc.h **** {
175:Drivers/CMSIS/Include/cmsis_gcc.h **** register uint32_t result;
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
178:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
179:Drivers/CMSIS/Include/cmsis_gcc.h **** }
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h ****
182:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
183:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer
184:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
185:Drivers/CMSIS/Include/cmsis_gcc.h ****
186:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
187:Drivers/CMSIS/Include/cmsis_gcc.h **** */
188:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
189:Drivers/CMSIS/Include/cmsis_gcc.h **** {
190:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
191:Drivers/CMSIS/Include/cmsis_gcc.h **** }
192:Drivers/CMSIS/Include/cmsis_gcc.h ****
193:Drivers/CMSIS/Include/cmsis_gcc.h ****
194:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
195:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask
196:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
197:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value
198:Drivers/CMSIS/Include/cmsis_gcc.h **** */
199:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
200:Drivers/CMSIS/Include/cmsis_gcc.h **** {
201:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
202:Drivers/CMSIS/Include/cmsis_gcc.h ****
203:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) );
204:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
205:Drivers/CMSIS/Include/cmsis_gcc.h **** }
206:Drivers/CMSIS/Include/cmsis_gcc.h ****
207:Drivers/CMSIS/Include/cmsis_gcc.h ****
208:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
209:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask
ARM GAS /tmp/ccnH7zer.s page 20
210:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
211:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask
212:Drivers/CMSIS/Include/cmsis_gcc.h **** */
213:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
214:Drivers/CMSIS/Include/cmsis_gcc.h **** {
215:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
216:Drivers/CMSIS/Include/cmsis_gcc.h **** }
217:Drivers/CMSIS/Include/cmsis_gcc.h ****
218:Drivers/CMSIS/Include/cmsis_gcc.h ****
219:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U)
220:Drivers/CMSIS/Include/cmsis_gcc.h ****
221:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
222:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ
223:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
224:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
225:Drivers/CMSIS/Include/cmsis_gcc.h **** */
226:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
227:Drivers/CMSIS/Include/cmsis_gcc.h **** {
228:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
229:Drivers/CMSIS/Include/cmsis_gcc.h **** }
230:Drivers/CMSIS/Include/cmsis_gcc.h ****
231:Drivers/CMSIS/Include/cmsis_gcc.h ****
232:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
233:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ
234:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
235:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
236:Drivers/CMSIS/Include/cmsis_gcc.h **** */
237:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
238:Drivers/CMSIS/Include/cmsis_gcc.h **** {
239:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
240:Drivers/CMSIS/Include/cmsis_gcc.h **** }
241:Drivers/CMSIS/Include/cmsis_gcc.h ****
242:Drivers/CMSIS/Include/cmsis_gcc.h ****
243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority
245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
246:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
247:Drivers/CMSIS/Include/cmsis_gcc.h **** */
248:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
250:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
251:Drivers/CMSIS/Include/cmsis_gcc.h ****
252:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
253:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
254:Drivers/CMSIS/Include/cmsis_gcc.h **** }
255:Drivers/CMSIS/Include/cmsis_gcc.h ****
256:Drivers/CMSIS/Include/cmsis_gcc.h ****
257:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority
259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
260:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
261:Drivers/CMSIS/Include/cmsis_gcc.h **** */
262:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
263:Drivers/CMSIS/Include/cmsis_gcc.h **** {
264:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
265:Drivers/CMSIS/Include/cmsis_gcc.h **** }
266:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccnH7zer.s page 21
267:Drivers/CMSIS/Include/cmsis_gcc.h ****
268:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
269:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition
270:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
271:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
272:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
273:Drivers/CMSIS/Include/cmsis_gcc.h **** */
274:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
275:Drivers/CMSIS/Include/cmsis_gcc.h **** {
276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
277:Drivers/CMSIS/Include/cmsis_gcc.h **** }
278:Drivers/CMSIS/Include/cmsis_gcc.h ****
279:Drivers/CMSIS/Include/cmsis_gcc.h ****
280:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
281:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask
282:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
283:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value
284:Drivers/CMSIS/Include/cmsis_gcc.h **** */
285:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
286:Drivers/CMSIS/Include/cmsis_gcc.h **** {
287:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
288:Drivers/CMSIS/Include/cmsis_gcc.h ****
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
290:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
291:Drivers/CMSIS/Include/cmsis_gcc.h **** }
292:Drivers/CMSIS/Include/cmsis_gcc.h ****
293:Drivers/CMSIS/Include/cmsis_gcc.h ****
294:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
295:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask
296:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
297:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
298:Drivers/CMSIS/Include/cmsis_gcc.h **** */
299:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
300:Drivers/CMSIS/Include/cmsis_gcc.h **** {
301:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
302:Drivers/CMSIS/Include/cmsis_gcc.h **** }
303:Drivers/CMSIS/Include/cmsis_gcc.h ****
304:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */
305:Drivers/CMSIS/Include/cmsis_gcc.h ****
306:Drivers/CMSIS/Include/cmsis_gcc.h ****
307:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
308:Drivers/CMSIS/Include/cmsis_gcc.h ****
309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR
311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value
313:Drivers/CMSIS/Include/cmsis_gcc.h **** */
314:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
316:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
317:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
318:Drivers/CMSIS/Include/cmsis_gcc.h ****
319:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
321:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
322:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
323:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
ARM GAS /tmp/ccnH7zer.s page 22
324:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
325:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0);
326:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
327:Drivers/CMSIS/Include/cmsis_gcc.h **** }
328:Drivers/CMSIS/Include/cmsis_gcc.h ****
329:Drivers/CMSIS/Include/cmsis_gcc.h ****
330:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
331:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR
332:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
333:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
334:Drivers/CMSIS/Include/cmsis_gcc.h **** */
335:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
336:Drivers/CMSIS/Include/cmsis_gcc.h **** {
337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
338:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
339:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
340:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
341:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("");
342:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
343:Drivers/CMSIS/Include/cmsis_gcc.h **** }
344:Drivers/CMSIS/Include/cmsis_gcc.h ****
345:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
346:Drivers/CMSIS/Include/cmsis_gcc.h ****
347:Drivers/CMSIS/Include/cmsis_gcc.h ****
348:Drivers/CMSIS/Include/cmsis_gcc.h ****
349:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
350:Drivers/CMSIS/Include/cmsis_gcc.h ****
351:Drivers/CMSIS/Include/cmsis_gcc.h ****
352:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
353:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
354:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions
355:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
356:Drivers/CMSIS/Include/cmsis_gcc.h **** */
357:Drivers/CMSIS/Include/cmsis_gcc.h ****
358:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
359:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
360:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
361:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
362:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
363:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
364:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
365:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
366:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
367:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
368:Drivers/CMSIS/Include/cmsis_gcc.h ****
369:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
370:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation
371:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
372:Drivers/CMSIS/Include/cmsis_gcc.h **** */
373:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
374:Drivers/CMSIS/Include/cmsis_gcc.h **** {
375:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("nop");
376:Drivers/CMSIS/Include/cmsis_gcc.h **** }
377:Drivers/CMSIS/Include/cmsis_gcc.h ****
378:Drivers/CMSIS/Include/cmsis_gcc.h ****
379:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
380:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt
ARM GAS /tmp/ccnH7zer.s page 23
381:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
382:Drivers/CMSIS/Include/cmsis_gcc.h **** */
383:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
385:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfi");
386:Drivers/CMSIS/Include/cmsis_gcc.h **** }
387:Drivers/CMSIS/Include/cmsis_gcc.h ****
388:Drivers/CMSIS/Include/cmsis_gcc.h ****
389:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
390:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event
391:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
392:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
393:Drivers/CMSIS/Include/cmsis_gcc.h **** */
394:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
395:Drivers/CMSIS/Include/cmsis_gcc.h **** {
396:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("wfe");
397:Drivers/CMSIS/Include/cmsis_gcc.h **** }
398:Drivers/CMSIS/Include/cmsis_gcc.h ****
399:Drivers/CMSIS/Include/cmsis_gcc.h ****
400:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
401:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event
402:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
403:Drivers/CMSIS/Include/cmsis_gcc.h **** */
404:Drivers/CMSIS/Include/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
405:Drivers/CMSIS/Include/cmsis_gcc.h **** {
406:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("sev");
393 .loc 2 406 0
394 .syntax divided
395 @ 406 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
396 001c 40BF sev
397 @ 0 "" 2
398 .thumb
399 .syntax unified
400 .LBE21:
401 .LBE20:
402 .LBB22:
403 .LBB23:
396:Drivers/CMSIS/Include/cmsis_gcc.h **** }
404 .loc 2 396 0
405 .syntax divided
406 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
407 001e 20BF wfe
408 @ 0 "" 2
409 .thumb
410 .syntax unified
411 .LBE23:
412 .LBE22:
413 .LBB24:
414 .LBB25:
415 .syntax divided
416 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
417 0020 20BF wfe
418 @ 0 "" 2
419 .thumb
420 .syntax unified
421 .L29:
422 .LBE25:
ARM GAS /tmp/ccnH7zer.s page 24
423 .LBE24:
500:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
501:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */
502:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI();
503:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
504:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** else
505:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
506:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Event */
507:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __SEV();
508:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE();
509:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE();
510:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
511:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
424 .loc 1 511 0
425 @ sp needed
426 0022 10BD pop {r4, pc}
427 .L32:
428 .LBB26:
429 .LBB27:
385:Drivers/CMSIS/Include/cmsis_gcc.h **** }
430 .loc 2 385 0
431 .syntax divided
432 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
433 0024 30BF wfi
434 @ 0 "" 2
435 .thumb
436 .syntax unified
437 0026 FCE7 b .L29
438 .L34:
439 .align 2
440 .L33:
441 0028 00700040 .word 1073770496
442 002c 00ED00E0 .word -536810240
443 .LBE27:
444 .LBE26:
445 .cfi_endproc
446 .LFE47:
448 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
449 .align 1
450 .global HAL_PWR_EnterSTOPMode
451 .syntax unified
452 .code 16
453 .thumb_func
454 .fpu softvfp
456 HAL_PWR_EnterSTOPMode:
457 .LFB48:
512:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
513:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
514:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Stop mode.
515:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
516:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
517:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * MSI or HSI16 RCoscillator is selected as system clock depending
518:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * the bit STOPWUCK in the RCC_CFGR register.
519:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
520:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
521:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
522:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * is higher although the startup time is reduced.
ARM GAS /tmp/ccnH7zer.s page 25
523:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Before entering in this function, it is important to ensure that the WUF
524:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * wakeup flag is cleared. To perform this action, it is possible to call the
525:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU)
526:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** *
527:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param Regulator: Specifies the regulator state in Stop mode.
528:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
529:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
530:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
531:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
532:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * This parameter can be one of the following values:
533:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
534:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
535:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
536:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
537:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
538:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
458 .loc 1 538 0
459 .cfi_startproc
460 @ args = 0, pretend = 0, frame = 0
461 @ frame_needed = 0, uses_anonymous_args = 0
462 .LVL11:
463 0000 10B5 push {r4, lr}
464 .LCFI1:
465 .cfi_def_cfa_offset 8
466 .cfi_offset 4, -8
467 .cfi_offset 14, -4
468 .LVL12:
539:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** uint32_t tmpreg = 0U;
540:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
541:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check the parameters */
542:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
543:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
544:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
545:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select the regulator state in Stop mode ---------------------------------*/
546:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** tmpreg = PWR->CR;
469 .loc 1 546 0
470 0002 0C4A ldr r2, .L39
471 0004 1368 ldr r3, [r2]
472 .LVL13:
547:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
548:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
549:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR));
473 .loc 1 549 0
474 0006 0324 movs r4, #3
475 0008 A343 bics r3, r4
476 .LVL14:
550:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
551:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set LPSDSR bit according to PWR_Regulator value */
552:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(tmpreg, Regulator);
477 .loc 1 552 0
478 000a 1843 orrs r0, r3
479 .LVL15:
553:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
554:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Store the new value */
555:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** PWR->CR = tmpreg;
480 .loc 1 555 0
481 000c 1060 str r0, [r2]
ARM GAS /tmp/ccnH7zer.s page 26
556:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
557:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
558:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
482 .loc 1 558 0
483 000e 0A4A ldr r2, .L39+4
484 0010 1369 ldr r3, [r2, #16]
485 0012 0420 movs r0, #4
486 .LVL16:
487 0014 0343 orrs r3, r0
488 0016 1361 str r3, [r2, #16]
489 .LVL17:
559:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
560:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/
561:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
490 .loc 1 561 0
491 0018 0129 cmp r1, #1
492 001a 08D0 beq .L38
493 .LBB28:
494 .LBB29:
495 .loc 2 406 0
496 .syntax divided
497 @ 406 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
498 001c 40BF sev
499 @ 0 "" 2
500 .thumb
501 .syntax unified
502 .LBE29:
503 .LBE28:
504 .LBB30:
505 .LBB31:
396:Drivers/CMSIS/Include/cmsis_gcc.h **** }
506 .loc 2 396 0
507 .syntax divided
508 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
509 001e 20BF wfe
510 @ 0 "" 2
511 .thumb
512 .syntax unified
513 .LBE31:
514 .LBE30:
515 .LBB32:
516 .LBB33:
517 .syntax divided
518 @ 396 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
519 0020 20BF wfe
520 @ 0 "" 2
521 .thumb
522 .syntax unified
523 .L37:
524 .LBE33:
525 .LBE32:
562:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
563:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */
564:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI();
565:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
566:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** else
567:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
ARM GAS /tmp/ccnH7zer.s page 27
568:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Event */
569:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __SEV();
570:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE();
571:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFE();
572:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
573:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
574:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
575:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
526 .loc 1 575 0
527 0022 054A ldr r2, .L39+4
528 0024 1369 ldr r3, [r2, #16]
529 0026 0421 movs r1, #4
530 .LVL18:
531 0028 8B43 bics r3, r1
532 002a 1361 str r3, [r2, #16]
576:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
577:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
533 .loc 1 577 0
534 @ sp needed
535 002c 10BD pop {r4, pc}
536 .LVL19:
537 .L38:
538 .LBB34:
539 .LBB35:
385:Drivers/CMSIS/Include/cmsis_gcc.h **** }
540 .loc 2 385 0
541 .syntax divided
542 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
543 002e 30BF wfi
544 @ 0 "" 2
545 .thumb
546 .syntax unified
547 0030 F7E7 b .L37
548 .L40:
549 0032 C046 .align 2
550 .L39:
551 0034 00700040 .word 1073770496
552 0038 00ED00E0 .word -536810240
553 .LBE35:
554 .LBE34:
555 .cfi_endproc
556 .LFE48:
558 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
559 .align 1
560 .global HAL_PWR_EnterSTANDBYMode
561 .syntax unified
562 .code 16
563 .thumb_func
564 .fpu softvfp
566 HAL_PWR_EnterSTANDBYMode:
567 .LFB49:
578:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
579:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
580:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enters Standby mode.
581:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
582:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - Reset pad (still available)
583:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
ARM GAS /tmp/ccnH7zer.s page 28
584:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out.
585:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - RTC_AF2 pin (PC13) if configured for tamper.
586:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 1 (PA00) if enabled.
587:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 2 (PC13) if enabled.
588:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only.
589:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only.
590:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
591:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
592:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
593:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
568 .loc 1 593 0
569 .cfi_startproc
570 @ args = 0, pretend = 0, frame = 0
571 @ frame_needed = 0, uses_anonymous_args = 0
572 @ link register save eliminated.
594:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Select Standby mode */
595:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS);
573 .loc 1 595 0
574 0000 054A ldr r2, .L42
575 0002 1368 ldr r3, [r2]
576 0004 0221 movs r1, #2
577 0006 0B43 orrs r3, r1
578 0008 1360 str r3, [r2]
596:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
597:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
598:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
579 .loc 1 598 0
580 000a 044A ldr r2, .L42+4
581 000c 1369 ldr r3, [r2, #16]
582 000e 0231 adds r1, r1, #2
583 0010 0B43 orrs r3, r1
584 0012 1361 str r3, [r2, #16]
585 .LBB36:
586 .LBB37:
385:Drivers/CMSIS/Include/cmsis_gcc.h **** }
587 .loc 2 385 0
588 .syntax divided
589 @ 385 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
590 0014 30BF wfi
591 @ 0 "" 2
592 .thumb
593 .syntax unified
594 .LBE37:
595 .LBE36:
599:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
600:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
601:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #if defined ( __CC_ARM)
602:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __force_stores();
603:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** #endif
604:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Request Wait For Interrupt */
605:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __WFI();
606:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
596 .loc 1 606 0
597 @ sp needed
598 0016 7047 bx lr
599 .L43:
600 .align 2
ARM GAS /tmp/ccnH7zer.s page 29
601 .L42:
602 0018 00700040 .word 1073770496
603 001c 00ED00E0 .word -536810240
604 .cfi_endproc
605 .LFE49:
607 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
608 .align 1
609 .global HAL_PWR_EnableSleepOnExit
610 .syntax unified
611 .code 16
612 .thumb_func
613 .fpu softvfp
615 HAL_PWR_EnableSleepOnExit:
616 .LFB50:
607:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
608:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
609:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
610:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
611:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
612:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
613:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * interruptions handling.
614:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
615:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
616:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
617:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
617 .loc 1 617 0
618 .cfi_startproc
619 @ args = 0, pretend = 0, frame = 0
620 @ frame_needed = 0, uses_anonymous_args = 0
621 @ link register save eliminated.
618:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
619:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
622 .loc 1 619 0
623 0000 024A ldr r2, .L45
624 0002 1369 ldr r3, [r2, #16]
625 0004 0221 movs r1, #2
626 0006 0B43 orrs r3, r1
627 0008 1361 str r3, [r2, #16]
620:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
628 .loc 1 620 0
629 @ sp needed
630 000a 7047 bx lr
631 .L46:
632 .align 2
633 .L45:
634 000c 00ED00E0 .word -536810240
635 .cfi_endproc
636 .LFE50:
638 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
639 .align 1
640 .global HAL_PWR_DisableSleepOnExit
641 .syntax unified
642 .code 16
643 .thumb_func
644 .fpu softvfp
646 HAL_PWR_DisableSleepOnExit:
647 .LFB51:
ARM GAS /tmp/ccnH7zer.s page 30
621:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
622:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
623:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
624:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
625:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
626:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
627:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
628:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
629:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
630:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
648 .loc 1 630 0
649 .cfi_startproc
650 @ args = 0, pretend = 0, frame = 0
651 @ frame_needed = 0, uses_anonymous_args = 0
652 @ link register save eliminated.
631:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
632:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
653 .loc 1 632 0
654 0000 024A ldr r2, .L48
655 0002 1369 ldr r3, [r2, #16]
656 0004 0221 movs r1, #2
657 0006 8B43 bics r3, r1
658 0008 1361 str r3, [r2, #16]
633:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
659 .loc 1 633 0
660 @ sp needed
661 000a 7047 bx lr
662 .L49:
663 .align 2
664 .L48:
665 000c 00ED00E0 .word -536810240
666 .cfi_endproc
667 .LFE51:
669 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
670 .align 1
671 .global HAL_PWR_EnableSEVOnPend
672 .syntax unified
673 .code 16
674 .thumb_func
675 .fpu softvfp
677 HAL_PWR_EnableSEVOnPend:
678 .LFB52:
634:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
635:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
636:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
637:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Enables CORTEX M0+ SEVONPEND bit.
638:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
639:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
640:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
641:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
642:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
643:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
679 .loc 1 643 0
680 .cfi_startproc
681 @ args = 0, pretend = 0, frame = 0
682 @ frame_needed = 0, uses_anonymous_args = 0
683 @ link register save eliminated.
ARM GAS /tmp/ccnH7zer.s page 31
644:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
645:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
684 .loc 1 645 0
685 0000 024A ldr r2, .L51
686 0002 1369 ldr r3, [r2, #16]
687 0004 1021 movs r1, #16
688 0006 0B43 orrs r3, r1
689 0008 1361 str r3, [r2, #16]
646:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
690 .loc 1 646 0
691 @ sp needed
692 000a 7047 bx lr
693 .L52:
694 .align 2
695 .L51:
696 000c 00ED00E0 .word -536810240
697 .cfi_endproc
698 .LFE52:
700 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
701 .align 1
702 .global HAL_PWR_DisableSEVOnPend
703 .syntax unified
704 .code 16
705 .thumb_func
706 .fpu softvfp
708 HAL_PWR_DisableSEVOnPend:
709 .LFB53:
647:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
648:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
649:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
650:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief Disables CORTEX M0+ SEVONPEND bit.
651:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
652:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
653:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
654:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
655:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
656:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
710 .loc 1 656 0
711 .cfi_startproc
712 @ args = 0, pretend = 0, frame = 0
713 @ frame_needed = 0, uses_anonymous_args = 0
714 @ link register save eliminated.
657:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
658:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
715 .loc 1 658 0
716 0000 024A ldr r2, .L54
717 0002 1369 ldr r3, [r2, #16]
718 0004 1021 movs r1, #16
719 0006 8B43 bics r3, r1
720 0008 1361 str r3, [r2, #16]
659:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
721 .loc 1 659 0
722 @ sp needed
723 000a 7047 bx lr
724 .L55:
725 .align 2
726 .L54:
ARM GAS /tmp/ccnH7zer.s page 32
727 000c 00ED00E0 .word -536810240
728 .cfi_endproc
729 .LFE53:
731 .section .text.HAL_PWR_PVDCallback,"ax",%progbits
732 .align 1
733 .weak HAL_PWR_PVDCallback
734 .syntax unified
735 .code 16
736 .thumb_func
737 .fpu softvfp
739 HAL_PWR_PVDCallback:
740 .LFB55:
660:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
661:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
662:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request.
663:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler().
664:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
665:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
666:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void)
667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
668:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check PWR exti flag */
669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
670:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
671:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* PWR PVD interrupt user callback */
672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** HAL_PWR_PVDCallback();
673:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
674:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Clear PWR Exti pending bit */
675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
676:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
678:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
679:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /**
680:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @brief PWR PVD interrupt callback
681:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** * @retval None
682:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
683:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void)
684:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
741 .loc 1 684 0
742 .cfi_startproc
743 @ args = 0, pretend = 0, frame = 0
744 @ frame_needed = 0, uses_anonymous_args = 0
745 @ link register save eliminated.
685:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed,
686:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file
687:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** */
688:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
746 .loc 1 688 0
747 @ sp needed
748 0000 7047 bx lr
749 .cfi_endproc
750 .LFE55:
752 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits
753 .align 1
754 .global HAL_PWR_PVD_IRQHandler
755 .syntax unified
756 .code 16
757 .thumb_func
ARM GAS /tmp/ccnH7zer.s page 33
758 .fpu softvfp
760 HAL_PWR_PVD_IRQHandler:
761 .LFB54:
667:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** /* Check PWR exti flag */
762 .loc 1 667 0
763 .cfi_startproc
764 @ args = 0, pretend = 0, frame = 0
765 @ frame_needed = 0, uses_anonymous_args = 0
766 0000 10B5 push {r4, lr}
767 .LCFI2:
768 .cfi_def_cfa_offset 8
769 .cfi_offset 4, -8
770 .cfi_offset 14, -4
669:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** {
771 .loc 1 669 0
772 0002 064B ldr r3, .L60
773 0004 5B69 ldr r3, [r3, #20]
774 0006 DB03 lsls r3, r3, #15
775 0008 00D4 bmi .L59
776 .L57:
677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
777 .loc 1 677 0
778 @ sp needed
779 000a 10BD pop {r4, pc}
780 .L59:
672:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
781 .loc 1 672 0
782 000c FFF7FEFF bl HAL_PWR_PVDCallback
783 .LVL20:
675:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c **** }
784 .loc 1 675 0
785 0010 024B ldr r3, .L60
786 0012 8022 movs r2, #128
787 0014 5202 lsls r2, r2, #9
788 0016 5A61 str r2, [r3, #20]
677:./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c ****
789 .loc 1 677 0
790 0018 F7E7 b .L57
791 .L61:
792 001a C046 .align 2
793 .L60:
794 001c 00040140 .word 1073808384
795 .cfi_endproc
796 .LFE54:
798 .text
799 .Letext0:
800 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h"
801 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h"
802 .file 5 "Drivers/CMSIS/Include/core_cm0plus.h"
803 .file 6 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h"
804 .file 7 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h"
805 .file 8 "/usr/arm-none-eabi/include/sys/lock.h"
806 .file 9 "/usr/arm-none-eabi/include/sys/_types.h"
807 .file 10 "/usr/lib/gcc/arm-none-eabi/7.2.0/include/stddef.h"
808 .file 11 "/usr/arm-none-eabi/include/sys/reent.h"
809 .file 12 "Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h"
810 .file 13 "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h"
ARM GAS /tmp/ccnH7zer.s page 34
ARM GAS /tmp/ccnH7zer.s page 35
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32l0xx_hal_pwr.c
/tmp/ccnH7zer.s:16 .text.HAL_PWR_DeInit:0000000000000000 $t
/tmp/ccnH7zer.s:23 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
/tmp/ccnH7zer.s:49 .text.HAL_PWR_DeInit:0000000000000018 $d
/tmp/ccnH7zer.s:55 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
/tmp/ccnH7zer.s:62 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
/tmp/ccnH7zer.s:82 .text.HAL_PWR_EnableBkUpAccess:0000000000000010 $d
/tmp/ccnH7zer.s:87 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
/tmp/ccnH7zer.s:94 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
/tmp/ccnH7zer.s:113 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d
/tmp/ccnH7zer.s:119 .text.HAL_PWR_ConfigPVD:0000000000000000 $t
/tmp/ccnH7zer.s:126 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD
/tmp/ccnH7zer.s:214 .text.HAL_PWR_ConfigPVD:0000000000000074 $d
/tmp/ccnH7zer.s:221 .text.HAL_PWR_EnablePVD:0000000000000000 $t
/tmp/ccnH7zer.s:228 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD
/tmp/ccnH7zer.s:247 .text.HAL_PWR_EnablePVD:000000000000000c $d
/tmp/ccnH7zer.s:252 .text.HAL_PWR_DisablePVD:0000000000000000 $t
/tmp/ccnH7zer.s:259 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD
/tmp/ccnH7zer.s:278 .text.HAL_PWR_DisablePVD:000000000000000c $d
/tmp/ccnH7zer.s:283 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
/tmp/ccnH7zer.s:290 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
/tmp/ccnH7zer.s:310 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d
/tmp/ccnH7zer.s:315 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
/tmp/ccnH7zer.s:322 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
/tmp/ccnH7zer.s:341 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d
/tmp/ccnH7zer.s:346 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
/tmp/ccnH7zer.s:353 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
/tmp/ccnH7zer.s:441 .text.HAL_PWR_EnterSLEEPMode:0000000000000028 $d
/tmp/ccnH7zer.s:449 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
/tmp/ccnH7zer.s:456 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
/tmp/ccnH7zer.s:551 .text.HAL_PWR_EnterSTOPMode:0000000000000034 $d
/tmp/ccnH7zer.s:559 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
/tmp/ccnH7zer.s:566 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
/tmp/ccnH7zer.s:602 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d
/tmp/ccnH7zer.s:608 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
/tmp/ccnH7zer.s:615 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
/tmp/ccnH7zer.s:634 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
/tmp/ccnH7zer.s:639 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
/tmp/ccnH7zer.s:646 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
/tmp/ccnH7zer.s:665 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
/tmp/ccnH7zer.s:670 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
/tmp/ccnH7zer.s:677 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
/tmp/ccnH7zer.s:696 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
/tmp/ccnH7zer.s:701 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
/tmp/ccnH7zer.s:708 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
/tmp/ccnH7zer.s:727 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d
/tmp/ccnH7zer.s:732 .text.HAL_PWR_PVDCallback:0000000000000000 $t
/tmp/ccnH7zer.s:739 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback
/tmp/ccnH7zer.s:753 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t
/tmp/ccnH7zer.s:760 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler
/tmp/ccnH7zer.s:794 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d
.debug_frame:0000000000000010 $d
NO UNDEFINED SYMBOLS