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307 lines
8.3 KiB
307 lines
8.3 KiB
/**
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******************************************************************************
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* @file stm32f10x_pwr.c
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @brief This file provides all the PWR firmware functions.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_pwr.h"
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#include "stm32f10x_rcc.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @defgroup PWR
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* @brief PWR driver modules
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* @{
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*/
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/** @defgroup PWR_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Defines
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* @{
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*/
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/* --------- PWR registers bit address in the alias region ---------- */
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#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of DBP bit */
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#define CR_OFFSET (PWR_OFFSET + 0x00)
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#define DBP_BitNumber 0x08
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#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
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/* Alias word address of PVDE bit */
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#define PVDE_BitNumber 0x04
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#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of EWUP bit */
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#define CSR_OFFSET (PWR_OFFSET + 0x04)
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#define EWUP_BitNumber 0x08
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#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
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/* ------------------ PWR registers bit mask ------------------------ */
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/* CR register bit mask */
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#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
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#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the PWR peripheral registers to their default reset values.
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* @param None
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* @retval None
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*/
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void PWR_DeInit(void)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
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}
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/**
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* @brief Enables or disables access to the RTC and backup registers.
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* @param NewState: new state of the access to the RTC and backup registers.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_BackupAccessCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Power Voltage Detector(PVD).
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* @param NewState: new state of the PVD.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_PVDCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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* @param PWR_PVDLevel: specifies the PVD detection level
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* This parameter can be one of the following values:
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* @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
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* @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
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* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
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* @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
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* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
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* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
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* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
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* @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
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* @retval None
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*/
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void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
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tmpreg = PWR->CR;
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/* Clear PLS[7:5] bits */
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tmpreg &= CR_PLS_MASK;
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/* Set PLS[7:5] bits according to PWR_PVDLevel value */
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tmpreg |= PWR_PVDLevel;
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/* Store the new value */
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PWR->CR = tmpreg;
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}
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/**
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* @brief Enables or disables the WakeUp Pin functionality.
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* @param NewState: new state of the WakeUp Pin functionality.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_WakeUpPinCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enters STOP mode.
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* @param PWR_Regulator: specifies the regulator state in STOP mode.
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* This parameter can be one of the following values:
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* @arg PWR_Regulator_ON: STOP mode with regulator ON
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* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
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* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
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* This parameter can be one of the following values:
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* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
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* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
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* @retval None
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*/
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void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_PWR_REGULATOR(PWR_Regulator));
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assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
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/* Select the regulator state in STOP mode ---------------------------------*/
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tmpreg = PWR->CR;
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/* Clear PDDS and LPDS bits */
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tmpreg &= CR_DS_MASK;
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/* Set LPDS bit according to PWR_Regulator value */
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tmpreg |= PWR_Regulator;
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/* Store the new value */
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PWR->CR = tmpreg;
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP;
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/* Select STOP mode entry --------------------------------------------------*/
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if(PWR_STOPEntry == PWR_STOPEntry_WFI)
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{
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/* Request Wait For Interrupt */
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__WFI();
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}
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else
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{
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/* Request Wait For Event */
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__WFE();
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}
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/* Reset SLEEPDEEP bit of Cortex System Control Register */
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SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
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}
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/**
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* @brief Enters STANDBY mode.
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* @param None
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* @retval None
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*/
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void PWR_EnterSTANDBYMode(void)
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{
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/* Clear Wake-up flag */
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PWR->CR |= PWR_CR_CWUF;
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/* Select STANDBY mode */
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PWR->CR |= PWR_CR_PDDS;
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP;
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/* This option is used to ensure that store operations are completed */
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#if defined ( __CC_ARM )
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__force_stores();
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#endif
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/* Request Wait For Interrupt */
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__WFI();
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}
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/**
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* @brief Checks whether the specified PWR flag is set or not.
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* @param PWR_FLAG: specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_WU: Wake Up flag
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* @arg PWR_FLAG_SB: StandBy flag
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* @arg PWR_FLAG_PVDO: PVD Output
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* @retval The new state of PWR_FLAG (SET or RESET).
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*/
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FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
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{
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FlagStatus bitstatus = RESET;
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/* Check the parameters */
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assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
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if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
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{
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bitstatus = SET;
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}
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else
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{
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bitstatus = RESET;
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}
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/* Return the flag status */
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return bitstatus;
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}
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/**
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* @brief Clears the PWR's pending flags.
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* @param PWR_FLAG: specifies the flag to clear.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_WU: Wake Up flag
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* @arg PWR_FLAG_SB: StandBy flag
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* @retval None
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*/
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void PWR_ClearFlag(uint32_t PWR_FLAG)
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{
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/* Check the parameters */
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assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
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PWR->CR |= PWR_FLAG << 2;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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