commit
11764cbd7a
@ -0,0 +1,17 @@ |
||||
*~ |
||||
*.o |
||||
*.d |
||||
*.bin |
||||
*.elf |
||||
*.axf |
||||
*.hex |
||||
*.srec |
||||
*.list |
||||
*.map |
||||
*.a |
||||
*.stylecheck |
||||
nbproject |
||||
|
||||
*.dis |
||||
|
||||
/lib/stm32f30x_dsp_stdperiph_lib_um.chm |
||||
@ -0,0 +1,3 @@ |
||||
[submodule "lib/sbmp"] |
||||
path = lib/sbmp |
||||
url = git@github.com:MightyPork/sbmp.git |
||||
@ -0,0 +1,205 @@ |
||||
################################################################
|
||||
|
||||
ARCH_FLAGS = -msoft-float -mfloat-abi=soft
|
||||
ARCH_FLAGS += -mthumb -mcpu=cortex-m3
|
||||
|
||||
# Clock speed constants
|
||||
DEFS += -DF_CPU=8000000UL
|
||||
|
||||
DEFS += -DSTM32F10X_MD
|
||||
DEFS += -DARM_MATH_CM3
|
||||
DEFS += -DUSE_STDPERIPH_DRIVER
|
||||
|
||||
LDSCRIPT = lib/cmsis/stm32_flash.ld
|
||||
STARTUP_SCRIPT = lib/cmsis/startup_stm32f10x_md.s
|
||||
|
||||
|
||||
################################################################
|
||||
|
||||
# Main file
|
||||
BINARY = main
|
||||
|
||||
# Project include dirs
|
||||
INCL_DIRS := project
|
||||
|
||||
# C files
|
||||
SOURCES := $(shell find project -type f -name "*.c")
|
||||
#SOURCES += $(shell find lib/sbmp/library -type f -name "*.c")
|
||||
|
||||
HEADERS := $(shell find project -type f -name "*.h")
|
||||
#HEADERS += $(shell find lib/sbmp/library -type f -name "*.h")
|
||||
|
||||
#INCL_DIRS += lib/sbmp/library
|
||||
|
||||
################################################################
|
||||
|
||||
# Add library sources and include paths
|
||||
LIB_INCL_DIRS =
|
||||
LIB_SOURCES =
|
||||
include lib/CMSIS.mk |
||||
include lib/SPL.mk |
||||
include lib/SBMP.mk |
||||
|
||||
INCL_DIRS += $(LIB_INCL_DIRS)
|
||||
|
||||
LIB_OBJS_ = $(LIB_SOURCES:.c=.o)
|
||||
LIB_OBJS = $(LIB_OBJS_:.S=.o)
|
||||
|
||||
# .c -> .o
|
||||
|
||||
OBJS = $(SOURCES:%.c=%.o)
|
||||
OBJS += $(STARTUP_SCRIPT:.s=.o)
|
||||
|
||||
LIBNAME = stm32f103spl
|
||||
LIBFILE = lib/lib$(LIBNAME).a
|
||||
|
||||
|
||||
################################################################
|
||||
|
||||
SUBDIR_ROOTS = .
|
||||
GARBAGE_PATTERNS := *.o *.d *.elf *.bin *.hex *.srec *.list *.map *.dis *.disasm .depend
|
||||
|
||||
DIRS := . $(shell find $(SUBDIR_ROOTS) -type d)
|
||||
GARBAGE := $(foreach DIR,$(DIRS),$(addprefix $(DIR)/,$(GARBAGE_PATTERNS)))
|
||||
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
|
||||
# Be silent per default, but 'make V=1' will show all compiler calls.
|
||||
ifneq ($(V),1) |
||||
Q := @
|
||||
NULL := 2>/dev/null
|
||||
endif |
||||
|
||||
###############################################################################
|
||||
# Executables
|
||||
|
||||
PREFIX ?= arm-none-eabi
|
||||
|
||||
CC := $(PREFIX)-gcc
|
||||
CXX := $(PREFIX)-g++
|
||||
LD := $(PREFIX)-gcc
|
||||
AR := $(PREFIX)-ar
|
||||
AS := $(PREFIX)-as
|
||||
OBJCOPY := $(PREFIX)-objcopy
|
||||
SIZE := $(PREFIX)-size
|
||||
OBJDUMP := $(PREFIX)-objdump
|
||||
GDB := $(PREFIX)-gdb
|
||||
STFLASH := $(shell which st-flash)
|
||||
|
||||
###############################################################################
|
||||
|
||||
# For CMSIS compatibility
|
||||
DEFS += -D__weak="__attribute__((weak))" -D__packed="__attribute__((__packed__))"
|
||||
DEFS += -DVERBOSE_LOGGING=1
|
||||
|
||||
###############################################################################
|
||||
# C flags
|
||||
|
||||
CFLAGS += -Os -ggdb -std=gnu99 -Wfatal-errors
|
||||
CFLAGS += -Wall -Wextra -Wshadow
|
||||
CFLAGS += -Wwrite-strings -Wold-style-definition -Winline -Wmissing-noreturn -Wstrict-prototypes
|
||||
CFLAGS += -Wredundant-decls -Wfloat-equal -Wsign-compare
|
||||
CFLAGS += -fno-common -ffunction-sections -fdata-sections -Wunused-function
|
||||
CFLAGS += -MD -Wno-format-zero-length
|
||||
CFLAGS += $(INCL_DIRS:%=-I%) $(DEFS)
|
||||
#-flto
|
||||
|
||||
# Special flags to hide warnings in CMSIS
|
||||
LIB_CFLAGS = -Wno-shadow -Wno-float-equal -Wno-inline -Wno-unused-parameter -Wno-unused
|
||||
#-Wno-old-style-definition -Wno-strict-prototypes
|
||||
|
||||
###############################################################################
|
||||
# Linker flags
|
||||
|
||||
LDFLAGS += --static -lm -lc -nostartfiles
|
||||
LDFLAGS += -Llib
|
||||
LDFLAGS += -T$(LDSCRIPT)
|
||||
LDFLAGS += -Wl,-Map=$(*).map
|
||||
LDFLAGS += -Wl,--gc-sections
|
||||
#-specs=nano.specs
|
||||
|
||||
###############################################################################
|
||||
# Used libraries
|
||||
|
||||
LDLIBS += -lm -lc -l$(LIBNAME)
|
||||
LDLIBS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group
|
||||
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
|
||||
.PHONY: all images clean elf bin hex srec list dis ttyusb ttyacm lib libcheck size |
||||
|
||||
.SUFFIXES: .elf .bin .hex .srec .list .map .images |
||||
.SECONDEXPANSION: |
||||
.SECONDARY: |
||||
|
||||
all: elf size |
||||
|
||||
elf: $(BINARY).elf |
||||
bin: $(BINARY).bin |
||||
hex: $(BINARY).hex |
||||
srec: $(BINARY).srec |
||||
list: $(BINARY).list |
||||
|
||||
images: $(BINARY).images |
||||
flash: $(BINARY).flash |
||||
|
||||
dis: $(BINARY).elf |
||||
$(Q)$(OBJDUMP) -dS $(BINARY).elf -j .text -j .isr_vector > $(BINARY).dis
|
||||
|
||||
lib: CFLAGS += $(LIB_CFLAGS) |
||||
lib: $(LIBFILE) |
||||
|
||||
$(LIBFILE): $(LIB_OBJS) |
||||
$(Q)$(AR) rcsv $@ $(LIB_OBJS)
|
||||
|
||||
libcheck: |
||||
$(Q)if [ ! -e $(LIBFILE) ]; then \
|
||||
echo "--- You must build the lib first! ---"; \
|
||||
exit 1; \
|
||||
fi
|
||||
|
||||
size: $(BINARY).elf |
||||
$(Q)$(SIZE) -A $(BINARY).elf | grep -v " 0"
|
||||
|
||||
%.images: %.bin %.hex %.srec %.list %.map |
||||
|
||||
%.bin: %.elf |
||||
$(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin
|
||||
|
||||
%.hex: %.elf |
||||
$(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex
|
||||
|
||||
%.srec: %.elf |
||||
$(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec
|
||||
|
||||
%.list: %.elf |
||||
$(Q)$(OBJDUMP) -S $(*).elf > $(*).list
|
||||
|
||||
%.elf %.map: libcheck $(OBJS) $(HEADERS) |
||||
$(Q)$(LD) $(LDFLAGS) $(ARCH_FLAGS) $(OBJS) $(LDLIBS) -o $(*).elf
|
||||
$(Q)$(SIZE) $(*).elf
|
||||
|
||||
%.o: %.c |
||||
$(Q)echo "CC $(*).c"
|
||||
$(Q)$(CC) $(CFLAGS) $(ARCH_FLAGS) -o $(*).o -c $(*).c
|
||||
|
||||
%.o: %.s |
||||
$(Q)echo "CC $(*).s"
|
||||
$(Q)$(CC) $(CFLAGS) $(ARCH_FLAGS) -o $(*).o -c $(*).s
|
||||
|
||||
%.o: %.S |
||||
$(Q)echo "CC $(*).S"
|
||||
$(Q)$(CC) $(CFLAGS) $(ARCH_FLAGS) -o $(*).o -c $(*).S
|
||||
|
||||
clean: |
||||
$(Q)$(RM) -r $(GARBAGE)
|
||||
|
||||
%.flash: %.bin |
||||
@printf " FLASH $<\n"
|
||||
$(Q)$(STFLASH) write $(*).bin 0x8000000
|
||||
|
||||
-include $(OBJS:.o=.d) |
||||
@ -0,0 +1,107 @@ |
||||
TEMPLATE = app |
||||
CONFIG += console |
||||
CONFIG -= app_bundle |
||||
CONFIG -= qt |
||||
|
||||
INCLUDEPATH += \ |
||||
project \ |
||||
lib/spl/inc \ |
||||
lib/cmsis \ |
||||
lib/sbmp/library \ |
||||
/usr/arm-none-eabi/include \ |
||||
/usr/lib/gcc/arm-none-eabi/5.3.0/include/ |
||||
|
||||
DEFINES += F_CPU=8000000UL \ |
||||
STM32F10X_MD \ |
||||
USE_STDPERIPH_DRIVER \ |
||||
__null=0 \ |
||||
__STATIC_INLINE="static inline" \ |
||||
__INLINE="inline" \ |
||||
__ASM=__asm \ |
||||
__CORTEX_M=3 \ |
||||
VERBOSE_LOGGING=1 |
||||
|
||||
HEADERS += \ |
||||
lib/cmsis/core_cm3.h \ |
||||
lib/cmsis/stm32f10x.h \ |
||||
lib/sbmp/library/crc32.h \ |
||||
lib/sbmp/library/payload_builder.h \ |
||||
lib/sbmp/library/payload_parser.h \ |
||||
lib/sbmp/library/sbmp.h \ |
||||
lib/sbmp/library/sbmp_bulk.h \ |
||||
lib/sbmp/library/sbmp_checksum.h \ |
||||
lib/sbmp/library/sbmp_config.example.h \ |
||||
lib/sbmp/library/sbmp_datagram.h \ |
||||
lib/sbmp/library/sbmp_frame.h \ |
||||
lib/sbmp/library/sbmp_session.h \ |
||||
lib/sbmp/library/type_coerce.h \ |
||||
lib/spl/inc/misc.h \ |
||||
lib/spl/inc/stm32f10x_adc.h \ |
||||
lib/spl/inc/stm32f10x_bkp.h \ |
||||
lib/spl/inc/stm32f10x_can.h \ |
||||
lib/spl/inc/stm32f10x_cec.h \ |
||||
lib/spl/inc/stm32f10x_crc.h \ |
||||
lib/spl/inc/stm32f10x_dac.h \ |
||||
lib/spl/inc/stm32f10x_dbgmcu.h \ |
||||
lib/spl/inc/stm32f10x_dma.h \ |
||||
lib/spl/inc/stm32f10x_exti.h \ |
||||
lib/spl/inc/stm32f10x_flash.h \ |
||||
lib/spl/inc/stm32f10x_fsmc.h \ |
||||
lib/spl/inc/stm32f10x_gpio.h \ |
||||
lib/spl/inc/stm32f10x_i2c.h \ |
||||
lib/spl/inc/stm32f10x_iwdg.h \ |
||||
lib/spl/inc/stm32f10x_pwr.h \ |
||||
lib/spl/inc/stm32f10x_rcc.h \ |
||||
lib/spl/inc/stm32f10x_rtc.h \ |
||||
lib/spl/inc/stm32f10x_sdio.h \ |
||||
lib/spl/inc/stm32f10x_spi.h \ |
||||
lib/spl/inc/stm32f10x_tim.h \ |
||||
lib/spl/inc/stm32f10x_usart.h \ |
||||
lib/spl/inc/stm32f10x_wwdg.h \ |
||||
project/stm32f10x_conf.h \ |
||||
project/stm32f10x_it.h \ |
||||
project/system_stm32f10x.h \ |
||||
project/sbmp_config.h |
||||
|
||||
SOURCES += \ |
||||
lib/cmsis/core_cm3.c \ |
||||
lib/sbmp/library/crc32.c \ |
||||
lib/sbmp/library/payload_builder.c \ |
||||
lib/sbmp/library/payload_parser.c \ |
||||
lib/sbmp/library/sbmp_bulk.c \ |
||||
lib/sbmp/library/sbmp_checksum.c \ |
||||
lib/sbmp/library/sbmp_datagram.c \ |
||||
lib/sbmp/library/sbmp_frame.c \ |
||||
lib/sbmp/library/sbmp_session.c \ |
||||
lib/spl/src/misc.c \ |
||||
lib/spl/src/stm32f10x_adc.c \ |
||||
lib/spl/src/stm32f10x_bkp.c \ |
||||
lib/spl/src/stm32f10x_can.c \ |
||||
lib/spl/src/stm32f10x_cec.c \ |
||||
lib/spl/src/stm32f10x_crc.c \ |
||||
lib/spl/src/stm32f10x_dac.c \ |
||||
lib/spl/src/stm32f10x_dbgmcu.c \ |
||||
lib/spl/src/stm32f10x_dma.c \ |
||||
lib/spl/src/stm32f10x_exti.c \ |
||||
lib/spl/src/stm32f10x_flash.c \ |
||||
lib/spl/src/stm32f10x_fsmc.c \ |
||||
lib/spl/src/stm32f10x_gpio.c \ |
||||
lib/spl/src/stm32f10x_i2c.c \ |
||||
lib/spl/src/stm32f10x_iwdg.c \ |
||||
lib/spl/src/stm32f10x_pwr.c \ |
||||
lib/spl/src/stm32f10x_rcc.c \ |
||||
lib/spl/src/stm32f10x_rtc.c \ |
||||
lib/spl/src/stm32f10x_sdio.c \ |
||||
lib/spl/src/stm32f10x_spi.c \ |
||||
lib/spl/src/stm32f10x_tim.c \ |
||||
lib/spl/src/stm32f10x_usart.c \ |
||||
lib/spl/src/stm32f10x_wwdg.c \ |
||||
project/main.c \ |
||||
project/stm32f10x_it.c \ |
||||
project/system_stm32f10x.c |
||||
|
||||
DISTFILES += \ |
||||
style.astylerc \ |
||||
Makefile \ |
||||
lib/cmsis/startup_stm32f10x_md.s \ |
||||
lib/cmsis/stm32_flash.ld |
||||
@ -0,0 +1,372 @@ |
||||
<?xml version="1.0" encoding="UTF-8"?> |
||||
<!DOCTYPE QtCreatorProject> |
||||
<!-- Written by QtCreator 3.6.1, 2016-05-11T19:11:14. --> |
||||
<qtcreator> |
||||
<data> |
||||
<variable>EnvironmentId</variable> |
||||
<value type="QByteArray">{dfe3cb4a-0f3e-4da9-9c52-5d2c464adafb}</value> |
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<data> |
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<variable>ProjectExplorer.Project.ActiveTarget</variable> |
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<value type="bool" key="EditorConfiguration.CamelCaseNavigation">true</value> |
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<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.0"> |
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<value type="QString" key="language">Cpp</value> |
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<valuemap type="QVariantMap" key="value"> |
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<value type="QByteArray" key="CurrentPreferences">CppGlobal</value> |
||||
</valuemap> |
||||
</valuemap> |
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<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.1"> |
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<value type="QString" key="language">QmlJS</value> |
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<valuemap type="QVariantMap" key="value"> |
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<value type="QByteArray" key="CurrentPreferences">QmlJSGlobal</value> |
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<value type="bool" key="EditorConfiguration.MouseHiding">true</value> |
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<value type="bool" key="EditorConfiguration.MouseNavigation">true</value> |
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<value type="int" key="EditorConfiguration.PaddingMode">1</value> |
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<value type="bool" key="EditorConfiguration.ScrollWheelZooming">true</value> |
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<value type="bool" key="EditorConfiguration.ShowMargin">false</value> |
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<value type="int" key="EditorConfiguration.SmartBackspaceBehavior">0</value> |
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<value type="bool" key="EditorConfiguration.SpacesForTabs">true</value> |
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<value type="int" key="EditorConfiguration.TabKeyBehavior">0</value> |
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<value type="int" key="EditorConfiguration.TabSize">8</value> |
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<value type="bool" key="EditorConfiguration.UseGlobal">true</value> |
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<value type="int" key="EditorConfiguration.Utf8BomBehavior">1</value> |
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<value type="bool" key="EditorConfiguration.addFinalNewLine">true</value> |
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<value type="bool" key="EditorConfiguration.cleanIndentation">true</value> |
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<value type="bool" key="EditorConfiguration.cleanWhitespace">true</value> |
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<value type="bool" key="EditorConfiguration.inEntireDocument">true</value> |
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||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.MakeStep</value> |
||||
<valuelist type="QVariantList" key="Qt4ProjectManager.MakeStep.AutomaticallyAddedMakeArguments"> |
||||
<value type="QString">-w</value> |
||||
<value type="QString">-r</value> |
||||
</valuelist> |
||||
<value type="bool" key="Qt4ProjectManager.MakeStep.Clean">true</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeArguments">clean</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeCommand"></value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Clean</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Clean</value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">2</value> |
||||
<value type="bool" key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment">false</value> |
||||
<valuelist type="QVariantList" key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges"/> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Debug</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.Qt4BuildConfiguration</value> |
||||
<value type="int" key="Qt4ProjectManager.Qt4BuildConfiguration.BuildConfiguration">2</value> |
||||
<value type="bool" key="Qt4ProjectManager.Qt4BuildConfiguration.UseShadowBuild">true</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.Target.BuildConfiguration.1"> |
||||
<value type="QString" key="ProjectExplorer.BuildConfiguration.BuildDirectory">/home/ondra/devel/build-f103-STLINK-Release</value> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0"> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">qmake</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">QtProjectManager.QMakeBuildStep</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.LinkQmlDebuggingLibrary">false</value> |
||||
<value type="QString" key="QtProjectManager.QMakeBuildStep.QMakeArguments"></value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.QMakeForced">false</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.SeparateDebugInfo">false</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.UseQtQuickCompiler">false</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.1"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.MakeStep</value> |
||||
<valuelist type="QVariantList" key="Qt4ProjectManager.MakeStep.AutomaticallyAddedMakeArguments"> |
||||
<value type="QString">-w</value> |
||||
<value type="QString">-r</value> |
||||
</valuelist> |
||||
<value type="bool" key="Qt4ProjectManager.MakeStep.Clean">false</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeArguments"></value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeCommand"></value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">2</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Build</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Build</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.1"> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.MakeStep</value> |
||||
<valuelist type="QVariantList" key="Qt4ProjectManager.MakeStep.AutomaticallyAddedMakeArguments"> |
||||
<value type="QString">-w</value> |
||||
<value type="QString">-r</value> |
||||
</valuelist> |
||||
<value type="bool" key="Qt4ProjectManager.MakeStep.Clean">true</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeArguments">clean</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeCommand"></value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Clean</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Clean</value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">2</value> |
||||
<value type="bool" key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment">false</value> |
||||
<valuelist type="QVariantList" key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges"/> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Release</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.Qt4BuildConfiguration</value> |
||||
<value type="int" key="Qt4ProjectManager.Qt4BuildConfiguration.BuildConfiguration">0</value> |
||||
<value type="bool" key="Qt4ProjectManager.Qt4BuildConfiguration.UseShadowBuild">true</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.Target.BuildConfiguration.2"> |
||||
<value type="QString" key="ProjectExplorer.BuildConfiguration.BuildDirectory">/home/ondra/devel/build-f103-STLINK-Profile</value> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0"> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">qmake</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">QtProjectManager.QMakeBuildStep</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.LinkQmlDebuggingLibrary">true</value> |
||||
<value type="QString" key="QtProjectManager.QMakeBuildStep.QMakeArguments"></value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.QMakeForced">false</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.SeparateDebugInfo">true</value> |
||||
<value type="bool" key="QtProjectManager.QMakeBuildStep.UseQtQuickCompiler">false</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.1"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.MakeStep</value> |
||||
<valuelist type="QVariantList" key="Qt4ProjectManager.MakeStep.AutomaticallyAddedMakeArguments"> |
||||
<value type="QString">-w</value> |
||||
<value type="QString">-r</value> |
||||
</valuelist> |
||||
<value type="bool" key="Qt4ProjectManager.MakeStep.Clean">false</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeArguments"></value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeCommand"></value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">2</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Build</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Build</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.1"> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0"> |
||||
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.MakeStep</value> |
||||
<valuelist type="QVariantList" key="Qt4ProjectManager.MakeStep.AutomaticallyAddedMakeArguments"> |
||||
<value type="QString">-w</value> |
||||
<value type="QString">-r</value> |
||||
</valuelist> |
||||
<value type="bool" key="Qt4ProjectManager.MakeStep.Clean">true</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeArguments">clean</value> |
||||
<value type="QString" key="Qt4ProjectManager.MakeStep.MakeCommand"></value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Clean</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Clean</value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">2</value> |
||||
<value type="bool" key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment">false</value> |
||||
<valuelist type="QVariantList" key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges"/> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Profile</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">Qt4ProjectManager.Qt4BuildConfiguration</value> |
||||
<value type="int" key="Qt4ProjectManager.Qt4BuildConfiguration.BuildConfiguration">0</value> |
||||
<value type="bool" key="Qt4ProjectManager.Qt4BuildConfiguration.UseShadowBuild">true</value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.Target.BuildConfigurationCount">3</value> |
||||
<value type="int" key="ProjectExplorer.Target.DeployConfigurationCount">0</value> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.Target.PluginSettings"/> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.Target.RunConfiguration.0"> |
||||
<value type="bool" key="Analyzer.QmlProfiler.FlushEnabled">false</value> |
||||
<value type="uint" key="Analyzer.QmlProfiler.FlushInterval">1000</value> |
||||
<value type="QString" key="Analyzer.QmlProfiler.LastTraceFile"></value> |
||||
<value type="bool" key="Analyzer.QmlProfiler.Settings.UseGlobalSettings">true</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.AddedSuppressionFiles"/> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectBusEvents">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectSystime">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableBranchSim">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableCacheSim">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableEventToolTips">true</value> |
||||
<value type="double" key="Analyzer.Valgrind.Callgrind.MinimumCostRatio">0.01</value> |
||||
<value type="double" key="Analyzer.Valgrind.Callgrind.VisualisationMinimumCostRatio">10</value> |
||||
<value type="bool" key="Analyzer.Valgrind.FilterExternalIssues">true</value> |
||||
<value type="int" key="Analyzer.Valgrind.LeakCheckOnFinish">1</value> |
||||
<value type="int" key="Analyzer.Valgrind.NumCallers">25</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.RemovedSuppressionFiles"/> |
||||
<value type="int" key="Analyzer.Valgrind.SelfModifyingCodeDetection">1</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Settings.UseGlobalSettings">true</value> |
||||
<value type="bool" key="Analyzer.Valgrind.ShowReachable">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.TrackOrigins">true</value> |
||||
<value type="QString" key="Analyzer.Valgrind.ValgrindExecutable">valgrind</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.VisibleErrorKinds"> |
||||
<value type="int">0</value> |
||||
<value type="int">1</value> |
||||
<value type="int">2</value> |
||||
<value type="int">3</value> |
||||
<value type="int">4</value> |
||||
<value type="int">5</value> |
||||
<value type="int">6</value> |
||||
<value type="int">7</value> |
||||
<value type="int">8</value> |
||||
<value type="int">9</value> |
||||
<value type="int">10</value> |
||||
<value type="int">11</value> |
||||
<value type="int">12</value> |
||||
<value type="int">13</value> |
||||
<value type="int">14</value> |
||||
</valuelist> |
||||
<value type="int" key="PE.EnvironmentAspect.Base">2</value> |
||||
<valuelist type="QVariantList" key="PE.EnvironmentAspect.Changes"/> |
||||
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Arguments"></value> |
||||
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Executable"></value> |
||||
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.WorkingDirectory">%{buildDir}</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Custom Executable</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.CustomExecutableRunConfiguration</value> |
||||
<value type="uint" key="RunConfiguration.QmlDebugServerPort">3768</value> |
||||
<value type="bool" key="RunConfiguration.UseCppDebugger">false</value> |
||||
<value type="bool" key="RunConfiguration.UseCppDebuggerAuto">true</value> |
||||
<value type="bool" key="RunConfiguration.UseMultiProcess">false</value> |
||||
<value type="bool" key="RunConfiguration.UseQmlDebugger">false</value> |
||||
<value type="bool" key="RunConfiguration.UseQmlDebuggerAuto">true</value> |
||||
</valuemap> |
||||
<valuemap type="QVariantMap" key="ProjectExplorer.Target.RunConfiguration.1"> |
||||
<value type="bool" key="Analyzer.QmlProfiler.FlushEnabled">false</value> |
||||
<value type="uint" key="Analyzer.QmlProfiler.FlushInterval">1000</value> |
||||
<value type="QString" key="Analyzer.QmlProfiler.LastTraceFile"></value> |
||||
<value type="bool" key="Analyzer.QmlProfiler.Settings.UseGlobalSettings">true</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.AddedSuppressionFiles"/> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectBusEvents">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectSystime">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableBranchSim">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableCacheSim">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableEventToolTips">true</value> |
||||
<value type="double" key="Analyzer.Valgrind.Callgrind.MinimumCostRatio">0.01</value> |
||||
<value type="double" key="Analyzer.Valgrind.Callgrind.VisualisationMinimumCostRatio">10</value> |
||||
<value type="bool" key="Analyzer.Valgrind.FilterExternalIssues">true</value> |
||||
<value type="int" key="Analyzer.Valgrind.LeakCheckOnFinish">1</value> |
||||
<value type="int" key="Analyzer.Valgrind.NumCallers">25</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.RemovedSuppressionFiles"/> |
||||
<value type="int" key="Analyzer.Valgrind.SelfModifyingCodeDetection">1</value> |
||||
<value type="bool" key="Analyzer.Valgrind.Settings.UseGlobalSettings">true</value> |
||||
<value type="bool" key="Analyzer.Valgrind.ShowReachable">false</value> |
||||
<value type="bool" key="Analyzer.Valgrind.TrackOrigins">true</value> |
||||
<value type="QString" key="Analyzer.Valgrind.ValgrindExecutable">valgrind</value> |
||||
<valuelist type="QVariantList" key="Analyzer.Valgrind.VisibleErrorKinds"> |
||||
<value type="int">0</value> |
||||
<value type="int">1</value> |
||||
<value type="int">2</value> |
||||
<value type="int">3</value> |
||||
<value type="int">4</value> |
||||
<value type="int">5</value> |
||||
<value type="int">6</value> |
||||
<value type="int">7</value> |
||||
<value type="int">8</value> |
||||
<value type="int">9</value> |
||||
<value type="int">10</value> |
||||
<value type="int">11</value> |
||||
<value type="int">12</value> |
||||
<value type="int">13</value> |
||||
<value type="int">14</value> |
||||
</valuelist> |
||||
<value type="QString" key="BareMetal.CustomRunConfig.Executable"></value> |
||||
<value type="QString" key="BareMetal.RunConfig.WorkingDirectory"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Run on GDB server or hardware debugger</value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value> |
||||
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">BareMetal.CustomRunConfig</value> |
||||
<value type="QString" key="Qt4ProjectManager.MaemoRunConfiguration.Arguments"></value> |
||||
<value type="QString" key="Qt4ProjectManager.MaemoRunConfiguration.ProFile"></value> |
||||
<value type="uint" key="RunConfiguration.QmlDebugServerPort">3768</value> |
||||
<value type="bool" key="RunConfiguration.UseCppDebugger">false</value> |
||||
<value type="bool" key="RunConfiguration.UseCppDebuggerAuto">true</value> |
||||
<value type="bool" key="RunConfiguration.UseMultiProcess">false</value> |
||||
<value type="bool" key="RunConfiguration.UseQmlDebugger">false</value> |
||||
<value type="bool" key="RunConfiguration.UseQmlDebuggerAuto">true</value> |
||||
</valuemap> |
||||
<value type="int" key="ProjectExplorer.Target.RunConfigurationCount">2</value> |
||||
</valuemap> |
||||
</data> |
||||
<data> |
||||
<variable>ProjectExplorer.Project.TargetCount</variable> |
||||
<value type="int">1</value> |
||||
</data> |
||||
<data> |
||||
<variable>ProjectExplorer.Project.Updater.FileVersion</variable> |
||||
<value type="int">18</value> |
||||
</data> |
||||
<data> |
||||
<variable>Version</variable> |
||||
<value type="int">18</value> |
||||
</data> |
||||
</qtcreator> |
||||
@ -0,0 +1,4 @@ |
||||
# Include CMSIS
|
||||
|
||||
LIB_INCL_DIRS += lib/cmsis
|
||||
LIB_SOURCES += lib/cmsis/core_cm3.c
|
||||
@ -0,0 +1,12 @@ |
||||
# Include SBMP
|
||||
|
||||
LIB_INCL_DIRS += lib/sbmp/library
|
||||
|
||||
LIB_SOURCES += lib/sbmp/library/crc32.c
|
||||
LIB_SOURCES += lib/sbmp/library/payload_builder.c
|
||||
LIB_SOURCES += lib/sbmp/library/payload_parser.c
|
||||
LIB_SOURCES += lib/sbmp/library/sbmp_bulk.c
|
||||
LIB_SOURCES += lib/sbmp/library/sbmp_checksum.c
|
||||
LIB_SOURCES += lib/sbmp/library/sbmp_datagram.c
|
||||
LIB_SOURCES += lib/sbmp/library/sbmp_frame.c
|
||||
LIB_SOURCES += lib/sbmp/library/sbmp_session.c
|
||||
@ -0,0 +1,27 @@ |
||||
# Include Standard peripheral Driver
|
||||
|
||||
LIB_INCL_DIRS += lib/spl/inc
|
||||
|
||||
LIB_SOURCES += lib/spl/src/misc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_adc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_bkp.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_can.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_cec.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_crc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_dac.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_dbgmcu.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_dma.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_exti.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_flash.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_fsmc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_gpio.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_i2c.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_iwdg.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_pwr.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_rcc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_rtc.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_sdio.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_spi.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_tim.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_usart.c
|
||||
LIB_SOURCES += lib/spl/src/stm32f10x_wwdg.c
|
||||
@ -0,0 +1,784 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm3.c |
||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File |
||||
* @version V1.30 |
||||
* @date 30. October 2009 |
||||
* |
||||
* @note |
||||
* Copyright (C) 2009 ARM Limited. All rights reserved. |
||||
* |
||||
* @par |
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M |
||||
* processor based microcontrollers. This file can be freely distributed |
||||
* within development tools that are supporting such ARM based processors. |
||||
* |
||||
* @par |
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
||||
* |
||||
******************************************************************************/ |
||||
|
||||
#include <stdint.h> |
||||
|
||||
/* define compiler specific symbols */ |
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
|
||||
#endif |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
||||
/* ARM armcc specific functions */ |
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer |
||||
* |
||||
* @return ProcessStackPointer |
||||
* |
||||
* Return the actual process stack pointer |
||||
*/ |
||||
__ASM uint32_t __get_PSP(void) |
||||
{ |
||||
mrs r0, psp |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer |
||||
* |
||||
* @param topOfProcStack Process Stack Pointer |
||||
* |
||||
* Assign the value ProcessStackPointer to the MSP |
||||
* (process stack pointer) Cortex processor register |
||||
*/ |
||||
__ASM void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
msr psp, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer |
||||
* |
||||
* @return Main Stack Pointer |
||||
* |
||||
* Return the current value of the MSP (main stack pointer) |
||||
* Cortex processor register |
||||
*/ |
||||
__ASM uint32_t __get_MSP(void) |
||||
{ |
||||
mrs r0, msp |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer |
||||
* |
||||
* @param topOfMainStack Main Stack Pointer |
||||
* |
||||
* Assign the value mainStackPointer to the MSP |
||||
* (main stack pointer) Cortex processor register |
||||
*/ |
||||
__ASM void __set_MSP(uint32_t mainStackPointer) |
||||
{ |
||||
msr msp, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in unsigned short value |
||||
*/ |
||||
__ASM uint32_t __REV16(uint16_t value) |
||||
{ |
||||
rev16 r0, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in signed short value with sign extension to integer |
||||
*/ |
||||
__ASM int32_t __REVSH(int16_t value) |
||||
{ |
||||
revsh r0, r0 |
||||
bx lr |
||||
} |
||||
|
||||
|
||||
#if (__ARMCC_VERSION < 400000) |
||||
|
||||
/**
|
||||
* @brief Remove the exclusive lock created by ldrex |
||||
* |
||||
* Removes the exclusive lock which is created by ldrex. |
||||
*/ |
||||
__ASM void __CLREX(void) |
||||
{ |
||||
clrex |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value |
||||
* |
||||
* @return BasePriority |
||||
* |
||||
* Return the content of the base priority register |
||||
*/ |
||||
__ASM uint32_t __get_BASEPRI(void) |
||||
{ |
||||
mrs r0, basepri |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value |
||||
* |
||||
* @param basePri BasePriority |
||||
* |
||||
* Set the base priority register |
||||
*/ |
||||
__ASM void __set_BASEPRI(uint32_t basePri) |
||||
{ |
||||
msr basepri, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value |
||||
* |
||||
* @return PriMask |
||||
* |
||||
* Return state of the priority mask bit from the priority mask register |
||||
*/ |
||||
__ASM uint32_t __get_PRIMASK(void) |
||||
{ |
||||
mrs r0, primask |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value |
||||
* |
||||
* @param priMask PriMask |
||||
* |
||||
* Set the priority mask bit in the priority mask register |
||||
*/ |
||||
__ASM void __set_PRIMASK(uint32_t priMask) |
||||
{ |
||||
msr primask, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value |
||||
* |
||||
* @return FaultMask |
||||
* |
||||
* Return the content of the fault mask register |
||||
*/ |
||||
__ASM uint32_t __get_FAULTMASK(void) |
||||
{ |
||||
mrs r0, faultmask |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value |
||||
* |
||||
* @param faultMask faultMask value |
||||
* |
||||
* Set the fault mask register |
||||
*/ |
||||
__ASM void __set_FAULTMASK(uint32_t faultMask) |
||||
{ |
||||
msr faultmask, r0 |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Control Register value |
||||
* |
||||
* @return Control value |
||||
* |
||||
* Return the content of the control register |
||||
*/ |
||||
__ASM uint32_t __get_CONTROL(void) |
||||
{ |
||||
mrs r0, control |
||||
bx lr |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Control Register value |
||||
* |
||||
* @param control Control value |
||||
* |
||||
* Set the control register |
||||
*/ |
||||
__ASM void __set_CONTROL(uint32_t control) |
||||
{ |
||||
msr control, r0 |
||||
bx lr |
||||
} |
||||
|
||||
#endif /* __ARMCC_VERSION */ |
||||
|
||||
|
||||
|
||||
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
||||
/* IAR iccarm specific functions */ |
||||
#pragma diag_suppress=Pe940 |
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer |
||||
* |
||||
* @return ProcessStackPointer |
||||
* |
||||
* Return the actual process stack pointer |
||||
*/ |
||||
uint32_t __get_PSP(void) |
||||
{ |
||||
__ASM("mrs r0, psp"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer |
||||
* |
||||
* @param topOfProcStack Process Stack Pointer |
||||
* |
||||
* Assign the value ProcessStackPointer to the MSP |
||||
* (process stack pointer) Cortex processor register |
||||
*/ |
||||
void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
__ASM("msr psp, r0"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer |
||||
* |
||||
* @return Main Stack Pointer |
||||
* |
||||
* Return the current value of the MSP (main stack pointer) |
||||
* Cortex processor register |
||||
*/ |
||||
uint32_t __get_MSP(void) |
||||
{ |
||||
__ASM("mrs r0, msp"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer |
||||
* |
||||
* @param topOfMainStack Main Stack Pointer |
||||
* |
||||
* Assign the value mainStackPointer to the MSP |
||||
* (main stack pointer) Cortex processor register |
||||
*/ |
||||
void __set_MSP(uint32_t topOfMainStack) |
||||
{ |
||||
__ASM("msr msp, r0"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in unsigned short value |
||||
*/ |
||||
uint32_t __REV16(uint16_t value) |
||||
{ |
||||
__ASM("rev16 r0, r0"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse bit order of value |
||||
*/ |
||||
uint32_t __RBIT(uint32_t value) |
||||
{ |
||||
__ASM("rbit r0, r0"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 8 bit values) |
||||
*/ |
||||
uint8_t __LDREXB(uint8_t *addr) |
||||
{ |
||||
__ASM("ldrexb r0, [r0]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 16 bit values |
||||
*/ |
||||
uint16_t __LDREXH(uint16_t *addr) |
||||
{ |
||||
__ASM("ldrexh r0, [r0]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 32 bit values |
||||
*/ |
||||
uint32_t __LDREXW(uint32_t *addr) |
||||
{ |
||||
__ASM("ldrex r0, [r0]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 8 bit values |
||||
*/ |
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr) |
||||
{ |
||||
__ASM("strexb r0, r0, [r1]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 16 bit values |
||||
*/ |
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
||||
{ |
||||
__ASM("strexh r0, r0, [r1]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 32 bit values |
||||
*/ |
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr) |
||||
{ |
||||
__ASM("strex r0, r0, [r1]"); |
||||
__ASM("bx lr"); |
||||
} |
||||
|
||||
#pragma diag_default=Pe940 |
||||
|
||||
|
||||
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
||||
/* GNU gcc specific functions */ |
||||
|
||||
/**
|
||||
* @brief Return the Process Stack Pointer |
||||
* |
||||
* @return ProcessStackPointer |
||||
* |
||||
* Return the actual process stack pointer |
||||
*/ |
||||
uint32_t __get_PSP(void) __attribute__( ( naked ) ); |
||||
uint32_t __get_PSP(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, psp\n\t" |
||||
"MOV r0, %0 \n\t" |
||||
"BX lr \n\t" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Process Stack Pointer |
||||
* |
||||
* @param topOfProcStack Process Stack Pointer |
||||
* |
||||
* Assign the value ProcessStackPointer to the MSP |
||||
* (process stack pointer) Cortex processor register |
||||
*/ |
||||
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); |
||||
void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
__ASM volatile ("MSR psp, %0\n\t" |
||||
"BX lr \n\t" : : "r" (topOfProcStack) ); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Main Stack Pointer |
||||
* |
||||
* @return Main Stack Pointer |
||||
* |
||||
* Return the current value of the MSP (main stack pointer) |
||||
* Cortex processor register |
||||
*/ |
||||
uint32_t __get_MSP(void) __attribute__( ( naked ) ); |
||||
uint32_t __get_MSP(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, msp\n\t" |
||||
"MOV r0, %0 \n\t" |
||||
"BX lr \n\t" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Main Stack Pointer |
||||
* |
||||
* @param topOfMainStack Main Stack Pointer |
||||
* |
||||
* Assign the value mainStackPointer to the MSP |
||||
* (main stack pointer) Cortex processor register |
||||
*/ |
||||
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); |
||||
void __set_MSP(uint32_t topOfMainStack) |
||||
{ |
||||
__ASM volatile ("MSR msp, %0\n\t" |
||||
"BX lr \n\t" : : "r" (topOfMainStack) ); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Base Priority value |
||||
* |
||||
* @return BasePriority |
||||
* |
||||
* Return the content of the base priority register |
||||
*/ |
||||
uint32_t __get_BASEPRI(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Base Priority value |
||||
* |
||||
* @param basePri BasePriority |
||||
* |
||||
* Set the base priority register |
||||
*/ |
||||
void __set_BASEPRI(uint32_t value) |
||||
{ |
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Priority Mask value |
||||
* |
||||
* @return PriMask |
||||
* |
||||
* Return state of the priority mask bit from the priority mask register |
||||
*/ |
||||
uint32_t __get_PRIMASK(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Priority Mask value |
||||
* |
||||
* @param priMask PriMask |
||||
* |
||||
* Set the priority mask bit in the priority mask register |
||||
*/ |
||||
void __set_PRIMASK(uint32_t priMask) |
||||
{ |
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Fault Mask value |
||||
* |
||||
* @return FaultMask |
||||
* |
||||
* Return the content of the fault mask register |
||||
*/ |
||||
uint32_t __get_FAULTMASK(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Fault Mask value |
||||
* |
||||
* @param faultMask faultMask value |
||||
* |
||||
* Set the fault mask register |
||||
*/ |
||||
void __set_FAULTMASK(uint32_t faultMask) |
||||
{ |
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the Control Register value |
||||
* |
||||
* @return Control value |
||||
* |
||||
* Return the content of the control register |
||||
*/ |
||||
uint32_t __get_CONTROL(void) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set the Control Register value |
||||
* |
||||
* @param control Control value |
||||
* |
||||
* Set the control register |
||||
*/ |
||||
void __set_CONTROL(uint32_t control) |
||||
{ |
||||
__ASM volatile ("MSR control, %0" : : "r" (control) ); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Reverse byte order in integer value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in integer value |
||||
*/ |
||||
uint32_t __REV(uint32_t value) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse byte order in unsigned short value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in unsigned short value |
||||
*/ |
||||
uint32_t __REV16(uint16_t value) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse byte order in signed short value with sign extension to integer |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse byte order in signed short value with sign extension to integer |
||||
*/ |
||||
int32_t __REVSH(int16_t value) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Reverse bit order of value |
||||
* |
||||
* @param value value to reverse |
||||
* @return reversed value |
||||
* |
||||
* Reverse bit order of value |
||||
*/ |
||||
uint32_t __RBIT(uint32_t value) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (8 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 8 bit value |
||||
*/ |
||||
uint8_t __LDREXB(uint8_t *addr) |
||||
{ |
||||
uint8_t result=0; |
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (16 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 16 bit values |
||||
*/ |
||||
uint16_t __LDREXH(uint16_t *addr) |
||||
{ |
||||
uint16_t result=0; |
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief LDR Exclusive (32 bit) |
||||
* |
||||
* @param *addr address pointer |
||||
* @return value of (*address) |
||||
* |
||||
* Exclusive LDR command for 32 bit values |
||||
*/ |
||||
uint32_t __LDREXW(uint32_t *addr) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (8 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 8 bit values |
||||
*/ |
||||
uint32_t __STREXB(uint8_t value, uint8_t *addr) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (16 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 16 bit values |
||||
*/ |
||||
uint32_t __STREXH(uint16_t value, uint16_t *addr) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
/**
|
||||
* @brief STR Exclusive (32 bit) |
||||
* |
||||
* @param value value to store |
||||
* @param *addr address pointer |
||||
* @return successful / failed |
||||
* |
||||
* Exclusive STR command for 32 bit values |
||||
*/ |
||||
uint32_t __STREXW(uint32_t value, uint32_t *addr) |
||||
{ |
||||
uint32_t result=0; |
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
||||
return(result); |
||||
} |
||||
|
||||
|
||||
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
||||
/* TASKING carm specific functions */ |
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all instrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,358 @@ |
||||
/** |
||||
****************************************************************************** |
||||
* @file startup_stm32f10x_md.s
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.0
|
||||
* @date 11-March-2011
|
||||
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
|
||||
* This module performs: |
||||
* - Set the initial SP |
||||
* - Set the initial PC == Reset_Handler, |
||||
* - Set the vector table entries with the exceptions ISR address |
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually |
||||
* calls main()). |
||||
* After Reset the Cortex-M3 processor is in Thread mode, |
||||
* priority is Privileged, and the Stack is set to Main. |
||||
****************************************************************************** |
||||
* @attention
|
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3 |
||||
.fpu softvfp
|
||||
.thumb |
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */ |
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */ |
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */ |
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */ |
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF108F85F |
||||
/** |
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely |
||||
* necessary set is performed, after which the application |
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/ |
||||
|
||||
.section .text.Reset_Handler |
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function |
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0 |
||||
b LoopCopyDataInit |
||||
|
||||
CopyDataInit: |
||||
ldr r3, =_sidata |
||||
ldr r3, [r3, r1] |
||||
str r3, [r0, r1] |
||||
adds r1, r1, #4 |
||||
|
||||
LoopCopyDataInit: |
||||
ldr r0, =_sdata |
||||
ldr r3, =_edata |
||||
adds r2, r0, r1 |
||||
cmp r2, r3 |
||||
bcc CopyDataInit |
||||
ldr r2, =_sbss |
||||
b LoopFillZerobss |
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss: |
||||
movs r3, #0 |
||||
str r3, [r2], #4 |
||||
|
||||
LoopFillZerobss: |
||||
ldr r3, = _ebss |
||||
cmp r2, r3 |
||||
bcc FillZerobss |
||||
/* Call the clock system intitialization function.*/ |
||||
bl SystemInit
|
||||
/* Call the application's entry point.*/ |
||||
bl main |
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler |
||||
|
||||
/** |
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving |
||||
* the system state for examination by a debugger. |
||||
* @param None
|
||||
* @retval None
|
||||
*/ |
||||
.section .text.Default_Handler,"ax",%progbits |
||||
Default_Handler: |
||||
Infinite_Loop: |
||||
b Infinite_Loop |
||||
.size Default_Handler, .-Default_Handler |
||||
/****************************************************************************** |
||||
* |
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs |
||||
* must be placed on this to ensure that it ends up at physical address |
||||
* 0x0000.0000. |
||||
* |
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits |
||||
.type g_pfnVectors, %object |
||||
.size g_pfnVectors, .-g_pfnVectors |
||||
|
||||
|
||||
g_pfnVectors: |
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_CAN1_TX_IRQHandler
|
||||
.word USB_LP_CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTCAlarm_IRQHandler
|
||||
.word USBWakeUp_IRQHandler |
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||
STM32F10x Medium Density devices. */ |
||||
|
||||
/******************************************************************************* |
||||
* |
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition. |
||||
* |
||||
*******************************************************************************/ |
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler |
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler |
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler |
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler |
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler |
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler |
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler |
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler |
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler |
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler |
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler |
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler |
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler |
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler |
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler |
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler |
||||
|
||||
.weak USB_HP_CAN1_TX_IRQHandler
|
||||
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler |
||||
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler |
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler |
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler |
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler |
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler |
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler |
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler |
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler |
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler |
||||
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.thumb_set USBWakeUp_IRQHandler,Default_Handler |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,141 @@ |
||||
/* (c) Attolic, modified */ |
||||
|
||||
/* Entry Point */ |
||||
ENTRY(Reset_Handler) |
||||
|
||||
/* Highest address of the user mode stack */ |
||||
_estack = 0x20005000; /* end of 12K RAM */ |
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */ |
||||
_Min_Heap_Size = 0; /* required amount of heap */ |
||||
_Min_Stack_Size = 0x200; /* required amount of stack */ |
||||
|
||||
/* Specify the memory areas */ |
||||
MEMORY |
||||
{ |
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K |
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K |
||||
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K |
||||
} |
||||
|
||||
/* Define output sections */ |
||||
SECTIONS |
||||
{ |
||||
/* The startup code goes first into FLASH */ |
||||
.isr_vector : |
||||
{ |
||||
. = ALIGN(4); |
||||
KEEP(*(.isr_vector)) /* Startup code */ |
||||
. = ALIGN(4); |
||||
} >FLASH |
||||
|
||||
/* The program code and other data goes into FLASH */ |
||||
.text : |
||||
{ |
||||
. = ALIGN(4); |
||||
*(.text) /* .text sections (code) */ |
||||
*(.text*) /* .text* sections (code) */ |
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */ |
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ |
||||
*(.glue_7) /* glue arm to thumb code */ |
||||
*(.glue_7t) /* glue thumb to arm code */ |
||||
|
||||
KEEP (*(.init)) |
||||
KEEP (*(.fini)) |
||||
|
||||
. = ALIGN(4); |
||||
_etext = .; /* define a global symbols at end of code */ |
||||
} >FLASH |
||||
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH |
||||
.ARM : { |
||||
__exidx_start = .; |
||||
*(.ARM.exidx*) |
||||
__exidx_end = .; |
||||
} >FLASH |
||||
|
||||
.ARM.attributes : { *(.ARM.attributes) } > FLASH |
||||
|
||||
.preinit_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__preinit_array_start = .); |
||||
KEEP (*(.preinit_array*)) |
||||
PROVIDE_HIDDEN (__preinit_array_end = .); |
||||
} >FLASH |
||||
.init_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__init_array_start = .); |
||||
KEEP (*(SORT(.init_array.*))) |
||||
KEEP (*(.init_array*)) |
||||
PROVIDE_HIDDEN (__init_array_end = .); |
||||
} >FLASH |
||||
.fini_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__fini_array_start = .); |
||||
KEEP (*(.fini_array*)) |
||||
KEEP (*(SORT(.fini_array.*))) |
||||
PROVIDE_HIDDEN (__fini_array_end = .); |
||||
} >FLASH |
||||
|
||||
/* used by the startup to initialize data */ |
||||
_sidata = .; |
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */ |
||||
.data : AT ( _sidata ) |
||||
{ |
||||
. = ALIGN(4); |
||||
_sdata = .; /* create a global symbol at data start */ |
||||
*(.data) /* .data sections */ |
||||
*(.data*) /* .data* sections */ |
||||
|
||||
. = ALIGN(4); |
||||
_edata = .; /* define a global symbol at data end */ |
||||
} >RAM |
||||
|
||||
/* Uninitialized data section */ |
||||
. = ALIGN(4); |
||||
.bss : |
||||
{ |
||||
/* This is used by the startup in order to initialize the .bss secion */ |
||||
_sbss = .; /* define a global symbol at bss start */ |
||||
__bss_start__ = _sbss; |
||||
*(.bss) |
||||
*(.bss*) |
||||
*(COMMON) |
||||
|
||||
. = ALIGN(4); |
||||
_ebss = .; /* define a global symbol at bss end */ |
||||
__bss_end__ = _ebss; |
||||
} >RAM |
||||
|
||||
PROVIDE ( end = _ebss ); |
||||
PROVIDE ( _end = _ebss ); |
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */ |
||||
._user_heap_stack : |
||||
{ |
||||
. = ALIGN(4); |
||||
. = . + _Min_Heap_Size; |
||||
. = . + _Min_Stack_Size; |
||||
. = ALIGN(4); |
||||
} >RAM |
||||
|
||||
/* MEMORY_bank1 section, code must be located here explicitly */ |
||||
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ |
||||
.memory_b1_text : |
||||
{ |
||||
*(.mb1text) /* .mb1text sections (code) */ |
||||
*(.mb1text*) /* .mb1text* sections (code) */ |
||||
*(.mb1rodata) /* read-only data (constants) */ |
||||
*(.mb1rodata*) |
||||
} >MEMORY_B1 |
||||
|
||||
/* Remove information from the standard libraries */ |
||||
/DISCARD/ : |
||||
{ |
||||
libc.a ( * ) |
||||
libm.a ( * ) |
||||
libgcc.a ( * ) |
||||
} |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@ |
||||
Subproject commit c4e6c1a76631da0f7fbe17f7f9df69a2e7534e23 |
||||
@ -0,0 +1,220 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file misc.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the miscellaneous |
||||
* firmware library functions (add-on to CMSIS functions). |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __MISC_H |
||||
#define __MISC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup MISC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup MISC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list, please |
||||
refer to stm32f10x.h file) */ |
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value |
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ |
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value |
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */ |
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup NVIC_Priority_Table
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
@code
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according |
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function |
||||
============================================================================================================================ |
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description |
||||
============================================================================================================================ |
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority |
||||
| | | 4 bits for subpriority |
||||
---------------------------------------------------------------------------------------------------------------------------- |
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority |
||||
| | | 3 bits for subpriority |
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority |
||||
| | | 2 bits for subpriority |
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority |
||||
| | | 1 bits for subpriority |
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority |
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================ |
||||
@endcode |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup Vector_Table_Base
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000) |
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) |
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ |
||||
((VECTTAB) == NVIC_VectTab_FLASH)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup System_Low_Power
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10) |
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) |
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) |
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ |
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Preemption_Priority_Group
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority |
||||
4 bits for subpriority */ |
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority |
||||
3 bits for subpriority */ |
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority |
||||
2 bits for subpriority */ |
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority |
||||
1 bits for subpriority */ |
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority |
||||
0 bits for subpriority */ |
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ |
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4)) |
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SysTick_clock_source
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) |
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) |
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ |
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup MISC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup MISC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); |
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); |
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); |
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); |
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __MISC_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,483 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_adc.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_ADC_H |
||||
#define __STM32F10x_ADC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup ADC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup ADC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */ |
||||
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode. |
||||
This parameter can be set to ENABLE or DISABLE */ |
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode. |
||||
This parameter can be set to ENABLE or DISABLE. */ |
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter |
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ |
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */ |
||||
|
||||
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group. |
||||
This parameter must range from 1 to 16. */ |
||||
}ADC_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ |
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3)) |
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ |
||||
((PERIPH) == ADC3)) |
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000) |
||||
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) |
||||
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) |
||||
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) |
||||
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) |
||||
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) |
||||
#define ADC_Mode_RegSimult ((uint32_t)0x00060000) |
||||
#define ADC_Mode_FastInterl ((uint32_t)0x00070000) |
||||
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) |
||||
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) |
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ |
||||
((MODE) == ADC_Mode_RegInjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_InjecSimult) || \
|
||||
((MODE) == ADC_Mode_RegSimult) || \
|
||||
((MODE) == ADC_Mode_FastInterl) || \
|
||||
((MODE) == ADC_Mode_SlowInterl) || \
|
||||
((MODE) == ADC_Mode_AlterTrig)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ |
||||
|
||||
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ |
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ |
||||
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ |
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ |
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000) |
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800) |
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ |
||||
((ALIGN) == ADC_DataAlign_Left)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_Channel_0 ((uint8_t)0x00) |
||||
#define ADC_Channel_1 ((uint8_t)0x01) |
||||
#define ADC_Channel_2 ((uint8_t)0x02) |
||||
#define ADC_Channel_3 ((uint8_t)0x03) |
||||
#define ADC_Channel_4 ((uint8_t)0x04) |
||||
#define ADC_Channel_5 ((uint8_t)0x05) |
||||
#define ADC_Channel_6 ((uint8_t)0x06) |
||||
#define ADC_Channel_7 ((uint8_t)0x07) |
||||
#define ADC_Channel_8 ((uint8_t)0x08) |
||||
#define ADC_Channel_9 ((uint8_t)0x09) |
||||
#define ADC_Channel_10 ((uint8_t)0x0A) |
||||
#define ADC_Channel_11 ((uint8_t)0x0B) |
||||
#define ADC_Channel_12 ((uint8_t)0x0C) |
||||
#define ADC_Channel_13 ((uint8_t)0x0D) |
||||
#define ADC_Channel_14 ((uint8_t)0x0E) |
||||
#define ADC_Channel_15 ((uint8_t)0x0F) |
||||
#define ADC_Channel_16 ((uint8_t)0x10) |
||||
#define ADC_Channel_17 ((uint8_t)0x11) |
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) |
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) |
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ |
||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) |
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) |
||||
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) |
||||
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) |
||||
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) |
||||
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) |
||||
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) |
||||
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) |
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ |
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_13Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_28Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_41Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_55Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_71Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_239Cycles5)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ |
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ |
||||
|
||||
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ |
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ |
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ |
||||
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ |
||||
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ |
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ |
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14) |
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18) |
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C) |
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20) |
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ |
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) |
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) |
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) |
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) |
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) |
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) |
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) |
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ |
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220) |
||||
#define ADC_IT_AWD ((uint16_t)0x0140) |
||||
#define ADC_IT_JEOC ((uint16_t)0x0480) |
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) |
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ |
||||
((IT) == ADC_IT_JEOC)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01) |
||||
#define ADC_FLAG_EOC ((uint8_t)0x02) |
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04) |
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08) |
||||
#define ADC_FLAG_STRT ((uint8_t)0x10) |
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) |
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ |
||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx); |
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); |
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); |
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); |
||||
void ADC_ResetCalibration(ADC_TypeDef* ADCx); |
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); |
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx); |
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); |
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); |
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); |
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); |
||||
uint32_t ADC_GetDualModeConversionValue(void); |
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); |
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); |
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); |
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); |
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); |
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); |
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); |
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); |
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); |
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState); |
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); |
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); |
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); |
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__STM32F10x_ADC_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,195 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_bkp.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the BKP firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_BKP_H |
||||
#define __STM32F10x_BKP_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup BKP
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup BKP_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup BKP_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup Tamper_Pin_active_level
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define BKP_TamperPinLevel_High ((uint16_t)0x0000) |
||||
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) |
||||
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ |
||||
((LEVEL) == BKP_TamperPinLevel_Low)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define BKP_RTCOutputSource_None ((uint16_t)0x0000) |
||||
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) |
||||
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) |
||||
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) |
||||
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ |
||||
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
|
||||
((SOURCE) == BKP_RTCOutputSource_Second)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Data_Backup_Register
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define BKP_DR1 ((uint16_t)0x0004) |
||||
#define BKP_DR2 ((uint16_t)0x0008) |
||||
#define BKP_DR3 ((uint16_t)0x000C) |
||||
#define BKP_DR4 ((uint16_t)0x0010) |
||||
#define BKP_DR5 ((uint16_t)0x0014) |
||||
#define BKP_DR6 ((uint16_t)0x0018) |
||||
#define BKP_DR7 ((uint16_t)0x001C) |
||||
#define BKP_DR8 ((uint16_t)0x0020) |
||||
#define BKP_DR9 ((uint16_t)0x0024) |
||||
#define BKP_DR10 ((uint16_t)0x0028) |
||||
#define BKP_DR11 ((uint16_t)0x0040) |
||||
#define BKP_DR12 ((uint16_t)0x0044) |
||||
#define BKP_DR13 ((uint16_t)0x0048) |
||||
#define BKP_DR14 ((uint16_t)0x004C) |
||||
#define BKP_DR15 ((uint16_t)0x0050) |
||||
#define BKP_DR16 ((uint16_t)0x0054) |
||||
#define BKP_DR17 ((uint16_t)0x0058) |
||||
#define BKP_DR18 ((uint16_t)0x005C) |
||||
#define BKP_DR19 ((uint16_t)0x0060) |
||||
#define BKP_DR20 ((uint16_t)0x0064) |
||||
#define BKP_DR21 ((uint16_t)0x0068) |
||||
#define BKP_DR22 ((uint16_t)0x006C) |
||||
#define BKP_DR23 ((uint16_t)0x0070) |
||||
#define BKP_DR24 ((uint16_t)0x0074) |
||||
#define BKP_DR25 ((uint16_t)0x0078) |
||||
#define BKP_DR26 ((uint16_t)0x007C) |
||||
#define BKP_DR27 ((uint16_t)0x0080) |
||||
#define BKP_DR28 ((uint16_t)0x0084) |
||||
#define BKP_DR29 ((uint16_t)0x0088) |
||||
#define BKP_DR30 ((uint16_t)0x008C) |
||||
#define BKP_DR31 ((uint16_t)0x0090) |
||||
#define BKP_DR32 ((uint16_t)0x0094) |
||||
#define BKP_DR33 ((uint16_t)0x0098) |
||||
#define BKP_DR34 ((uint16_t)0x009C) |
||||
#define BKP_DR35 ((uint16_t)0x00A0) |
||||
#define BKP_DR36 ((uint16_t)0x00A4) |
||||
#define BKP_DR37 ((uint16_t)0x00A8) |
||||
#define BKP_DR38 ((uint16_t)0x00AC) |
||||
#define BKP_DR39 ((uint16_t)0x00B0) |
||||
#define BKP_DR40 ((uint16_t)0x00B4) |
||||
#define BKP_DR41 ((uint16_t)0x00B8) |
||||
#define BKP_DR42 ((uint16_t)0x00BC) |
||||
|
||||
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ |
||||
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
|
||||
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
|
||||
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
|
||||
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
|
||||
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
|
||||
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
|
||||
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
|
||||
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
|
||||
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
|
||||
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
|
||||
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
|
||||
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
|
||||
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) |
||||
|
||||
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup BKP_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup BKP_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void BKP_DeInit(void); |
||||
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); |
||||
void BKP_TamperPinCmd(FunctionalState NewState); |
||||
void BKP_ITConfig(FunctionalState NewState); |
||||
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); |
||||
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); |
||||
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); |
||||
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); |
||||
FlagStatus BKP_GetFlagStatus(void); |
||||
void BKP_ClearFlag(void); |
||||
ITStatus BKP_GetITStatus(void); |
||||
void BKP_ClearITPendingBit(void); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_BKP_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,697 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_can.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_CAN_H |
||||
#define __STM32F10x_CAN_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup CAN
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ |
||||
((PERIPH) == CAN2)) |
||||
|
||||
/**
|
||||
* @brief CAN init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */ |
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of
|
||||
@ref CAN_operating_mode */ |
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization. |
||||
This parameter can be a value of
|
||||
@ref CAN_synchronisation_jump_width */ |
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */ |
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 2. |
||||
This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_2 */ |
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
|
||||
communication mode. This parameter can be set
|
||||
either to ENABLE or DISABLE. */ |
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
|
||||
management. This parameter can be set either
|
||||
to ENABLE or DISABLE. */ |
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or
|
||||
DISABLE. */ |
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
|
||||
retransmission mode. This parameter can be
|
||||
set either to ENABLE or DISABLE. */ |
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */ |
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */ |
||||
} CAN_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration). |
||||
This parameter can be a value between 0x0000 and 0xFFFF */ |
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration). |
||||
This parameter can be a value between 0x0000 and 0xFFFF */ |
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration, |
||||
first one for a 16-bit configuration). |
||||
This parameter can be a value between 0x0000 and 0xFFFF */ |
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration, |
||||
second one for a 16-bit configuration). |
||||
This parameter can be a value between 0x0000 and 0xFFFF */ |
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */ |
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ |
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */ |
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */ |
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */ |
||||
} CAN_FilterInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */ |
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */ |
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */ |
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */ |
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */ |
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */ |
||||
} CanTxMsg; |
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */ |
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */ |
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */ |
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */ |
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */ |
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */ |
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */ |
||||
} CanRxMsg; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ |
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ |
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ |
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ |
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ |
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ |
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Operating_Mode
|
||||
* @{ |
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ |
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ |
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ |
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ |
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @defgroup CAN_Mode_Status |
||||
* @{ |
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ |
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ |
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ |
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ |
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ |
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ |
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ |
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ |
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ |
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ |
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ |
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ |
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ |
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ |
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ |
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ |
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ |
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ |
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ |
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ |
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ |
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ |
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ |
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ |
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ |
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ |
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ |
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ |
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ |
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ |
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{ |
||||
*/ |
||||
#ifndef STM32F10X_CL |
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) |
||||
#else |
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) |
||||
#endif /* STM32F10X_CL */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ |
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ |
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ |
||||
((MODE) == CAN_FilterMode_IdList)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ |
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ |
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ |
||||
((SCALE) == CAN_FilterScale_32bit)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ |
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ |
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ |
||||
((FIFO) == CAN_FilterFIFO1)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Start_bank_filter_for_slave_CAN
|
||||
* @{ |
||||
*/ |
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) |
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) |
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) |
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ |
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ |
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ |
||||
((IDTYPE) == CAN_Id_Extended)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ |
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ |
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ |
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ |
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ |
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ |
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ |
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ |
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ |
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants |
||||
* @{ |
||||
*/
|
||||
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ |
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ |
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ |
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ |
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ |
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ |
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ |
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{ |
||||
*/ |
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */ |
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ |
||||
|
||||
/* Transmit Flags */ |
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ |
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ |
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ |
||||
|
||||
/* Receive Flags */ |
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ |
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ |
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ |
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ |
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ |
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ |
||||
|
||||
/* Operating Mode Flags */ |
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ |
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ |
||||
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/ |
||||
|
||||
/* Error Flags */ |
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ |
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ |
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ |
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ |
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ |
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK )) |
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ |
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ |
||||
|
||||
/* Receive Interrupts */ |
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ |
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ |
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ |
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ |
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ |
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ |
||||
|
||||
/* Operating Mode Interrupts */ |
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ |
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ |
||||
|
||||
/* Error Interrupts */ |
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ |
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ |
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ |
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ |
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ |
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */ |
||||
#define CAN_IT_RQCP0 CAN_IT_TME |
||||
#define CAN_IT_RQCP1 CAN_IT_TME |
||||
#define CAN_IT_RQCP2 CAN_IT_TME |
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ |
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) |
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ |
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Legacy
|
||||
* @{ |
||||
*/ |
||||
#define CANINITFAILED CAN_InitStatus_Failed |
||||
#define CANINITOK CAN_InitStatus_Success |
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0 |
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1 |
||||
#define CAN_ID_STD CAN_Id_Standard |
||||
#define CAN_ID_EXT CAN_Id_Extended |
||||
#define CAN_RTR_DATA CAN_RTR_Data |
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote |
||||
#define CANTXFAILE CAN_TxStatus_Failed |
||||
#define CANTXOK CAN_TxStatus_Ok |
||||
#define CANTXPENDING CAN_TxStatus_Pending |
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox |
||||
#define CANSLEEPFAILED CAN_Sleep_Failed |
||||
#define CANSLEEPOK CAN_Sleep_Ok |
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed |
||||
#define CANWAKEUPOK CAN_WakeUp_Ok |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CAN_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx); |
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); |
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); |
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); |
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); |
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); |
||||
|
||||
/* Transmit functions *********************************************************/ |
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); |
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); |
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); |
||||
|
||||
/* Receive functions **********************************************************/ |
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); |
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); |
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); |
||||
|
||||
|
||||
/* Operation modes functions **************************************************/ |
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); |
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx); |
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx); |
||||
|
||||
/* Error management functions *************************************************/ |
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); |
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); |
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); |
||||
|
||||
/* Interrupts and flags management functions **********************************/ |
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); |
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); |
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); |
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); |
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_CAN_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,210 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_cec.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_CEC_H |
||||
#define __STM32F10x_CEC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup CEC
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup CEC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief CEC Init structure definition
|
||||
*/
|
||||
typedef struct |
||||
{ |
||||
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitTiming_Mode */ |
||||
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
|
||||
This parameter can be a value of @ref CEC_BitPeriod_Mode */ |
||||
}CEC_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup CEC_BitTiming_Mode
|
||||
* @{ |
||||
*/
|
||||
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ |
||||
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ |
||||
|
||||
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ |
||||
((MODE) == CEC_BitTimingErrFreeMode)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CEC_BitPeriod_Mode
|
||||
* @{ |
||||
*/
|
||||
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ |
||||
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ |
||||
|
||||
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ |
||||
((MODE) == CEC_BitPeriodFlexibleMode)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_interrupts_definition
|
||||
* @{ |
||||
*/
|
||||
#define CEC_IT_TERR CEC_CSR_TERR |
||||
#define CEC_IT_TBTRF CEC_CSR_TBTRF |
||||
#define CEC_IT_RERR CEC_CSR_RERR |
||||
#define CEC_IT_RBTF CEC_CSR_RBTF |
||||
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ |
||||
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CEC_Own_Address
|
||||
* @{ |
||||
*/
|
||||
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup CEC_Prescaler
|
||||
* @{ |
||||
*/
|
||||
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CEC_flags_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief ESR register flags
|
||||
*/
|
||||
#define CEC_FLAG_BTE ((uint32_t)0x10010000) |
||||
#define CEC_FLAG_BPE ((uint32_t)0x10020000) |
||||
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) |
||||
#define CEC_FLAG_SBE ((uint32_t)0x10080000) |
||||
#define CEC_FLAG_ACKE ((uint32_t)0x10100000) |
||||
#define CEC_FLAG_LINE ((uint32_t)0x10200000) |
||||
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) |
||||
|
||||
/**
|
||||
* @brief CSR register flags
|
||||
*/
|
||||
#define CEC_FLAG_TEOM ((uint32_t)0x00000002) |
||||
#define CEC_FLAG_TERR ((uint32_t)0x00000004) |
||||
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) |
||||
#define CEC_FLAG_RSOM ((uint32_t)0x00000010) |
||||
#define CEC_FLAG_REOM ((uint32_t)0x00000020) |
||||
#define CEC_FLAG_RERR ((uint32_t)0x00000040) |
||||
#define CEC_FLAG_RBTF ((uint32_t)0x00000080) |
||||
|
||||
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) |
||||
|
||||
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ |
||||
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
|
||||
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
|
||||
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
|
||||
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
|
||||
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
|
||||
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup CEC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CEC_Exported_Functions
|
||||
* @{ |
||||
*/
|
||||
void CEC_DeInit(void); |
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); |
||||
void CEC_Cmd(FunctionalState NewState); |
||||
void CEC_ITConfig(FunctionalState NewState); |
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); |
||||
void CEC_SetPrescaler(uint16_t CEC_Prescaler); |
||||
void CEC_SendDataByte(uint8_t Data); |
||||
uint8_t CEC_ReceiveDataByte(void); |
||||
void CEC_StartOfMessage(void); |
||||
void CEC_EndOfMessageCmd(FunctionalState NewState); |
||||
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); |
||||
void CEC_ClearFlag(uint32_t CEC_FLAG); |
||||
ITStatus CEC_GetITStatus(uint8_t CEC_IT); |
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_CEC_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,94 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_crc.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_CRC_H |
||||
#define __STM32F10x_CRC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup CRC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CRC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CRC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CRC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void CRC_ResetDR(void); |
||||
uint32_t CRC_CalcCRC(uint32_t Data); |
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); |
||||
uint32_t CRC_GetCRC(void); |
||||
void CRC_SetIDRegister(uint8_t IDValue); |
||||
uint8_t CRC_GetIDRegister(void); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_CRC_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,317 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_dac.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_DAC_H |
||||
#define __STM32F10x_DAC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DAC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DAC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */ |
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated. |
||||
This parameter can be a value of @ref DAC_wave_generation */ |
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ |
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */ |
||||
}DAC_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register |
||||
has been loaded, and not by external trigger */ |
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel |
||||
only in High-density devices*/ |
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel |
||||
only in Connectivity line, Medium-density and Low-density Value Line devices */ |
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel |
||||
only in Medium-density and Low-density Value Line devices*/ |
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ |
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ |
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ |
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000) |
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) |
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) |
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ |
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ |
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ |
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ |
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ |
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ |
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ |
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ |
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ |
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ |
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ |
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ |
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ |
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ |
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ |
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ |
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) |
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) |
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ |
||||
((STATE) == DAC_OutputBuffer_Disable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000) |
||||
#define DAC_Channel_2 ((uint32_t)0x00000010) |
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ |
||||
((CHANNEL) == DAC_Channel_2)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000) |
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004) |
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008) |
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ |
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040) |
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080) |
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ |
||||
((WAVE) == DAC_Wave_Triangle)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000) |
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) |
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DAC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void DAC_DeInit(void); |
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); |
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); |
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); |
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); |
||||
#endif |
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); |
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); |
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); |
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); |
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); |
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); |
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); |
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); |
||||
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) |
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); |
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); |
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); |
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); |
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__STM32F10x_DAC_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,119 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_dbgmcu.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||
* firmware library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_DBGMCU_H |
||||
#define __STM32F10x_DBGMCU_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DBGMCU_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001) |
||||
#define DBGMCU_STOP ((uint32_t)0x00000002) |
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004) |
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) |
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) |
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) |
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) |
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) |
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) |
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) |
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) |
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) |
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) |
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) |
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) |
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) |
||||
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) |
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) |
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) |
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) |
||||
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) |
||||
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) |
||||
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) |
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) |
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) |
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) |
||||
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DBGMCU_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
uint32_t DBGMCU_GetREVID(void); |
||||
uint32_t DBGMCU_GetDEVID(void); |
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_DBGMCU_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,439 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_dma.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_DMA_H |
||||
#define __STM32F10x_DMA_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DMA
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ |
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ |
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */ |
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize |
||||
or DMA_MemoryDataSize members depending in the transfer direction. */ |
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */ |
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */ |
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */ |
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */ |
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode. |
||||
@note: The circular buffer mode cannot be used if the memory-to-memory |
||||
data transfer is configured on the selected Channel */ |
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */ |
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */ |
||||
}DMA_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ |
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5)) |
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) |
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) |
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ |
||||
((DIR) == DMA_DIR_PeripheralSRC)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) |
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ |
||||
((STATE) == DMA_PeripheralInc_Disable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) |
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ |
||||
((STATE) == DMA_MemoryInc_Disable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) |
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) |
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ |
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) |
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) |
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ |
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020) |
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000) |
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) |
||||
#define DMA_Priority_High ((uint32_t)0x00002000) |
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000) |
||||
#define DMA_Priority_Low ((uint32_t)0x00000000) |
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ |
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000) |
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000) |
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002) |
||||
#define DMA_IT_HT ((uint32_t)0x00000004) |
||||
#define DMA_IT_TE ((uint32_t)0x00000008) |
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) |
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001) |
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002) |
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004) |
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008) |
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010) |
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020) |
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040) |
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080) |
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100) |
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200) |
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400) |
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800) |
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000) |
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000) |
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000) |
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000) |
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000) |
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000) |
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000) |
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000) |
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000) |
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000) |
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000) |
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000) |
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000) |
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000) |
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000) |
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000) |
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001) |
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002) |
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004) |
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008) |
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010) |
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020) |
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040) |
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080) |
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100) |
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200) |
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400) |
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800) |
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000) |
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000) |
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000) |
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000) |
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000) |
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000) |
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000) |
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000) |
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) |
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ |
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{ |
||||
*/ |
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) |
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) |
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) |
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) |
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) |
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) |
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) |
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) |
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) |
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) |
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) |
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) |
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) |
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) |
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) |
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) |
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) |
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) |
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) |
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) |
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) |
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) |
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) |
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) |
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) |
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) |
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) |
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) |
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) |
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) |
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) |
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) |
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) |
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) |
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) |
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) |
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) |
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) |
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) |
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) |
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) |
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) |
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) |
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) |
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) |
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) |
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) |
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) |
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) |
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ |
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); |
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); |
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); |
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); |
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); |
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); |
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); |
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG); |
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT); |
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__STM32F10x_DMA_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,184 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_exti.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the EXTI firmware |
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_EXTI_H |
||||
#define __STM32F10x_EXTI_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{ |
||||
EXTI_Mode_Interrupt = 0x00, |
||||
EXTI_Mode_Event = 0x04 |
||||
}EXTIMode_TypeDef; |
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) |
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{ |
||||
EXTI_Trigger_Rising = 0x08, |
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10 |
||||
}EXTITrigger_TypeDef; |
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ |
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling)) |
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */ |
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */ |
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */ |
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ |
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ |
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ |
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ |
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ |
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ |
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ |
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ |
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ |
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ |
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ |
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ |
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ |
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ |
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ |
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ |
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ |
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS |
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ |
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) |
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ |
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void EXTI_DeInit(void); |
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); |
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); |
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); |
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); |
||||
void EXTI_ClearFlag(uint32_t EXTI_Line); |
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); |
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_EXTI_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,426 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_flash.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_FLASH_H |
||||
#define __STM32F10x_FLASH_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{
|
||||
FLASH_BUSY = 1, |
||||
FLASH_ERROR_PG, |
||||
FLASH_ERROR_WRP, |
||||
FLASH_COMPLETE, |
||||
FLASH_TIMEOUT |
||||
}FLASH_Status; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ |
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ |
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ |
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ |
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Half_Cycle_Enable_Disable
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ |
||||
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ |
||||
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ |
||||
((STATE) == FLASH_HalfCycleAccess_Disable))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Prefetch_Buffer_Enable_Disable
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ |
||||
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ |
||||
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ |
||||
((STATE) == FLASH_PrefetchBuffer_Disable))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Values to be used with STM32 Low and Medium density devices */ |
||||
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ |
||||
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ |
||||
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ |
||||
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ |
||||
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ |
||||
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ |
||||
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ |
||||
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ |
||||
|
||||
/* Values to be used with STM32 Medium-density devices */ |
||||
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ |
||||
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ |
||||
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ |
||||
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ |
||||
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ |
||||
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ |
||||
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ |
||||
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ |
||||
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ |
||||
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ |
||||
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ |
||||
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ |
||||
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ |
||||
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ |
||||
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ |
||||
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ |
||||
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ |
||||
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ |
||||
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ |
||||
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ |
||||
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ |
||||
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ |
||||
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ |
||||
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ |
||||
|
||||
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ |
||||
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 0 to 1 */ |
||||
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 2 to 3 */ |
||||
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 4 to 5 */ |
||||
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 6 to 7 */ |
||||
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 8 to 9 */ |
||||
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 10 to 11 */ |
||||
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 12 to 13 */ |
||||
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 14 to 15 */ |
||||
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 16 to 17 */ |
||||
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 18 to 19 */ |
||||
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 20 to 21 */ |
||||
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 22 to 23 */ |
||||
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 24 to 25 */ |
||||
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 26 to 27 */ |
||||
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 28 to 29 */ |
||||
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 30 to 31 */ |
||||
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 32 to 33 */ |
||||
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 34 to 35 */ |
||||
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 36 to 37 */ |
||||
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 38 to 39 */ |
||||
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 40 to 41 */ |
||||
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 42 to 43 */ |
||||
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 44 to 45 */ |
||||
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 46 to 47 */ |
||||
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 48 to 49 */ |
||||
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 50 to 51 */ |
||||
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 52 to 53 */ |
||||
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 54 to 55 */ |
||||
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 56 to 57 */ |
||||
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 58 to 59 */ |
||||
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: |
||||
Write protection of page 60 to 61 */ |
||||
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ |
||||
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ |
||||
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ |
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ |
||||
|
||||
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) |
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) |
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ |
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ |
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ |
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ |
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ |
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ |
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) |
||||
|
||||
#ifdef STM32F10X_XL |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/** @defgroup FLASH_Boot
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position |
||||
and this parameter is selected the device will boot from Bank1(Default) */ |
||||
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position |
||||
and this parameter is selected the device will boot from Bank 2 or Bank 1, |
||||
depending on the activation of the bank */ |
||||
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) |
||||
#endif |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{ |
||||
*/ |
||||
#ifdef STM32F10X_XL |
||||
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ |
||||
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ |
||||
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ |
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ |
||||
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ |
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ |
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) |
||||
#else |
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ |
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ |
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ |
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ |
||||
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{ |
||||
*/ |
||||
#ifdef STM32F10X_XL |
||||
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ |
||||
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ |
||||
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ |
||||
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ |
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ |
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ |
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ |
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ |
||||
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ |
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ |
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ |
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ |
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ |
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) |
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ |
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR)|| \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) |
||||
#else |
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ |
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ |
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ |
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ |
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ |
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ |
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ |
||||
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ |
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ |
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) |
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ |
||||
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTERR)) |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/*------------ Functions used for all STM32F10x devices -----*/ |
||||
void FLASH_SetLatency(uint32_t FLASH_Latency); |
||||
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); |
||||
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); |
||||
void FLASH_Unlock(void); |
||||
void FLASH_Lock(void); |
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address); |
||||
FLASH_Status FLASH_EraseAllPages(void); |
||||
FLASH_Status FLASH_EraseOptionBytes(void); |
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); |
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); |
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); |
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); |
||||
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); |
||||
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); |
||||
uint32_t FLASH_GetUserOptionByte(void); |
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void); |
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void); |
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void); |
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); |
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); |
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG); |
||||
FLASH_Status FLASH_GetStatus(void); |
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); |
||||
|
||||
/*------------ New function used for all STM32F10x devices -----*/ |
||||
void FLASH_UnlockBank1(void); |
||||
void FLASH_LockBank1(void); |
||||
FLASH_Status FLASH_EraseAllBank1Pages(void); |
||||
FLASH_Status FLASH_GetBank1Status(void); |
||||
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); |
||||
|
||||
#ifdef STM32F10X_XL |
||||
/*---- New Functions used only with STM32F10x_XL density devices -----*/ |
||||
void FLASH_UnlockBank2(void); |
||||
void FLASH_LockBank2(void); |
||||
FLASH_Status FLASH_EraseAllBank2Pages(void); |
||||
FLASH_Status FLASH_GetBank2Status(void); |
||||
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); |
||||
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); |
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_FLASH_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,733 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_fsmc.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_FSMC_H |
||||
#define __STM32F10x_FSMC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF. |
||||
@note: It is not used with synchronous NOR Flash memories. */ |
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time. |
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories.*/ |
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time. |
||||
This parameter can be a value between 0 and 0xFF. |
||||
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ |
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround. |
||||
This parameter can be a value between 0 and 0xF. |
||||
@note: It is only used for multiplexed NOR Flash memories. */ |
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF. |
||||
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ |
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data. |
||||
The value of this parameter depends on the memory type as shown below: |
||||
- It must be set to 0 in case of a CRAM |
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses |
||||
- It may assume a value between 0 and 0xF in NOR Flash memories |
||||
with synchronous burst mode enable */ |
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */ |
||||
}FSMC_NORSRAMTimingInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank. |
||||
This parameter can be a value of @ref FSMC_Memory_Type */ |
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */ |
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories. |
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories. |
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */ |
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode. |
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode. |
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */ |
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state, |
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */ |
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */ |
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */ |
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */ |
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief Timing parameters For FSMC NAND and PCCARD Banks |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access |
||||
to common/Attribute or I/O memory space (depending on |
||||
the memory space timing to be configured). |
||||
This parameter can be a value between 0 and 0xFF.*/ |
||||
|
||||
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to |
||||
common/Attribute or I/O memory space (depending on the |
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */ |
||||
|
||||
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion |
||||
for NAND-Flash read or write access to common/Attribute |
||||
or I/O memory space (depending on the memory space timing |
||||
to be configured). |
||||
This parameter can be a number between 0x00 and 0xFF */ |
||||
|
||||
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash |
||||
write access to common/Attribute or I/O memory space (depending |
||||
on the memory space timing to be configured). |
||||
This parameter can be a number between 0x00 and 0xFF */ |
||||
}FSMC_NAND_PCCARDTimingInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief FSMC NAND Init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NAND_Bank */ |
||||
|
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */ |
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref FSMC_Data_Width */ |
||||
|
||||
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref FSMC_ECC */ |
||||
|
||||
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low. |
||||
This parameter can be a value between 0 and 0xFF. */ |
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low. |
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ |
||||
}FSMC_NANDInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief FSMC PCCARD Init structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref FSMC_Wait_feature */ |
||||
|
||||
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low. |
||||
This parameter can be a value between 0 and 0xFF. */ |
||||
|
||||
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low. |
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ |
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||
|
||||
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||
}FSMC_PCCARDInitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{ |
||||
*/ |
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) |
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) |
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) |
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_NAND_Bank
|
||||
* @{ |
||||
*/
|
||||
#define FSMC_Bank2_NAND ((uint32_t)0x00000010) |
||||
#define FSMC_Bank3_NAND ((uint32_t)0x00000100) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_PCCARD_Bank
|
||||
* @{ |
||||
*/
|
||||
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ |
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4)) |
||||
|
||||
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
||||
((BANK) == FSMC_Bank3_NAND)) |
||||
|
||||
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD)) |
||||
|
||||
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
||||
((BANK) == FSMC_Bank3_NAND) || \
|
||||
((BANK) == FSMC_Bank4_PCCARD)) |
||||
|
||||
/** @defgroup NOR_SRAM_Controller
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) |
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ |
||||
((MUX) == FSMC_DataAddressMux_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) |
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) |
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) |
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ |
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) |
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) |
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ |
||||
((WIDTH) == FSMC_MemoryDataWidth_16b)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) |
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ |
||||
((STATE) == FSMC_BurstAccessMode_Enable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{ |
||||
*/ |
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) |
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ |
||||
((STATE) == FSMC_AsynchronousWait_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) |
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) |
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ |
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) |
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ |
||||
((MODE) == FSMC_WrapMode_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) |
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) |
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ |
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) |
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ |
||||
((OPERATION) == FSMC_WriteOperation_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) |
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ |
||||
((SIGNAL) == FSMC_WaitSignal_Enable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) |
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ |
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) |
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ |
||||
((BURST) == FSMC_WriteBurst_Enable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000) |
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000) |
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000) |
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000) |
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ |
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup NAND_PCCARD_Controller
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wait_feature
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) |
||||
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ |
||||
((FEATURE) == FSMC_Waitfeature_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup FSMC_ECC
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_ECC_Disable ((uint32_t)0x00000000) |
||||
#define FSMC_ECC_Enable ((uint32_t)0x00000040) |
||||
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ |
||||
((STATE) == FSMC_ECC_Enable)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_ECC_Page_Size
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) |
||||
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) |
||||
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) |
||||
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) |
||||
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) |
||||
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) |
||||
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ |
||||
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||
((SIZE) == FSMC_ECCPageSize_8192Bytes)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_TCLR_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_TAR_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Wait_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Hold_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_HiZ_Setup_Time
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Interrupt_sources
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) |
||||
#define FSMC_IT_Level ((uint32_t)0x00000010) |
||||
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) |
||||
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) |
||||
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ |
||||
((IT) == FSMC_IT_Level) || \
|
||||
((IT) == FSMC_IT_FallingEdge))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Flags
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) |
||||
#define FSMC_FLAG_Level ((uint32_t)0x00000002) |
||||
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) |
||||
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) |
||||
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ |
||||
((FLAG) == FSMC_FLAG_Level) || \
|
||||
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||
((FLAG) == FSMC_FLAG_FEMPT)) |
||||
|
||||
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FSMC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); |
||||
void FSMC_NANDDeInit(uint32_t FSMC_Bank); |
||||
void FSMC_PCCARDDeInit(void); |
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
||||
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); |
||||
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); |
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
||||
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); |
||||
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); |
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
||||
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
||||
void FSMC_PCCARDCmd(FunctionalState NewState); |
||||
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
||||
uint32_t FSMC_GetECC(uint32_t FSMC_Bank); |
||||
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); |
||||
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); |
||||
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); |
||||
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); |
||||
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__STM32F10x_FSMC_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,385 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_gpio.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_GPIO_H |
||||
#define __STM32F10x_GPIO_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ |
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG)) |
||||
|
||||
/**
|
||||
* @brief Output Maximum frequency selection
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{
|
||||
GPIO_Speed_10MHz = 1, |
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_50MHz |
||||
}GPIOSpeed_TypeDef; |
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ |
||||
((SPEED) == GPIO_Speed_50MHz)) |
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{ GPIO_Mode_AIN = 0x0, |
||||
GPIO_Mode_IN_FLOATING = 0x04, |
||||
GPIO_Mode_IPD = 0x28, |
||||
GPIO_Mode_IPU = 0x48, |
||||
GPIO_Mode_Out_OD = 0x14, |
||||
GPIO_Mode_Out_PP = 0x10, |
||||
GPIO_Mode_AF_OD = 0x1C, |
||||
GPIO_Mode_AF_PP = 0x18 |
||||
}GPIOMode_TypeDef; |
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ |
||||
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
|
||||
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
|
||||
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) |
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */ |
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */ |
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */ |
||||
}GPIO_InitTypeDef; |
||||
|
||||
|
||||
/**
|
||||
* @brief Bit_SET and Bit_RESET enumeration
|
||||
*/ |
||||
|
||||
typedef enum |
||||
{ Bit_RESET = 0, |
||||
Bit_SET |
||||
}BitAction; |
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ |
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ |
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ |
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ |
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ |
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ |
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ |
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ |
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ |
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ |
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ |
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ |
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ |
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ |
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ |
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ |
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ |
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) |
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ |
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Remap_define
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ |
||||
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ |
||||
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ |
||||
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ |
||||
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ |
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ |
||||
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ |
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ |
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ |
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ |
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ |
||||
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ |
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ |
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ |
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ |
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ |
||||
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ |
||||
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ |
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ |
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ |
||||
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ |
||||
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ |
||||
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ |
||||
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ |
||||
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ |
||||
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ |
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ |
||||
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ |
||||
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected |
||||
to TIM2 Internal Trigger 1 for calibration |
||||
(only for Connectivity line devices) */ |
||||
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ |
||||
|
||||
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ |
||||
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ |
||||
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ |
||||
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ |
||||
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ |
||||
|
||||
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ |
||||
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ |
||||
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ |
||||
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ |
||||
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ |
||||
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ |
||||
|
||||
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ |
||||
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ |
||||
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, |
||||
only for High density Value line devices) */
|
||||
|
||||
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ |
||||
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
|
||||
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
|
||||
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
|
||||
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
|
||||
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
|
||||
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
|
||||
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
|
||||
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
|
||||
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
|
||||
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
|
||||
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
|
||||
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
|
||||
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
|
||||
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
|
||||
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
|
||||
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
|
||||
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
|
||||
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Port_Sources
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00) |
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01) |
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02) |
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03) |
||||
#define GPIO_PortSourceGPIOE ((uint8_t)0x04) |
||||
#define GPIO_PortSourceGPIOF ((uint8_t)0x05) |
||||
#define GPIO_PortSourceGPIOG ((uint8_t)0x06) |
||||
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ |
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE)) |
||||
|
||||
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ |
||||
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == GPIO_PortSourceGPIOG)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00) |
||||
#define GPIO_PinSource1 ((uint8_t)0x01) |
||||
#define GPIO_PinSource2 ((uint8_t)0x02) |
||||
#define GPIO_PinSource3 ((uint8_t)0x03) |
||||
#define GPIO_PinSource4 ((uint8_t)0x04) |
||||
#define GPIO_PinSource5 ((uint8_t)0x05) |
||||
#define GPIO_PinSource6 ((uint8_t)0x06) |
||||
#define GPIO_PinSource7 ((uint8_t)0x07) |
||||
#define GPIO_PinSource8 ((uint8_t)0x08) |
||||
#define GPIO_PinSource9 ((uint8_t)0x09) |
||||
#define GPIO_PinSource10 ((uint8_t)0x0A) |
||||
#define GPIO_PinSource11 ((uint8_t)0x0B) |
||||
#define GPIO_PinSource12 ((uint8_t)0x0C) |
||||
#define GPIO_PinSource13 ((uint8_t)0x0D) |
||||
#define GPIO_PinSource14 ((uint8_t)0x0E) |
||||
#define GPIO_PinSource15 ((uint8_t)0x0F) |
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ |
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup Ethernet_Media_Interface
|
||||
* @{ |
||||
*/
|
||||
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) |
||||
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) |
||||
|
||||
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ |
||||
((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx); |
||||
void GPIO_AFIODeInit(void); |
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); |
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); |
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); |
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); |
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); |
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); |
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); |
||||
void GPIO_EventOutputCmd(FunctionalState NewState); |
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); |
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); |
||||
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F10x_GPIO_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,684 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f10x_i2c.h |
||||
* @author MCD Application Team |
||||
* @version V3.5.0 |
||||
* @date 11-March-2011 |
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||||
* |
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F10x_I2C_H |
||||
#define __STM32F10x_I2C_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f10x.h" |
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup I2C
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Exported_Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */ |
||||
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */ |
||||
|
||||
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ |
||||
|
||||
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */ |
||||
|
||||
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */ |
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */ |
||||
}I2C_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ |
||||
((PERIPH) == I2C2)) |
||||
/** @defgroup I2C_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000) |
||||
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) |
||||
#define I2C_Mode_SMBusHost ((uint16_t)0x000A) |
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ |
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ |
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ |
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ |
||||
((CYCLE) == I2C_DutyCycle_2)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400) |
||||
#define I2C_Ack_Disable ((uint16_t)0x0000) |
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ |
||||
((STATE) == I2C_Ack_Disable)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00) |
||||
#define I2C_Direction_Receiver ((uint8_t)0x01) |
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ |
||||
((DIRECTION) == I2C_Direction_Receiver)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) |
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) |
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ |
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00) |
||||
#define I2C_Register_CR2 ((uint8_t)0x04) |
||||
#define I2C_Register_OAR1 ((uint8_t)0x08) |
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C) |
||||
#define I2C_Register_DR ((uint8_t)0x10) |
||||
#define I2C_Register_SR1 ((uint8_t)0x14) |
||||
#define I2C_Register_SR2 ((uint8_t)0x18) |
||||
#define I2C_Register_CCR ((uint8_t)0x1C) |
||||
#define I2C_Register_TRISE ((uint8_t)0x20) |
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ |
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_CCR) || \
|
||||
((REGISTER) == I2C_Register_TRISE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_SMBusAlert_Low ((uint16_t)0x2000) |
||||
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) |
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ |
||||
((ALERT) == I2C_SMBusAlert_High)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800) |
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF) |
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ |
||||
((POSITION) == I2C_PECPosition_Current)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup I2C_NCAK_position
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800) |
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) |
||||
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ |
||||
((POSITION) == I2C_NACKPosition_Current)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400) |
||||
#define I2C_IT_EVT ((uint16_t)0x0200) |
||||
#define I2C_IT_ERR ((uint16_t)0x0100) |
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define I2C_IT_SMBALERT ((uint32_t)0x01008000) |
||||
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) |
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000) |
||||
#define I2C_IT_OVR ((uint32_t)0x01000800) |
||||
#define I2C_IT_AF ((uint32_t)0x01000400) |
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200) |
||||
#define I2C_IT_BERR ((uint32_t)0x01000100) |
||||
#define I2C_IT_TXE ((uint32_t)0x06000080) |
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040) |
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010) |
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008) |
||||
#define I2C_IT_BTF ((uint32_t)0x02000004) |
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002) |
||||
#define I2C_IT_SB ((uint32_t)0x02000001) |
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) |
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ |
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief SR2 register flags
|
||||
*/ |
||||
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000) |
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) |
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) |
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) |
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000) |
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000) |
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000) |
||||
|
||||
/**
|
||||
* @brief SR1 register flags
|
||||
*/ |
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) |
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) |
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000) |
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800) |
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400) |
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200) |
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100) |
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080) |
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040) |
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010) |
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) |
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004) |
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002) |
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001) |
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) |
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ |
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{ |
||||
*/ |
||||
|
||||
/*========================================
|
||||
|
||||
I2C Master Events (Events grouped in order of communication) |
||||
==========================================*/ |
||||
/**
|
||||
* @brief Communication start |
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating). |
||||
*
|
||||
*/ |
||||
/* --EV5 */ |
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ |
||||
|
||||
/**
|
||||
* @brief Address Acknowledge |
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set: |
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set. |
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set |
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/ |
||||
|
||||
/* --EV6 */ |
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ |
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ |
||||
/* --EV9 */ |
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ |
||||
|
||||
/**
|
||||
* @brief Communication events |
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures: |
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function). |
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2. |
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out. |
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus. |
||||
* In most cases, using EV8 is sufficient for the application. |
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test. |
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation). |
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). |
||||
* In this case the communication may be slower. |
||||
*
|
||||
*/ |
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */ |
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ |
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/ |
||||
/* --EV8 */ |
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ |
||||
/* --EV8_2 */ |
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ |
||||
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Slave Events (Events grouped in order of communication) |
||||
==========================================*/ |
||||
|
||||
/**
|
||||
* @brief Communication start events |
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_AcknowledgeConfig()) and the events listed above are set : |
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER). |
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set. |
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/ |
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */ |
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ |
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ |
||||
|
||||
/* 2) Case of Dual address managed by the slave */ |
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ |
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ |
||||
|
||||
/* 3) Case of General Call enabled for the slave */ |
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ |
||||
|
||||
/**
|
||||
* @brief Communication events |
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode: |
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped. |
||||
*
|
||||
* - Slave Transmitter mode: |
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and |
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the |
||||
* current byte end of transfer. |
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus. |
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). |
||||
* In this case the communication may be slower. |
||||
* |
||||
*/ |
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */ |
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ |
||||
/* --EV4 */ |
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ |
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/ |
||||
/* --EV3 */ |
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ |
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ |
||||
/* --EV3_2 */ |
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ |
||||
|
||||
/*=========================== End of Events Description ==========================================*/ |
||||
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ |
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_clock_speed
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx); |
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); |
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); |
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); |
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); |
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); |
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); |
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); |
||||
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); |
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); |
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); |
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); |
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); |
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); |
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); |
||||
|
||||
/**
|
||||
* @brief |
||||
**************************************************************************************** |
||||
* |
||||
* I2C State Monitoring Functions |
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring |
||||
* depending on the application requirements and constraints: |
||||
*
|
||||
*
|
||||
* 1) Basic state monitoring: |
||||
* Using I2C_CheckEvent() function: |
||||
* It compares the status registers (SR1 and SR2) content to a given event |
||||
* (can be the combination of one or more flags). |
||||
* It returns SUCCESS if the current status includes the given flags
|
||||
* and returns ERROR if one or more flags are missing in the current status. |
||||
* - When to use: |
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (RM0008). |
||||
* - It is also suitable for users who need to define their own events. |
||||
* - Limitations: |
||||
* - If an error occurs (ie. error flags are set besides to the monitored flags), |
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication |
||||
* hold or corrupted real state.
|
||||
* In this case, it is advised to use error interrupts to monitor the error |
||||
* events and handle them in the interrupt IRQ handler. |
||||
*
|
||||
* @note
|
||||
* For error management, it is advised to use the following functions: |
||||
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). |
||||
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. |
||||
* Where x is the peripheral instance (I2C1, I2C2 ...) |
||||
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() |
||||
* in order to determine which error occurred. |
||||
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() |
||||
* and/or I2C_GenerateStop() in order to clear the error flag and source, |
||||
* and return to correct communication status. |
||||
*
|
||||
* |
||||
* 2) Advanced state monitoring: |
||||
* Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
* by 16 bits and concatenated to Status Register 1). |
||||
* - When to use: |
||||
* - This function is suitable for the same applications above but it allows to |
||||
* overcome the limitations of I2C_GetFlagStatus() function (see below). |
||||
* The returned value could be compared to events already defined in the
|
||||
* library (stm32f10x_i2c.h) or to custom values defined by user. |
||||
* - This function is suitable when multiple flags are monitored at the same time. |
||||
* - At the opposite of I2C_CheckEvent() function, this function allows user to |
||||
* choose when an event is accepted (when all events flags are set and no
|
||||
* other flags are set or just when the needed flags are set like
|
||||
* I2C_CheckEvent() function). |
||||
* - Limitations: |
||||
* - User may need to define his own events. |
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags). |
||||
*
|
||||
* |
||||
* 3) Flag-based state monitoring: |
||||
* Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
* one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
* - When to use: |
||||
* - This function could be used for specific applications or in debug phase. |
||||
* - It is suitable when only one flag checking is needed (most I2C events
|
||||
* are monitored through multiple flags). |
||||
* - Limitations:
|
||||
* - When calling this function, the Status register is accessed. Some flags are |
||||
* cleared when the status register is accessed. So checking the status |
||||
* of one Flag, may clear other ones. |
||||
* - Function may need to be called twice or more in order to monitor one
|
||||
* single event. |
||||
*
|
||||
*/ |
||||
|
||||
/**
|
||||
*
|
||||
* 1) Basic state monitoring |
||||
******************************************************************************* |
||||
*/ |
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); |
||||
/**
|
||||
*
|
||||
* 2) Advanced state monitoring |
||||
******************************************************************************* |
||||
*/ |
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); |
||||
/**
|
||||
*
|
||||
* 3) Flag-based state monitoring |
||||
********************** | ||||