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343 lines
10 KiB
343 lines
10 KiB
/**
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******************************************************************************
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* @file stm8s_itc.c
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* @author MCD Application Team
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* @version V2.2.0
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* @date 30-September-2014
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* @brief This file contains all the functions for the ITC peripheral.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm8s_itc.h"
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/** @addtogroup STM8S_StdPeriph_Driver
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup ITC_Private_Functions
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* @{
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*/
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/**
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* @brief Utility function used to read CC register.
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* @param None
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* @retval CPU CC register value
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*/
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uint8_t ITC_GetCPUCC(void)
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{
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#ifdef _COSMIC_
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_asm("push cc");
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_asm("pop a");
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return; /* Ignore compiler warning, the returned value is in A register */
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#elif defined _RAISONANCE_ /* _RAISONANCE_ */
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return _getCC_();
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#else /* _IAR_ */
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asm("push cc");
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asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
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#endif /* _COSMIC_*/
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}
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/**
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* @}
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*/
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/* Public functions ----------------------------------------------------------*/
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/** @addtogroup ITC_Public_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the ITC registers to their default reset value.
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* @param None
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* @retval None
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*/
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void ITC_DeInit(void)
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{
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ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
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ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
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}
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/**
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* @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
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* @param None
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* @retval The interrupt software priority bits value.
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*/
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uint8_t ITC_GetSoftIntStatus(void)
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{
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return (uint8_t)(ITC_GetCPUCC() & CPU_CC_I1I0);
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}
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/**
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* @brief Gets the software priority of the specified interrupt source.
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* @param IrqNum : Specifies the peripheral interrupt source.
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* @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.
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*/
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ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
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{
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uint8_t Value = 0;
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uint8_t Mask = 0;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
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/* Define the mask corresponding to the bits position in the SPR register */
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Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U));
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switch (IrqNum)
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{
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case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
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case ITC_IRQ_AWU:
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case ITC_IRQ_CLK:
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case ITC_IRQ_PORTA:
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Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_PORTB:
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case ITC_IRQ_PORTC:
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case ITC_IRQ_PORTD:
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case ITC_IRQ_PORTE:
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Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
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break;
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#if defined(STM8S208) || defined(STM8AF52Ax)
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case ITC_IRQ_CAN_RX:
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case ITC_IRQ_CAN_TX:
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#endif /*STM8S208 or STM8AF52Ax */
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#if defined(STM8S903) || defined(STM8AF622x)
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case ITC_IRQ_PORTF:
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#endif /*STM8S903 or STM8AF622x */
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case ITC_IRQ_SPI:
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case ITC_IRQ_TIM1_OVF:
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Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_TIM1_CAPCOM:
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#if defined (STM8S903) || defined (STM8AF622x)
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case ITC_IRQ_TIM5_OVFTRI:
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case ITC_IRQ_TIM5_CAPCOM:
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#else
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case ITC_IRQ_TIM2_OVF:
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case ITC_IRQ_TIM2_CAPCOM:
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#endif /* STM8S903 or STM8AF622x*/
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case ITC_IRQ_TIM3_OVF:
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Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_TIM3_CAPCOM:
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#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
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defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
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case ITC_IRQ_UART1_TX:
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case ITC_IRQ_UART1_RX:
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#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
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#if defined(STM8AF622x)
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case ITC_IRQ_UART4_TX:
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case ITC_IRQ_UART4_RX:
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#endif /*STM8AF622x */
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case ITC_IRQ_I2C:
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Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
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break;
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#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
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case ITC_IRQ_UART2_TX:
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case ITC_IRQ_UART2_RX:
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#endif /*STM8S105 or STM8AF626x*/
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#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
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defined(STM8AF62Ax)
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case ITC_IRQ_UART3_TX:
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case ITC_IRQ_UART3_RX:
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case ITC_IRQ_ADC2:
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#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
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#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
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defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x)
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case ITC_IRQ_ADC1:
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#endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S903 or STM8AF626x or STM8AF622x */
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#if defined (STM8S903) || defined (STM8AF622x)
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case ITC_IRQ_TIM6_OVFTRI:
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#else
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case ITC_IRQ_TIM4_OVF:
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#endif /*STM8S903 or STM8AF622x */
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Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
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break;
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case ITC_IRQ_EEPROM_EEC:
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Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
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break;
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default:
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break;
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}
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Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u);
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return((ITC_PriorityLevel_TypeDef)Value);
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}
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/**
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* @brief Sets the software priority of the specified interrupt source.
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* @note - The modification of the software priority is only possible when
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* the interrupts are disabled.
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* - The normal behavior is to disable the interrupt before calling
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* this function, and re-enable it after.
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* - The priority level 0 cannot be set (see product specification
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* for more details).
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* @param IrqNum : Specifies the peripheral interrupt source.
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* @param PriorityValue : Specifies the software priority value to set,
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* can be a value of @ref ITC_PriorityLevel_TypeDef .
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* @retval None
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*/
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void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)
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{
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uint8_t Mask = 0;
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uint8_t NewPriority = 0;
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/* Check function parameters */
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assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
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assert_param(IS_ITC_PRIORITY_OK(PriorityValue));
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/* Check if interrupts are disabled */
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assert_param(IS_ITC_INTERRUPTS_DISABLED);
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/* Define the mask corresponding to the bits position in the SPR register */
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/* The mask is reversed in order to clear the 2 bits after more easily */
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Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)));
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/* Define the new priority to write */
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NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U));
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switch (IrqNum)
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{
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case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */
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case ITC_IRQ_AWU:
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case ITC_IRQ_CLK:
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case ITC_IRQ_PORTA:
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ITC->ISPR1 &= Mask;
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ITC->ISPR1 |= NewPriority;
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break;
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case ITC_IRQ_PORTB:
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case ITC_IRQ_PORTC:
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case ITC_IRQ_PORTD:
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case ITC_IRQ_PORTE:
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ITC->ISPR2 &= Mask;
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ITC->ISPR2 |= NewPriority;
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break;
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#if defined(STM8S208) || defined(STM8AF52Ax)
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case ITC_IRQ_CAN_RX:
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case ITC_IRQ_CAN_TX:
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#endif /*STM8S208 or STM8AF52Ax */
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#if defined(STM8S903) || defined(STM8AF622x)
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case ITC_IRQ_PORTF:
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#endif /*STM8S903 or STM8AF622x */
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case ITC_IRQ_SPI:
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case ITC_IRQ_TIM1_OVF:
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ITC->ISPR3 &= Mask;
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ITC->ISPR3 |= NewPriority;
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break;
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case ITC_IRQ_TIM1_CAPCOM:
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#if defined(STM8S903) || defined(STM8AF622x)
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case ITC_IRQ_TIM5_OVFTRI:
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case ITC_IRQ_TIM5_CAPCOM:
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#else
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case ITC_IRQ_TIM2_OVF:
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case ITC_IRQ_TIM2_CAPCOM:
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#endif /*STM8S903 or STM8AF622x */
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case ITC_IRQ_TIM3_OVF:
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ITC->ISPR4 &= Mask;
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ITC->ISPR4 |= NewPriority;
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break;
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case ITC_IRQ_TIM3_CAPCOM:
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#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
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defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
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case ITC_IRQ_UART1_TX:
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case ITC_IRQ_UART1_RX:
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#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
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#if defined(STM8AF622x)
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case ITC_IRQ_UART4_TX:
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case ITC_IRQ_UART4_RX:
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#endif /*STM8AF622x */
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case ITC_IRQ_I2C:
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ITC->ISPR5 &= Mask;
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ITC->ISPR5 |= NewPriority;
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break;
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#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
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case ITC_IRQ_UART2_TX:
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case ITC_IRQ_UART2_RX:
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#endif /*STM8S105 or STM8AF626x */
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#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
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defined(STM8AF62Ax)
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case ITC_IRQ_UART3_TX:
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case ITC_IRQ_UART3_RX:
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case ITC_IRQ_ADC2:
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#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
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#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
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defined(STM8S903) || defined(STM8AF626x) || defined (STM8AF622x)
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case ITC_IRQ_ADC1:
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#endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S903 or STM8AF626x or STM8AF622x */
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#if defined (STM8S903) || defined (STM8AF622x)
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case ITC_IRQ_TIM6_OVFTRI:
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#else
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case ITC_IRQ_TIM4_OVF:
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#endif /* STM8S903 or STM8AF622x */
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ITC->ISPR6 &= Mask;
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ITC->ISPR6 |= NewPriority;
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break;
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case ITC_IRQ_EEPROM_EEC:
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ITC->ISPR7 &= Mask;
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ITC->ISPR7 |= NewPriority;
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break;
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default:
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break;
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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