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345 lines
8.0 KiB
345 lines
8.0 KiB
/*
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* Fitipower FC0012 tuner driver
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*
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* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
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*
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* modified for use in librtlsdr
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* Copyright (C) 2012 Steve Markgraf <steve@steve-m.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "rtlsdr_i2c.h"
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#include "tuner_fc0012.h"
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static int fc0012_writereg(void *dev, uint8_t reg, uint8_t val)
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{
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uint8_t data[2];
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data[0] = reg;
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data[1] = val;
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if (rtlsdr_i2c_write_fn(dev, FC0012_I2C_ADDR, data, 2) < 0)
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return -1;
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return 0;
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}
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static int fc0012_readreg(void *dev, uint8_t reg, uint8_t *val)
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{
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uint8_t data = reg;
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if (rtlsdr_i2c_write_fn(dev, FC0012_I2C_ADDR, &data, 1) < 0)
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return -1;
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if (rtlsdr_i2c_read_fn(dev, FC0012_I2C_ADDR, &data, 1) < 0)
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return -1;
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*val = data;
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return 0;
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}
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/* Incomplete list of register settings:
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*
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* Name Reg Bits Desc
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* CHIP_ID 0x00 0-7 Chip ID (constant 0xA1)
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* RF_A 0x01 0-3 Number of count-to-9 cycles in RF
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* divider (suggested: 2..9)
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* RF_M 0x02 0-7 Total number of cycles (to-8 and to-9)
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* in RF divider
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* RF_K_HIGH 0x03 0-6 Bits 8..14 of fractional divider
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* RF_K_LOW 0x04 0-7 Bits 0..7 of fractional RF divider
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* RF_OUTDIV_A 0x05 3-7 Power of two required?
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* LNA_POWER_DOWN 0x06 0 Set to 1 to switch off low noise amp
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* RF_OUTDIV_B 0x06 1 Set to select 3 instead of 2 for the
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* RF output divider
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* VCO_SPEED 0x06 3 Select tuning range of VCO:
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* 0 = Low range, (ca. 1.1 - 1.5GHz)
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* 1 = High range (ca. 1.4 - 1.8GHz)
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* BANDWIDTH 0x06 6-7 Set bandwidth. 6MHz = 0x80, 7MHz=0x40
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* 8MHz=0x00
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* XTAL_SPEED 0x07 5 Set to 1 for 28.8MHz Crystal input
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* or 0 for 36MHz
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* <agc params> 0x08 0-7
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* EN_CAL_RSSI 0x09 4 Enable calibrate RSSI
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* (Receive Signal Strength Indicator)
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* LNA_FORCE 0x0d 0
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* AGC_FORCE 0x0d ?
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* LNA_GAIN 0x13 3-4 Low noise amp gain
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* LNA_COMPS 0x15 3 ?
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* VCO_CALIB 0x0e 7 Set high then low to calibrate VCO
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* (fast lock?)
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* VCO_VOLTAGE 0x0e 0-6 Read Control voltage of VCO
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* (big value -> low freq)
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*/
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int fc0012_init(void *dev)
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{
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int ret = 0;
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unsigned int i;
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uint8_t reg[] = {
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0x00, /* dummy reg. 0 */
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0x05, /* reg. 0x01 */
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0x10, /* reg. 0x02 */
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0x00, /* reg. 0x03 */
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0x00, /* reg. 0x04 */
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0x0f, /* reg. 0x05: may also be 0x0a */
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0x00, /* reg. 0x06: divider 2, VCO slow */
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0x00, /* reg. 0x07: may also be 0x0f */
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0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
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Loop Bw 1/8 */
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0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
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0xb8, /* reg. 0x0a: Disable LO Test Buffer */
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0x82, /* reg. 0x0b: Output Clock is same as clock frequency,
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may also be 0x83 */
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0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
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0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */
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0x00, /* reg. 0x0e */
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0x00, /* reg. 0x0f */
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0x00, /* reg. 0x10: may also be 0x0d */
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0x00, /* reg. 0x11 */
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0x1f, /* reg. 0x12: Set to maximum gain */
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0x08, /* reg. 0x13: Set to Middle Gain: 0x08,
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Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */
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0x00, /* reg. 0x14 */
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0x04, /* reg. 0x15: Enable LNA COMPS */
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};
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#if 0
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switch (rtlsdr_get_tuner_clock(dev)) {
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case FC_XTAL_27_MHZ:
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case FC_XTAL_28_8_MHZ:
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reg[0x07] |= 0x20;
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break;
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case FC_XTAL_36_MHZ:
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default:
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break;
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}
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#endif
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reg[0x07] |= 0x20;
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// if (priv->dual_master)
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reg[0x0c] |= 0x02;
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for (i = 1; i < sizeof(reg); i++) {
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ret = fc0012_writereg(dev, i, reg[i]);
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if (ret)
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break;
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}
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return ret;
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}
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int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
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{
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int i, ret = 0;
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uint8_t reg[7], am, pm, multi, tmp;
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uint64_t f_vco;
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uint32_t xtal_freq_div_2;
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uint16_t xin, xdiv;
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int vco_select = 0;
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xtal_freq_div_2 = rtlsdr_get_tuner_clock(dev) / 2;
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/* select frequency divider and the frequency of VCO */
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if (freq < 37084000) { /* freq * 96 < 3560000000 */
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multi = 96;
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reg[5] = 0x82;
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reg[6] = 0x00;
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} else if (freq < 55625000) { /* freq * 64 < 3560000000 */
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multi = 64;
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reg[5] = 0x82;
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reg[6] = 0x02;
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} else if (freq < 74167000) { /* freq * 48 < 3560000000 */
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multi = 48;
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reg[5] = 0x42;
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reg[6] = 0x00;
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} else if (freq < 111250000) { /* freq * 32 < 3560000000 */
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multi = 32;
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reg[5] = 0x42;
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reg[6] = 0x02;
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} else if (freq < 148334000) { /* freq * 24 < 3560000000 */
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multi = 24;
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reg[5] = 0x22;
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reg[6] = 0x00;
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} else if (freq < 222500000) { /* freq * 16 < 3560000000 */
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multi = 16;
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reg[5] = 0x22;
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reg[6] = 0x02;
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} else if (freq < 296667000) { /* freq * 12 < 3560000000 */
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multi = 12;
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reg[5] = 0x12;
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reg[6] = 0x00;
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} else if (freq < 445000000) { /* freq * 8 < 3560000000 */
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multi = 8;
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reg[5] = 0x12;
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reg[6] = 0x02;
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} else if (freq < 593334000) { /* freq * 6 < 3560000000 */
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multi = 6;
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reg[5] = 0x0a;
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reg[6] = 0x00;
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} else {
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multi = 4;
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reg[5] = 0x0a;
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reg[6] = 0x02;
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}
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f_vco = freq * multi;
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if (f_vco >= 3060000000U) {
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reg[6] |= 0x08;
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vco_select = 1;
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}
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/* From divided value (XDIV) determined the FA and FP value */
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xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
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if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
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xdiv++;
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pm = (uint8_t)(xdiv / 8);
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am = (uint8_t)(xdiv - (8 * pm));
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if (am < 2) {
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am += 8;
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pm--;
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}
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if (pm > 31) {
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reg[1] = am + (8 * (pm - 31));
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reg[2] = 31;
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} else {
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reg[1] = am;
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reg[2] = pm;
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}
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if ((reg[1] > 15) || (reg[2] < 0x0b)) {
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fprintf(stderr, "[FC0012] no valid PLL combination "
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"found for %u Hz!\n", freq);
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return -1;
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}
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/* fix clock out */
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reg[6] |= 0x20;
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/* From VCO frequency determines the XIN ( fractional part of Delta
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Sigma PLL) and divided value (XDIV) */
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xin = (uint16_t)((f_vco - (f_vco / xtal_freq_div_2) * xtal_freq_div_2) / 1000);
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xin = (xin << 15) / (xtal_freq_div_2 / 1000);
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if (xin >= 16384)
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xin += 32768;
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reg[3] = xin >> 8; /* xin with 9 bit resolution */
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reg[4] = xin & 0xff;
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reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
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switch (bandwidth) {
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case 6000000:
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reg[6] |= 0x80;
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break;
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case 7000000:
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reg[6] |= 0x40;
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break;
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case 8000000:
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default:
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break;
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}
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/* modified for Realtek demod */
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reg[5] |= 0x07;
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for (i = 1; i <= 6; i++) {
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ret = fc0012_writereg(dev, i, reg[i]);
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if (ret)
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goto exit;
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}
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/* VCO Calibration */
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ret = fc0012_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x00);
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/* VCO Re-Calibration if needed */
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x00);
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if (!ret) {
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// msleep(10);
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ret = fc0012_readreg(dev, 0x0e, &tmp);
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}
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if (ret)
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goto exit;
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/* vco selection */
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tmp &= 0x3f;
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if (vco_select) {
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if (tmp > 0x3c) {
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reg[6] &= ~0x08;
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ret = fc0012_writereg(dev, 0x06, reg[6]);
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x00);
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}
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} else {
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if (tmp < 0x02) {
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reg[6] |= 0x08;
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ret = fc0012_writereg(dev, 0x06, reg[6]);
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x80);
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if (!ret)
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ret = fc0012_writereg(dev, 0x0e, 0x00);
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}
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}
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exit:
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return ret;
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}
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int fc0012_set_gain(void *dev, int gain)
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{
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int ret;
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uint8_t tmp = 0;
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ret = fc0012_readreg(dev, 0x13, &tmp);
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/* mask bits off */
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tmp &= 0xe0;
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switch (gain) {
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case -99: /* -9.9 dB */
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tmp |= 0x02;
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break;
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case -40: /* -4 dB */
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break;
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case 71:
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tmp |= 0x08; /* 7.1 dB */
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break;
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case 179:
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tmp |= 0x17; /* 17.9 dB */
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break;
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case 192:
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default:
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tmp |= 0x10; /* 19.2 dB */
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break;
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}
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ret = fc0012_writereg(dev, 0x13, tmp);
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return ret;
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}
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